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* [Support] Format codeRichard Qin2026-10-216-239/+343
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [Utils] Use LLVM format and tidy toolsRichard Qin2026-10-217-322/+2806
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [Support] Add ErrorOr supportRichard Qin2026-10-211-0/+293
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [Support] Add errno supportRichard Qin2026-10-212-0/+140
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [Support] Add compiler abstraction supportRichard Qin2026-10-211-0/+843
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* [CMake] Add RCC platform configuration checksRichard Qin2026-10-2115-0/+3438
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* [CMake] Generate RCC configuration headersRichard Qin2026-10-213-1/+477
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* [RCC] Add Basic Data TypesRichard Qin2026-10-212-0/+102
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [Dev] Configure build presets and code checksRichard Qin2026-10-205-47/+160
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* [CMake] Establish RCC and CFront builds and package exportsRichard Qin2026-10-2019-78/+585
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* [CMake] Add compiler options and target helpersRichard Qin2026-10-205-0/+1407
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* Rename LICENSE to COPYINGRichard Qin2026-10-181-0/+0
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [MIR] Merge identical scalar type branchesRichard-Qin-X2026-08-291-5/+1
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* [RISCV] Merge identical selector casesRichard-Qin-X2026-08-291-2/+0
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* [RISCV] Widen jump table entry size arithmeticRichard-Qin-X2026-08-291-1/+1
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* [RISCV] Reuse validated Zcmp frame offsetsRichard-Qin-X2026-08-291-8/+12
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* [RISCV] Assert merged memory offset invariantsRichard-Qin-X2026-08-291-0/+2
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* [RISCV] Reuse validated move registersRichard-Qin-X2026-08-291-5/+9
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* [GlobalISel] Bind register bank optionals onceRichard-Qin-X2026-08-291-6/+9
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* [GlobalISel] Assert vector element type invariantsRichard-Qin-X2026-08-291-3/+7
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* [CodeGen] Bind virtual register types onceRichard-Qin-X2026-08-291-2/+3
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* [CodeGen] Apply LLVM declaration styleRichard-Qin-X2026-08-293-3/+3
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* [TableGen] Assert normalized MC pseudo operandsRichard-Qin-X2026-08-291-0/+2
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* [TableGen] Preserve optional target description valuesRichard-Qin-X2026-08-292-9/+10
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* [GlobalISel] Remove redundant PHI narrowing checksRichard-Qin-X2026-08-291-12/+7
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* [CodeGen] Complete LaneMask bitwise operationsRichard-Qin-X2026-08-284-17/+19
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* [Support] Use standard power-of-two checksRichard-Qin-X2026-08-288-39/+20
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* [CMake] Remove unused clang-tidy file registrationRichard-Qin-X2026-08-2838-281/+81
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* [RISCV] Complete Zcmp frame lowering and optimizationRichard-Qin-X2026-08-288-210/+439
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* [RISCV] Generate complete Zcmp instruction definitionsRichard-Qin-X2026-08-286-44/+217
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* [CodeGen] Add target machine registryRichard-Qin-X2026-08-2824-233/+735
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* [CodeGen] Separate assembly emission ownershipRichard-Qin-X2026-08-2815-930/+1033
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* [RISCV] Separate calling convention assignmentRichard-Qin-X2026-08-286-479/+566
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* [CodeGen] Separate pass instrumentation ownershipRichard-Qin-X2026-08-287-612/+648
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* [CodeGen] Remove pass instrumentation snapshotsRichard-Qin-X2026-08-282-104/+11
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* [CodeGen] Centralize machine instruction erasureRichard-Qin-X2026-08-2830-474/+148
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* [GlobalISel] Generate floating memory selectionRichard-Qin-X2026-08-279-159/+179
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* [RISCV] Generate atomic RMW selectionRichard-Qin-X2026-08-273-95/+366
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* [RISCV] Remove unused selector helpersRichard-Qin-X2026-08-271-80/+0
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* [GlobalISel] Select each instruction onceRichard-Qin-X2026-08-273-93/+0
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* [CodeGen] Remove machine action replayRichard-Qin-X2026-08-275-214/+16
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* [CodeGen] Run machine optimizations onceRichard-Qin-X2026-08-2713-217/+21
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* [CodeGen] Run scheduling transformations onceRichard-Qin-X2026-08-267-138/+30
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* [CodeGen] Remove transactional register allocationRichard-Qin-X2026-08-269-174/+47
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* [CodeGen] Run SSA exit transformations onceRichard-Qin-X2026-08-264-57/+22
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* [GlobalISel] Run machine transformations onceRichard-Qin-X2026-08-266-78/+20
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* [CodeGen] Centralize machine pass property validationRichard-Qin-X2026-08-2624-169/+0
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* [RISCV] Implement push-pop optimizationRichard-Qin-X2026-08-2610-27/+318
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* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-2610-5/+667
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* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-2610-43/+554
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generated by cgit v1.2.3 (git 2.46.0) at 2026-11-09 22:48:01 +0000