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| * CSR unit and testsRichard Qin2026-03-195-10/+893
| * M/S/U Mode csr pakageRichard Qin2026-03-181-0/+110
| * Add fibonacci tests and fix bugsRichard Qin2026-03-183-8/+77
| * fixed vm_trace bugRichard Qin2026-03-181-6/+6
| * CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-185-8/+1252
| * Hazard unit and testsRichard Qin2026-03-183-0/+446
| * Merge pull request #3 from Richard-Qin-001/fix/wb-stage-review-99385726772028...Richard Qin2026-03-182-17/+25
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| | * test(core): fix WB stage tests after naming and logic refactorRichard Qin2026-03-171-5/+8
| | * refactor(core): address WB stage architectural and naming review feedbackRichard Qin2026-03-171-12/+17
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| * Write Back stage unit and testsRichard Qin2026-03-183-0/+240
| * Merge pull request #2 from Richard-Qin-001/audit-report-fixes-180556562870443...Richard Qin2026-03-186-29/+29
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| | * Merge branch 'main' into audit-report-fixes-18055656287044378367Richard Qin2026-03-180-0/+0
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| * | Memory Stage and MEM/WB pipeline stage registerRichard Qin2026-03-185-0/+739
| * | fix known bugsRichard Qin2026-03-176-21/+68
| * | EX/MEM Pipeline Register unit and testsRichard Qin2026-03-177-2/+386
| | * docs: Finalized Richard CPU RTL architectural and naming convention audit rep...Richard Qin2026-03-1713-20/+1190
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| * Execute Stage unit and testsRichard Qin2026-03-173-0/+343
| * ID/EX Pipeline Register and testsRichard Qin2026-03-173-0/+354
| * IF/ID RegFile and testsRichard Qin2026-03-173-0/+193
| * Instruction Decoder Stage unit and testsRichard Qin2026-03-173-0/+345
| * Instruction fetching stage unit and testRichard Qin2026-03-163-0/+180
| * branch unit and testRichard Qin2026-03-164-0/+174
| * Merge pull request #1 from Richard-Qin-001/expand-testsRichard Qin2026-03-163-21/+143
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| | * format outputRichard Qin2026-03-163-13/+20
| | * expand tests and format outputRichard Qin2026-03-163-9/+124
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| * fix naming problemsRichard Qin2026-03-167-84/+77
| * Naming conventionRichard Qin2026-03-161-0/+159
| * Decoder unit and testRichard Qin2026-03-163-9/+697
| * Register file unit and testRichard Qin2026-03-163-13/+172
| * LicenseRichard Qin2026-03-151-0/+17
| * Add and test alu unitRichard Qin2026-03-156-8/+241
| * initial commit: project architectureRichard Qin2026-03-1541-0/+2185
* [libbase][adt] Add ilistRichard Qin4 days1-0/+546
* [libbase][adt] Add simple ilistRichard Qin4 days1-0/+482
* [libbase][adt] Add ilist baseRichard Qin4 days1-0/+139
* [libbase][adt] Add ilist iteratorRichard Qin4 days1-0/+591
* [libbase][adt] Add ilist nodeRichard Qin4 days1-0/+470
* [libbase][adt] Add ilist node baseRichard Qin4 days1-0/+167
* [libbase][adt] Add ilist node optionsRichard Qin5 days1-0/+244
* [libbase][adt] Add pointer utility typesRichard Qin5 days2-0/+466
* [libbase] Format C++ CodeRichard Qin6 days6-315/+534
* [libbase][adt] Add SmallVector ImplementationRichard Qin7 days2-0/+235
* [libbase][adt] Add TwineRichard Qin7 days1-0/+679
* [libbase] Rename public namespace and unreachable symbolsRichard Qin8 days11-38/+38
* [libbase] Fix copyright headers and cstddef includeRichard Qin8 days4-5/+5
* Restructure libbase and RCCCore buildRichard Qin8 days24-1601/+1911
* Move support code into CoreLibRichard Qin9 days14-13/+2351
* Merge remote-tracking branch 'raytracing-import/master'Richard Qin9 days21-0/+1535
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| * Remove generated ray tracing artifactsRichard Qin9 days5-335797/+0
| * Shading with Surface NormalsRichard Qin2026-03-112-5/+90016
generated by cgit v1.2.3 (git 2.46.0) at 2026-11-09 22:45:18 +0000