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* refactor(core): address WB stage architectural and naming review feedbackRichard Qin2026-03-171-12/+17
* Write Back stage unit and testsRichard Qin2026-03-183-0/+240
* Merge pull request #2 from Richard-Qin-001/audit-report-fixes-180556562870443...Richard Qin2026-03-186-29/+29
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| * Merge branch 'main' into audit-report-fixes-18055656287044378367Richard Qin2026-03-180-0/+0
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* | Memory Stage and MEM/WB pipeline stage registerRichard Qin2026-03-185-0/+739
* | fix known bugsRichard Qin2026-03-176-21/+68
* | EX/MEM Pipeline Register unit and testsRichard Qin2026-03-177-2/+386
| * docs: Finalized Richard CPU RTL architectural and naming convention audit rep...Richard Qin2026-03-1713-20/+1190
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* Execute Stage unit and testsRichard Qin2026-03-173-0/+343
* ID/EX Pipeline Register and testsRichard Qin2026-03-173-0/+354
* IF/ID RegFile and testsRichard Qin2026-03-173-0/+193
* Instruction Decoder Stage unit and testsRichard Qin2026-03-173-0/+345
* Instruction fetching stage unit and testRichard Qin2026-03-163-0/+180
* branch unit and testRichard Qin2026-03-164-0/+174
* Merge pull request #1 from Richard-Qin-001/expand-testsRichard Qin2026-03-163-21/+143
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| * format outputRichard Qin2026-03-163-13/+20
| * expand tests and format outputRichard Qin2026-03-163-9/+124
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* fix naming problemsRichard Qin2026-03-167-84/+77
* Naming conventionRichard Qin2026-03-161-0/+159
* Decoder unit and testRichard Qin2026-03-163-9/+697
* Register file unit and testRichard Qin2026-03-163-13/+172
* LicenseRichard Qin2026-03-151-0/+17
* Add and test alu unitRichard Qin2026-03-156-8/+241
* initial commit: project architectureRichard Qin2026-03-1541-0/+2185
generated by cgit v1.2.3 (git 2.46.0) at 2026-11-09 13:52:48 +0000