rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[MIR] Accept fixed-baseline LLVM syntax	Richard-Qin-X	2026-08-11	1	-2/+7
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*	[MIR] Add machine instruction parser and printer	Richard-Qin-X	2026-08-04	1	-0/+23
\| \| \| \|	Parse MachineFunction bodies in two passes and serialize the same MachineIR model in complete or readable form. Extend instruction attachments and memory operands required by the fixed LLVM MIR grammar, and cover deterministic parse-print round trips.
*	[CodeGen] Add target MIR text schema	Richard-Qin-X	2026-08-03	1	-0/+1
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*	[CodeGen] Add MIR function and block attributes	Richard-Qin-X	2026-08-01	1	-18/+0
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*	[CodeGen] Build the core MachineIR object model	Richard-Qin-X	2026-08-01	1	-0/+6
\| \| \| \| \| \|	Add arena-owned, address-stable MachineFunction, MachineBasicBlock, and MachineInstr nodes with intrusive layout and instruction lists. Model every required MachineOperand category, reciprocal ties, source state, and immutable per-instruction memory references. Implement physical and virtual register def-use chains whose back-links survive operand vector moves, plus vreg properties, tombstones, live-ins, reserved registers, and atomic CFG updates. Exercise ownership, reallocation, unlink/relink, cross-function rejection, and sanitizer paths.
*	[CodeGen] Add machine IR value semantics	Richard-Qin-X	2026-08-01	1	-0/+245
	Add strongly typed machine indices, lane masks, instruction flags, fixed-point branch probabilities, and preserved-register masks. Model immutable machine memory operands with explicit base identity, size, alignment, address space, alias information, and validated atomic operation and ordering rules. Cover normal, boundary, and invalid combinations in standalone tests.