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An optimizing compiler for C.
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RISCV
Commit message (
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Author
Age
Files
Lines
*
[CodeGen] Align pass manager ownership
Richard-Qin-X
2026-08-13
1
-2
/
+2
|
*
[RISCV] Split the GlobalISel target components
Richard-Qin-X
2026-08-12
5
-96
/
+46
|
*
[GlobalISel] Split the generic pipeline components
Richard-Qin-X
2026-08-12
1
-6
/
+7
|
*
[RISCV] Consolidate instruction behavior in RISCVInstrInfo
Richard-Qin-X
2026-08-12
1
-3
/
+0
|
*
[CodeGen] Add TargetInstrInfo ownership
Richard-Qin-X
2026-08-12
1
-2
/
+2
|
*
[Tooling] Remove the duplicate assembly emitter
Richard-Qin-X
2026-08-12
1
-5
/
+0
|
*
[RISCV] Support absolute address operand flags
Richard-Qin-X
2026-08-12
1
-0
/
+2
|
*
[RISCV] Add LP64 calling-convention facts
Richard-Qin-X
2026-08-11
1
-1
/
+2
|
*
[RISCV] Honor invocation subtarget features
Richard-Qin-X
2026-08-11
3
-0
/
+58
|
*
[RISCV] Legalize fixed-baseline RV64 MachineIR
Richard-Qin-X
2026-08-11
1
-0
/
+63
|
*
[Tooling] Complete backend tooling and validation
Richard-Qin-X
2026-08-10
1
-0
/
+35
|
*
[MC] Implement RV64GC object emission
Richard-Qin-X
2026-08-09
7
-0
/
+219
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*
[MC] Implement RV64GC assembly emission
Richard-Qin-X
2026-08-09
3
-0
/
+133
|
*
[CodeGen] Implement machine optimization and scheduling
Richard-Qin-X
2026-08-09
1
-0
/
+12
|
*
[CodeGen] Implement RV64GC frame lowering
Richard-Qin-X
2026-08-09
1
-0
/
+2
|
*
[CodeGen] Complete register allocation infrastructure
Richard-Qin-X
2026-08-09
1
-0
/
+2
|
*
[CodeGen] Implement machine SSA exit
Richard-Qin-X
2026-08-08
1
-0
/
+1
|
*
[CodeGen] Implement RV64GC legalization and instruction selection
Richard-Qin-X
2026-08-08
1
-0
/
+16
|
*
[CodeGen] Complete machine pass and ABI lowering infrastructure
Richard-Qin-X
2026-08-07
1
-0
/
+43
|
*
[RISCV] Complete RV64GC instruction description
Richard-Qin-X
2026-08-07
1
-2
/
+53
|
*
[RISCV] Add generated RV64GC register description
Richard-Qin-X
2026-08-07
1
-0
/
+23
Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
