rcc-project - An optimizing compiler for C.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[CodeGen] Implement RISC-V machine outlining	Richard-Qin-X	2026-08-25	1	-0/+3
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*	[RISCV] Implement Zcmp move merging	Richard-Qin-X	2026-08-25	1	-0/+1
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*	[RISCV] Match LLVM compressed stack frame lowering	Richard-Qin-X	2026-08-24	1	-0/+3
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*	[RISCV] Match LLVM emergency spill layout	Richard-Qin-X	2026-08-24	1	-0/+1
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*	[RISCV] Match LLVM frame lowering semantics	Richard-Qin-X	2026-08-24	1	-1/+13
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*	[CodeGen] Generate RISC-V macro fusion rules	Richard-Qin-X	2026-08-22	2	-0/+10
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*	[RISCV][GlobalISel] Select and expand global addresses	Richard-Qin-X	2026-08-19	3	-1/+16
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*	[RISCV][GlobalISel] Generate integer extension selections	Richard-Qin-X	2026-08-17	1	-0/+1
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*	[RISCV][GlobalISel] Legalize floating-point remainder	Richard-Qin-X	2026-08-15	1	-0/+1
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*	[GlobalISel] Match LLVM CSE builder result semantics	Richard-Qin-X	2026-08-15	1	-0/+2
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*	[GlobalISel] Legalize G_ABDS and G_ABDU	Richard-Qin-X	2026-08-14	1	-0/+1
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*	[CodeGen] Match LLVM machine copy propagation	Richard-Qin-X	2026-08-13	1	-2/+8
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*	[RISCV] Model non-ISA subtarget features	Richard-Qin-X	2026-08-13	1	-1/+34
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*	[CodeGen] Align pass manager ownership	Richard-Qin-X	2026-08-13	1	-2/+2
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*	[RISCV] Split the GlobalISel target components	Richard-Qin-X	2026-08-12	5	-96/+46
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*	[GlobalISel] Split the generic pipeline components	Richard-Qin-X	2026-08-12	1	-6/+7
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*	[RISCV] Consolidate instruction behavior in RISCVInstrInfo	Richard-Qin-X	2026-08-12	1	-3/+0
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*	[CodeGen] Add TargetInstrInfo ownership	Richard-Qin-X	2026-08-12	1	-2/+2
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*	[Tooling] Remove the duplicate assembly emitter	Richard-Qin-X	2026-08-12	1	-5/+0
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*	[RISCV] Support absolute address operand flags	Richard-Qin-X	2026-08-12	1	-0/+2
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*	[RISCV] Add LP64 calling-convention facts	Richard-Qin-X	2026-08-11	1	-1/+2
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*	[RISCV] Honor invocation subtarget features	Richard-Qin-X	2026-08-11	3	-0/+58
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*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	1	-0/+63
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*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	1	-0/+35
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	7	-0/+219
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*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	3	-0/+133
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	1	-0/+12
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*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	1	-0/+2
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	1	-0/+2
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*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	1	-0/+1
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*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	1	-0/+16
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*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	1	-0/+43
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	1	-2/+53
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	1	-0/+23
	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.