rcc-project - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	[RISCV] Honor invocation subtarget features	Richard-Qin-X	2026-08-11	3	-0/+58
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*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	1	-0/+63
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*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	1	-0/+35
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	7	-0/+219
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*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	3	-0/+133
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	1	-0/+12
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*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	1	-0/+2
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	1	-0/+2
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*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	1	-0/+1
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*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	1	-0/+16
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*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	1	-0/+43
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	1	-2/+53
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	1	-0/+23
	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.