rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[GlobalISel] Match LLVM legalization value tracking	Richard-Qin-X	2026-08-14	8	-426/+532
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*	[CodeGen] Match LLVM Legalizer ownership	Richard-Qin-X	2026-08-14	13	-8/+2333
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*	[CodeGen] Unify scalar low-level types	Richard-Qin-X	2026-08-13	5	-77/+55
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*	[CodeGen] Match LLVM machine copy propagation	Richard-Qin-X	2026-08-13	5	-13/+36
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*	[CodeGen] Match LLVM branch relaxation semantics	Richard-Qin-X	2026-08-13	2	-0/+2
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*	[RISCV] Model non-ISA subtarget features	Richard-Qin-X	2026-08-13	1	-1/+34
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*	[RISCV] Match LLVM register bank mappings	Richard-Qin-X	2026-08-13	2	-5/+18
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*	[MIR] Omit predictable successors in simplified output	Richard-Qin-X	2026-08-13	1	-0/+7
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*	[CodeGen] Remove duplicate analysis declarations	Richard-Qin-X	2026-08-13	2	-5/+0
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*	[IR] Sequence analysis registration moves	Richard-Qin-X	2026-08-13	1	-2/+3
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*	[Tooling] Remove the duplicate output kind	Richard-Qin-X	2026-08-13	3	-18/+6
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*	[Support] Centralize error context handling	Richard-Qin-X	2026-08-13	1	-0/+2
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*	[CodeGen] Remove the unused property query	Richard-Qin-X	2026-08-13	1	-1/+0
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*	[TableGen] Split the target description generator	Richard-Qin-X	2026-08-13	2	-0/+255
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*	[IR] Split LL parsing, assembly writing, and data layout	Richard-Qin-X	2026-08-13	8	-61/+128
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*	[Support] Split APInt and APFloat ownership	Richard-Qin-X	2026-08-13	8	-118/+176
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*	[CodeGen] Align MIR parser and printer ownership	Richard-Qin-X	2026-08-13	8	-231/+167
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*	[CodeGen] Align pass manager ownership	Richard-Qin-X	2026-08-13	42	-826/+1142
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*	[CodeGen] Split machine liveness components	Richard-Qin-X	2026-08-13	9	-416/+542
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*	[CodeGen] Split PHI elimination and two-address rewriting	Richard-Qin-X	2026-08-13	3	-49/+62
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*	[RISCV] Split the GlobalISel target components	Richard-Qin-X	2026-08-12	6	-104/+50
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*	[GlobalISel] Split the generic pipeline components	Richard-Qin-X	2026-08-12	9	-169/+229
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*	[RISCV] Consolidate instruction behavior in RISCVInstrInfo	Richard-Qin-X	2026-08-12	6	-54/+31
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*	[CodeGen] Add TargetInstrInfo ownership	Richard-Qin-X	2026-08-12	10	-30/+30
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*	[Tooling] Remove the duplicate assembly emitter	Richard-Qin-X	2026-08-12	1	-5/+0
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*	[Tooling] Complete the LLVM MIR command-line contract	Richard-Qin-X	2026-08-12	4	-30/+78
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*	[Tooling] Adopt LLVM MIR command-line spellings	Richard-Qin-X	2026-08-12	2	-0/+2
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*	[MIR] Remove alternate layout and float APIs	Richard-Qin-X	2026-08-12	4	-5/+0
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*	[RISCV] Legalize llvm.va_copy	Richard-Qin-X	2026-08-12	1	-0/+9
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*	[RISCV] Support absolute address operand flags	Richard-Qin-X	2026-08-12	1	-0/+2
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*	[RISCV] Add LP64 calling-convention facts	Richard-Qin-X	2026-08-11	1	-1/+2
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*	[CodeGen] Remove redundant numeric call-site IDs	Richard-Qin-X	2026-08-11	1	-6/+0
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*	[RISCV] Honor invocation subtarget features	Richard-Qin-X	2026-08-11	4	-1/+64
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*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	1	-0/+63
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*	[MIR] Accept fixed-baseline LLVM syntax	Richard-Qin-X	2026-08-11	9	-3/+349
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*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	20	-25/+754
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	17	-0/+722
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*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	17	-0/+1205
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	38	-0/+1518
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*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	8	-0/+177
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	20	-19/+1160
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*	[CodeGen] Implement machine liveness analysis	Richard-Qin-X	2026-08-09	3	-0/+414
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*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	7	-4/+95
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*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	3	-0/+173
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*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	8	-0/+1763
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	2	-2/+102
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	2	-0/+30
\| \| \| \|	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
*	[MIR] Complete document parsing and printing	Richard-Qin-X	2026-08-07	14	-25/+611
\| \| \| \|	Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.
*	[MIR] Add machine instruction parser and printer	Richard-Qin-X	2026-08-04	4	-0/+212
\| \| \| \|	Parse MachineFunction bodies in two passes and serialize the same MachineIR model in complete or readable form. Extend instruction attachments and memory operands required by the fixed LLVM MIR grammar, and cover deterministic parse-print round trips.
*	[MIR] Add machine instruction lexer	Richard-Qin-X	2026-08-03	1	-0/+181
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