rcc-project - An optimizing compiler for C.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[MIR] Accept fixed-baseline LLVM syntax	Richard-Qin-X	2026-08-11	1	-2/+0
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	1	-0/+60
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*	[CodeGen] Track debug instruction identities	Richard-Qin-X	2026-08-01	1	-0/+14
\| \| \| \|	Add monotonic MIR debug instruction numbers and structured value substitutions. Verify live number uniqueness, meta-instruction exclusion, substitution graph integrity, and target subregister references while preserving debug identities during cloning.
*	[CodeGen] Add target state and compilation status	Richard-Qin-X	2026-08-01	1	-0/+11
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*	[CodeGen] Add constant and jump table state	Richard-Qin-X	2026-08-01	1	-1/+2
\| \| \| \|	Add stable, tombstone-preserving MachineConstantPool and MachineJumpTableInfo ownership. Define the versioned TargetConstant contract and integrate all table references with builders, verification, and deterministic deep cloning.
*	[CMake] Match LLVM EH and RTTI defaults	Richard-Qin-X	2026-08-01	1	-10/+7
\| \| \| \|	Disable C++ exceptions and RTTI by default while retaining explicit, validated opt-in switches. Replace the arena's exception syntax with an RAII construction guard so both configurations share one implementation.
*	[CodeGen] Build the core MachineIR object model	Richard-Qin-X	2026-08-01	1	-0/+205
	Add arena-owned, address-stable MachineFunction, MachineBasicBlock, and MachineInstr nodes with intrusive layout and instruction lists. Model every required MachineOperand category, reciprocal ties, source state, and immutable per-instruction memory references. Implement physical and virtual register def-use chains whose back-links survive operand vector moves, plus vreg properties, tombstones, live-ins, reserved registers, and atomic CFG updates. Exercise ownership, reallocation, unlink/relink, cross-function rejection, and sanitizer paths.