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path: root/backend/lib/CodeGen/MachineIRBuilder.cpp
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* [GlobalISel] Match LLVM legalization value trackingRichard-Qin-X2026-08-141-21/+141
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* [CodeGen] Match LLVM Legalizer ownershipRichard-Qin-X2026-08-141-0/+193
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* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-131-4/+2
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* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-071-0/+13
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* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-031-0/+75
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* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-021-4/+30
| | | | Replace marker-based metadata operands with scoped references and inline DIExpression values. Add structured DILocation chains, instruction debug attachments, stack variable records, and entry values with unified verification, builder support, and deterministic cloning.
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-011-18/+21
| | | | Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.
* [CodeGen] Add constant and jump table stateRichard-Qin-X2026-08-011-1/+37
| | | | Add stable, tombstone-preserving MachineConstantPool and MachineJumpTableInfo ownership. Define the versioned TargetConstant contract and integrate all table references with builders, verification, and deterministic deep cloning.
* [CodeGen] Add MachineFrameInfoRichard-Qin-X2026-08-011-0/+22
| | | | Model stable frame indices, stack object kinds, tombstones, lifetimes, and frozen layouts. Validate owned frame references in the builder and verifier, and remap complete frame state during MachineFunction cloning.
* [CodeGen] Add transactional MachineIR builderRichard-Qin-X2026-08-011-0/+537
Validate insertion cursors, operand ownership, descriptor constraints, ties, implicit registers, and memory operands before allocating or publishing an instruction. Share instruction legality checks with the verifier path and preserve deterministic insertion order.