rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[CodeGen] Match LLVM machine debug stripping	Richard-Qin-X	2026-08-22	1	-0/+16
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*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	1	-0/+14
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*	[MIR] Add machine instruction parser and printer	Richard-Qin-X	2026-08-04	1	-0/+69
\| \| \| \|	Parse MachineFunction bodies in two passes and serialize the same MachineIR model in complete or readable form. Extend instruction attachments and memory operands required by the fixed LLVM MIR grammar, and cover deterministic parse-print round trips.
*	[CodeGen] Model machine debug metadata	Richard-Qin-X	2026-08-02	1	-0/+9
\| \| \| \|	Replace marker-based metadata operands with scoped references and inline DIExpression values. Add structured DILocation chains, instruction debug attachments, stack variable records, and entry values with unified verification, builder support, and deterministic cloning.
*	[CodeGen] Track debug instruction identities	Richard-Qin-X	2026-08-01	1	-0/+26
\| \| \| \|	Add monotonic MIR debug instruction numbers and structured value substitutions. Verify live number uniqueness, meta-instruction exclusion, substitution graph integrity, and target subregister references while preserving debug identities during cloning.
*	[CodeGen] Add transactional MachineIR builder	Richard-Qin-X	2026-08-01	1	-4/+4
\| \| \| \|	Validate insertion cursors, operand ownership, descriptor constraints, ties, implicit registers, and memory operands before allocating or publishing an instruction. Share instruction legality checks with the verifier path and preserve deterministic insertion order.
*	[CodeGen] Build the core MachineIR object model	Richard-Qin-X	2026-08-01	1	-0/+199
	Add arena-owned, address-stable MachineFunction, MachineBasicBlock, and MachineInstr nodes with intrusive layout and instruction lists. Model every required MachineOperand category, reciprocal ties, source state, and immutable per-instruction memory references. Implement physical and virtual register def-use chains whose back-links survive operand vector moves, plus vreg properties, tombstones, live-ins, reserved registers, and atomic CFG updates. Exercise ownership, reallocation, unlink/relink, cross-function rejection, and sanitizer paths.