rcc-project - An optimizing compiler for C.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	1	-2/+28
\| \| \| \|	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
*	[CodeGen] Add target MIR text schema	Richard-Qin-X	2026-08-03	1	-9/+66
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*	[CodeGen] Model complete MIR operands	Richard-Qin-X	2026-08-03	1	-1/+1
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*	[CodeGen] Add target register descriptions	Richard-Qin-X	2026-08-01	1	-0/+603
	Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.