| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
| |
Disable C++ exceptions and RTTI by default while retaining explicit, validated opt-in switches. Replace the arena's exception syntax with an RAII construction guard so both configurations share one implementation.
|
| |
|
|
| |
Introduce an immutable instruction registry with exact operand, implicit register, tie, pseudo lifecycle, and memory constraints. Validate descriptor tables before publication and use the same rules to verify MachineInstr instances.
|
| |
|
|
|
|
| |
Add arena-owned, address-stable MachineFunction, MachineBasicBlock, and MachineInstr nodes with intrusive layout and instruction lists. Model every required MachineOperand category, reciprocal ties, source state, and immutable per-instruction memory references.
Implement physical and virtual register def-use chains whose back-links survive operand vector moves, plus vreg properties, tombstones, live-ins, reserved registers, and atomic CFG updates. Exercise ownership, reallocation, unlink/relink, cross-function rejection, and sanitizer paths.
|
| |
|
|
|
|
| |
Add strongly typed machine indices, lane masks, instruction flags, fixed-point branch probabilities, and preserved-register masks.
Model immutable machine memory operands with explicit base identity, size, alignment, address space, alias information, and validated atomic operation and ordering rules. Cover normal, boundary, and invalid combinations in standalone tests.
|
|
|
Introduce an independent 64-bit extended LLT representation that preserves exact floating-point semantics and supports fixed and scalable vectors. Add opaque physical and virtual registers, strongly typed monotonic stable IDs, and atomic MachineFunctionProperties transitions.
Export the primitives through RCCBackend::CodeGen, cover their boundary and failure cases, record the frozen invariants, and normalize the architecture document permissions.
|
