| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Implement make-compressible pass | Richard-Qin-X | 2026-08-25 | 1 | -0/+39 |
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| * | [CodeGen] Implement RISC-V machine outlining | Richard-Qin-X | 2026-08-25 | 1 | -0/+17 |
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| * | [RISCV][GlobalISel] Select and expand global addresses | Richard-Qin-X | 2026-08-19 | 1 | -0/+27 |
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| * | [RISCV] Split the GlobalISel target components | Richard-Qin-X | 2026-08-12 | 1 | -2/+2 |
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| * | [MIR] Accept fixed-baseline LLVM syntax | Richard-Qin-X | 2026-08-11 | 1 | -1/+120 |
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| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 1 | -13/+11 |
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| * | [MIR] Complete document parsing and printing | Richard-Qin-X | 2026-08-07 | 1 | -40/+148 |
| | | | | | Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage. | ||||
| * | [MIR] Add compilation unit reference context | Richard-Qin-X | 2026-08-01 | 1 | -0/+636 |
