| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Legalize fixed-baseline RV64 MachineIR | Richard-Qin-X | 2026-08-11 | 1 | -3/+24 |
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| * | [MC] Implement RV64GC object emission | Richard-Qin-X | 2026-08-09 | 1 | -0/+195 |
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| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -2/+55 |
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| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 1 | -11/+11 |
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| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 1 | -1/+2978 |
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| * | [RISCV] Add generated RV64GC register description | Richard-Qin-X | 2026-08-07 | 1 | -0/+220 |
| Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling. | |||||
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index : rcc-project | |
| A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser. |
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