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path: root/backend/lib/Target/RISCV/RISCVCodeGen.cpp
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* [RISCV] Legalize G_PTR_ADD with s64 offsetsRichard-Qin-X2026-08-121-2/+2
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* [RISCV] Legalize G_FRAME_INDEX for p0Richard-Qin-X2026-08-121-0/+4
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* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-121-3/+188
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* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-121-0/+103
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* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-111-3/+6
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* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-111-1/+0
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* [RISCV] Lower multiply without M through libcallsRichard-Qin-X2026-08-111-3/+123
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* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-111-1/+14
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* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-111-15/+49
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* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-111-0/+18
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* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-111-0/+28
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* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-111-4/+151
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* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-111-2/+3
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* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-111-0/+94
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* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-111-2/+3
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* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-111-0/+140
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* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-111-25/+2430
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* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-081-0/+199
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* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-081-0/+3239
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 22:56:16 +0000