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path: root/backend/lib/Target/RISCV/RISCVPipeline.cpp
Commit message (Collapse)AuthorAgeFilesLines
* [RISCV] Implement base offset mergingRichard-Qin-X2026-08-251-0/+3
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* [RISCV] Implement Zcmp move mergingRichard-Qin-X2026-08-251-0/+5
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* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-241-1/+5
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* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-241-5/+12
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* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-241-1/+3
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* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-221-10/+17
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* [GlobalISel] Generate prelegalizer combiner rulesRichard-Qin-X2026-08-191-5/+5
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* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-191-1/+5
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* [RISCV][GlobalISel] Legalize floating-point remainderRichard-Qin-X2026-08-151-2/+2
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* [GlobalISel] Lower integer operations to libcallsRichard-Qin-X2026-08-151-2/+9
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* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-151-4/+5
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* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-131-6/+14
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* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-131-10/+12
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* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-131-3/+4
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* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-121-23/+17
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* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-121-7/+9
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* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-121-4/+5
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* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-121-14/+0
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* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-121-2/+11
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* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-111-6/+18
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* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-101-0/+162
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 12:57:35 +0000