| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [CodeGen] Implement machine SSA exit | Richard-Qin-X | 2026-08-08 | 1 | -0/+199 |
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| * | [CodeGen] Implement RV64GC legalization and instruction selection | Richard-Qin-X | 2026-08-08 | 2 | -0/+3243 |
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| * | [CodeGen] Complete machine pass and ABI lowering infrastructure | Richard-Qin-X | 2026-08-07 | 2 | -0/+1477 |
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| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 3 | -9/+3065 |
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| * | [RISCV] Add generated RV64GC register description | Richard-Qin-X | 2026-08-07 | 3 | -0/+402 |
| Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling. | |||||
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index : rcc-project | |
| A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser. |
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