rcc-project - An optimizing compiler for C.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[RISCV] Lower multiply without M through libcalls	Richard-Qin-X	2026-08-11	1	-3/+123
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*	[RISCV] Accept generic scalars in call lowering	Richard-Qin-X	2026-08-11	1	-3/+2
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*	[RISCV] Honor invocation subtarget features	Richard-Qin-X	2026-08-11	4	-7/+130
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*	[RISCV] Fold narrow binary artifact chains	Richard-Qin-X	2026-08-11	1	-15/+49
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*	[RISCV] Preserve folded constant placement	Richard-Qin-X	2026-08-11	1	-0/+18
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*	[RISCV] Reuse compare operand extensions	Richard-Qin-X	2026-08-11	1	-0/+28
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*	[RISCV] Legalize integer compares to RV64 containers	Richard-Qin-X	2026-08-11	1	-4/+151
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*	[RISCV] Preserve live constants when folding extensions	Richard-Qin-X	2026-08-11	1	-2/+3
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*	[RISCV] Lower cmpxchg with success	Richard-Qin-X	2026-08-11	1	-0/+94
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*	[RISCV] Preserve narrow cmpxchg results when widening	Richard-Qin-X	2026-08-11	1	-2/+3
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*	[RISCV] Legalize narrow atomic compare exchange	Richard-Qin-X	2026-08-11	1	-0/+140
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*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	9	-32/+2824
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*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	2	-0/+166
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	7	-25/+1983
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*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	4	-1/+1522
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	9	-33/+1693
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*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	3	-0/+2106
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	3	-11/+293
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*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	1	-0/+199
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*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	2	-0/+3243
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*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	2	-0/+1477
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	3	-9/+3065
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	3	-0/+402
	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.