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* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-111-0/+18
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* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-111-0/+28
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* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-111-4/+151
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* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-111-2/+3
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* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-111-0/+94
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* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-111-2/+3
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* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-111-0/+140
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* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-119-32/+2824
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* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-102-0/+166
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* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-098-34/+2004
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* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-094-1/+1522
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* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0910-36/+1697
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* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-093-0/+2106
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* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-095-24/+311
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* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-081-0/+199
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* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-082-0/+3243
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* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-072-0/+1477
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* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-075-15/+4969
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* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-076-0/+1589
Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.