aboutsummaryrefslogtreecommitdiff
path: root/backend/lib/Target
Commit message (Expand)AuthorAgeFilesLines
...
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-114-7/+130
* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-111-15/+49
* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-111-0/+18
* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-111-0/+28
* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-111-4/+151
* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-111-2/+3
* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-111-0/+94
* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-111-2/+3
* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-111-0/+140
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-119-32/+2824
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-102-0/+166
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-098-34/+2004
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-094-1/+1522
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0910-36/+1697
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-093-0/+2106
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-095-24/+311
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-081-0/+199
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-082-0/+3243
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-072-0/+1477
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-075-15/+4969
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-076-0/+1589
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 23:40:00 +0000