rcc-project - An optimizing compiler for C.

	Commit message (Collapse)	Author	Age	Files	Lines
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*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	2	-0/+166
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	8	-34/+2004
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*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	4	-1/+1522
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	10	-36/+1697
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*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	3	-0/+2106
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	5	-24/+311
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*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	1	-0/+199
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*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	2	-0/+3243
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*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	2	-0/+1477
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	5	-15/+4969
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	6	-0/+1589
	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.