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* [CodeGen] Reuse register diagnostic formattingRichard-Qin-X2026-08-131-2/+1
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* [TableGen] Fix quality tool source pathsRichard-Qin-X2026-08-131-0/+1
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* [Tooling] Remove the duplicate output kindRichard-Qin-X2026-08-134-118/+66
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* [RISCV] Remove physical register forwarding helpersRichard-Qin-X2026-08-133-57/+39
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* [RISCV] Use the generated opcode conversionRichard-Qin-X2026-08-138-194/+164
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* [Support] Centralize error context handlingRichard-Qin-X2026-08-1329-234/+117
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* [CodeGen] Remove the unused property queryRichard-Qin-X2026-08-131-4/+0
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* [TableGen] Split the target description generatorRichard-Qin-X2026-08-137-3102/+1281
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* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-1316-2268/+2168
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* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-1315-1852/+1785
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* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-1325-4921/+4633
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* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-1341-673/+284
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* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-1338-1195/+1310
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* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-134-487/+634
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* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-1231-6674/+6892
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* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-128-761/+964
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* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-1213-243/+166
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* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-1210-23/+35
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* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-121-14/+0
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* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-1210-129/+359
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* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-125-19/+45
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* [CodeGen] Verify local physical live-insRichard-Qin-X2026-08-121-3/+73
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* [CodeGen] Allow dynamic implicit operands on copiesRichard-Qin-X2026-08-121-1/+1
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* [RISCV] Describe vector tuple registersRichard-Qin-X2026-08-122-1/+87
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* [RISCV] Describe vector physical registersRichard-Qin-X2026-08-121-0/+77
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* [clang-format] Format MIR sourcesRichard-Qin-X2026-08-122-13/+11
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* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-1212-78/+28
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* [RISCV] Add Zba and Zbb instruction descriptionsRichard-Qin-X2026-08-123-2/+253
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* [CodeGen] Allow narrow atomic RMW memory typesRichard-Qin-X2026-08-121-1/+1
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* [RISCV] Make call-preserved masks optionalRichard-Qin-X2026-08-121-2/+2
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* [RISCV] Make target memory operands optionalRichard-Qin-X2026-08-122-53/+3
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* [CodeGen] Preserve variable-sized stack object offsetsRichard-Qin-X2026-08-121-6/+2
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* [RISCV] Legalize G_PTR_ADD with s64 offsetsRichard-Qin-X2026-08-121-2/+2
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* [RISCV] Legalize G_FRAME_INDEX for p0Richard-Qin-X2026-08-121-0/+4
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* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-122-25/+192
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* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-121-15/+15
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* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-122-0/+104
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* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-121-1/+1
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* [MIR] Create virtual registers referenced by live-insRichard-Qin-X2026-08-123-6/+14
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* [CodeGen] Track reserved register defs preciselyRichard-Qin-X2026-08-122-9/+8
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* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-121-0/+50
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* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-123-1/+100
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* [MIR] Ignore empty YAML documentsRichard-Qin-X2026-08-121-16/+33
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* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-121-0/+15
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* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-121-4/+12
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* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-121-0/+163
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* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-125-12/+44
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* [MIR] Accept physical-only function live-insRichard-Qin-X2026-08-121-4/+6
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* [MIR] Accept unnamed stack objectsRichard-Qin-X2026-08-121-3/+4
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* [MIR] Accept empty optional register fieldsRichard-Qin-X2026-08-122-7/+17
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generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 16:55:18 +0000