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Commit message (Collapse)AuthorAgeFilesLines
* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-121-14/+0
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* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-1210-129/+359
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* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-125-19/+45
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* [CodeGen] Verify local physical live-insRichard-Qin-X2026-08-121-3/+73
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* [CodeGen] Allow dynamic implicit operands on copiesRichard-Qin-X2026-08-121-1/+1
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* [RISCV] Describe vector tuple registersRichard-Qin-X2026-08-122-1/+87
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* [RISCV] Describe vector physical registersRichard-Qin-X2026-08-121-0/+77
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* [clang-format] Format MIR sourcesRichard-Qin-X2026-08-122-13/+11
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* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-1212-78/+28
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* [RISCV] Add Zba and Zbb instruction descriptionsRichard-Qin-X2026-08-123-2/+253
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* [CodeGen] Allow narrow atomic RMW memory typesRichard-Qin-X2026-08-121-1/+1
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* [RISCV] Make call-preserved masks optionalRichard-Qin-X2026-08-121-2/+2
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* [RISCV] Make target memory operands optionalRichard-Qin-X2026-08-122-53/+3
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* [CodeGen] Preserve variable-sized stack object offsetsRichard-Qin-X2026-08-121-6/+2
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* [RISCV] Legalize G_PTR_ADD with s64 offsetsRichard-Qin-X2026-08-121-2/+2
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* [RISCV] Legalize G_FRAME_INDEX for p0Richard-Qin-X2026-08-121-0/+4
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* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-122-25/+192
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* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-121-15/+15
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* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-122-0/+104
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* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-121-1/+1
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* [MIR] Create virtual registers referenced by live-insRichard-Qin-X2026-08-123-6/+14
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* [CodeGen] Track reserved register defs preciselyRichard-Qin-X2026-08-122-9/+8
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* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-121-0/+50
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* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-123-1/+100
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* [MIR] Ignore empty YAML documentsRichard-Qin-X2026-08-121-16/+33
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* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-121-0/+15
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* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-121-4/+12
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* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-121-0/+163
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* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-125-12/+44
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* [MIR] Accept physical-only function live-insRichard-Qin-X2026-08-121-4/+6
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* [MIR] Accept unnamed stack objectsRichard-Qin-X2026-08-121-3/+4
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* [MIR] Accept empty optional register fieldsRichard-Qin-X2026-08-122-7/+17
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* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-111-0/+11
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* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-111-2/+2
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* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-117-77/+183
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* [RISCV] Order call operands like LLVM MIRRichard-Qin-X2026-08-111-8/+8
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* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-114-55/+97
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* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-115-30/+14
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* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-114-74/+33
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* [RISCV] Use canonical copies for full ABI valuesRichard-Qin-X2026-08-111-4/+10
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* [RISCV] Lower multiply without M through libcallsRichard-Qin-X2026-08-111-3/+123
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* [RISCV] Accept generic scalars in call loweringRichard-Qin-X2026-08-111-3/+2
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* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-115-17/+147
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* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-111-15/+49
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* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-111-12/+11
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* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-111-0/+18
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* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-111-0/+28
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* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-111-4/+151
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* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-111-2/+3
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* [MIR] Omit absent zero-offset MMO basesRichard-Qin-X2026-08-111-3/+5
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