rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[RISCV] Allow frame indices in ADDI	Richard-Qin-X	2026-08-12	1	-1/+1
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*	[MIR] Create virtual registers referenced by live-ins	Richard-Qin-X	2026-08-12	3	-6/+14
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*	[CodeGen] Track reserved register defs precisely	Richard-Qin-X	2026-08-12	2	-9/+8
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*	[RISCV] Model dynamic rounding-mode state	Richard-Qin-X	2026-08-12	1	-0/+50
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*	[RISCV] Model FFLAGS accesses	Richard-Qin-X	2026-08-12	3	-1/+100
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*	[MIR] Ignore empty YAML documents	Richard-Qin-X	2026-08-12	1	-16/+33
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*	[RISCV] Describe the GPR select pseudo	Richard-Qin-X	2026-08-12	1	-0/+15
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*	[CodeGen] Accept pointer comparisons in G_ICMP	Richard-Qin-X	2026-08-12	1	-4/+12
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*	[RISCV] Model target-specific generic opcodes	Richard-Qin-X	2026-08-12	1	-0/+163
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*	[RISCV] Support absolute address operand flags	Richard-Qin-X	2026-08-12	5	-12/+44
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*	[MIR] Accept physical-only function live-ins	Richard-Qin-X	2026-08-12	1	-4/+6
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*	[MIR] Accept unnamed stack objects	Richard-Qin-X	2026-08-12	1	-3/+4
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*	[MIR] Accept empty optional register fields	Richard-Qin-X	2026-08-12	2	-7/+17
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*	[CodeGen] Treat reserved registers as always live	Richard-Qin-X	2026-08-11	1	-0/+11
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*	[CodeGen] Accept conservative physical live-ins	Richard-Qin-X	2026-08-11	1	-2/+2
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*	[RISCV] Model typed floating-point register views	Richard-Qin-X	2026-08-11	7	-77/+183
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*	[RISCV] Order call operands like LLVM MIR	Richard-Qin-X	2026-08-11	1	-8/+8
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*	[RISCV] Add LP64 calling-convention facts	Richard-Qin-X	2026-08-11	4	-55/+97
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*	[CodeGen] Remove redundant numeric call-site IDs	Richard-Qin-X	2026-08-11	5	-30/+14
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*	[RISCV] Match LLVM call-frame pseudo semantics	Richard-Qin-X	2026-08-11	4	-74/+33
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*	[RISCV] Use canonical copies for full ABI values	Richard-Qin-X	2026-08-11	1	-4/+10
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*	[RISCV] Lower multiply without M through libcalls	Richard-Qin-X	2026-08-11	1	-3/+123
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*	[RISCV] Accept generic scalars in call lowering	Richard-Qin-X	2026-08-11	1	-3/+2
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*	[RISCV] Honor invocation subtarget features	Richard-Qin-X	2026-08-11	5	-17/+147
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*	[RISCV] Fold narrow binary artifact chains	Richard-Qin-X	2026-08-11	1	-15/+49
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*	[CodeGen] Revisit instructions invalidated by legalization	Richard-Qin-X	2026-08-11	1	-12/+11
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*	[RISCV] Preserve folded constant placement	Richard-Qin-X	2026-08-11	1	-0/+18
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*	[RISCV] Reuse compare operand extensions	Richard-Qin-X	2026-08-11	1	-0/+28
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*	[RISCV] Legalize integer compares to RV64 containers	Richard-Qin-X	2026-08-11	1	-4/+151
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*	[RISCV] Preserve live constants when folding extensions	Richard-Qin-X	2026-08-11	1	-2/+3
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*	[MIR] Omit absent zero-offset MMO bases	Richard-Qin-X	2026-08-11	1	-3/+5
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*	[RISCV] Lower cmpxchg with success	Richard-Qin-X	2026-08-11	1	-0/+94
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*	[RISCV] Preserve narrow cmpxchg results when widening	Richard-Qin-X	2026-08-11	1	-2/+3
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*	[RISCV] Legalize narrow atomic compare exchange	Richard-Qin-X	2026-08-11	2	-2/+142
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*	[MIR] Parse one-ordering compare-exchange MMOs	Richard-Qin-X	2026-08-11	2	-43/+42
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*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	11	-58/+2900
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*	[MIR] Accept fixed-baseline LLVM syntax	Richard-Qin-X	2026-08-11	30	-623/+1739
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*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	50	-2871/+7754
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	21	-45/+4393
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*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	21	-1/+3982
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	43	-37/+9871
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*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	16	-7/+2659
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	35	-154/+2955
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*	[CodeGen] Implement machine liveness analysis	Richard-Qin-X	2026-08-09	6	-32/+1931
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*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	9	-49/+1796
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*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	4	-0/+3862
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*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	8	-0/+5577
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	6	-55/+5144
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	8	-7/+1629
\| \| \| \|	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
*	[MIR] Complete document parsing and printing	Richard-Qin-X	2026-08-07	20	-179/+9288
\| \| \| \|	Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.