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* [RISCV] Legalize G_PTR_ADD with s64 offsetsRichard-Qin-X2026-08-121-2/+2
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* [RISCV] Legalize G_FRAME_INDEX for p0Richard-Qin-X2026-08-121-0/+4
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* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-122-25/+192
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* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-121-15/+15
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* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-122-0/+104
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* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-121-1/+1
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* [MIR] Create virtual registers referenced by live-insRichard-Qin-X2026-08-123-6/+14
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* [CodeGen] Track reserved register defs preciselyRichard-Qin-X2026-08-122-9/+8
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* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-121-0/+50
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* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-123-1/+100
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* [MIR] Ignore empty YAML documentsRichard-Qin-X2026-08-121-16/+33
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* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-121-0/+15
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* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-121-4/+12
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* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-121-0/+163
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* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-125-12/+44
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* [MIR] Accept physical-only function live-insRichard-Qin-X2026-08-121-4/+6
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* [MIR] Accept unnamed stack objectsRichard-Qin-X2026-08-121-3/+4
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* [MIR] Accept empty optional register fieldsRichard-Qin-X2026-08-122-7/+17
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* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-111-0/+11
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* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-111-2/+2
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* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-117-77/+183
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* [RISCV] Order call operands like LLVM MIRRichard-Qin-X2026-08-111-8/+8
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* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-114-55/+97
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* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-115-30/+14
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* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-114-74/+33
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* [RISCV] Use canonical copies for full ABI valuesRichard-Qin-X2026-08-111-4/+10
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* [RISCV] Lower multiply without M through libcallsRichard-Qin-X2026-08-111-3/+123
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* [RISCV] Accept generic scalars in call loweringRichard-Qin-X2026-08-111-3/+2
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* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-115-17/+147
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* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-111-15/+49
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* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-111-12/+11
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* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-111-0/+18
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* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-111-0/+28
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* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-111-4/+151
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* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-111-2/+3
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* [MIR] Omit absent zero-offset MMO basesRichard-Qin-X2026-08-111-3/+5
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* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-111-0/+94
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* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-111-2/+3
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* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-112-2/+142
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* [MIR] Parse one-ordering compare-exchange MMOsRichard-Qin-X2026-08-112-43/+42
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* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-1111-58/+2900
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* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-1130-623/+1739
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* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1050-2871/+7754
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* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-0921-45/+4393
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* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-0921-1/+3982
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* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0943-37/+9871
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* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-0916-7/+2659
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* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0935-154/+2955
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* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-096-32/+1931
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* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-089-49/+1796
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