aboutsummaryrefslogtreecommitdiff
path: root/backend/lib
Commit message (Collapse)AuthorAgeFilesLines
* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-123-1/+100
|
* [MIR] Ignore empty YAML documentsRichard-Qin-X2026-08-121-16/+33
|
* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-121-0/+15
|
* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-121-4/+12
|
* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-121-0/+163
|
* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-125-12/+44
|
* [MIR] Accept physical-only function live-insRichard-Qin-X2026-08-121-4/+6
|
* [MIR] Accept unnamed stack objectsRichard-Qin-X2026-08-121-3/+4
|
* [MIR] Accept empty optional register fieldsRichard-Qin-X2026-08-122-7/+17
|
* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-111-0/+11
|
* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-111-2/+2
|
* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-117-77/+183
|
* [RISCV] Order call operands like LLVM MIRRichard-Qin-X2026-08-111-8/+8
|
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-114-55/+97
|
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-115-30/+14
|
* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-114-74/+33
|
* [RISCV] Use canonical copies for full ABI valuesRichard-Qin-X2026-08-111-4/+10
|
* [RISCV] Lower multiply without M through libcallsRichard-Qin-X2026-08-111-3/+123
|
* [RISCV] Accept generic scalars in call loweringRichard-Qin-X2026-08-111-3/+2
|
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-115-17/+147
|
* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-111-15/+49
|
* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-111-12/+11
|
* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-111-0/+18
|
* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-111-0/+28
|
* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-111-4/+151
|
* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-111-2/+3
|
* [MIR] Omit absent zero-offset MMO basesRichard-Qin-X2026-08-111-3/+5
|
* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-111-0/+94
|
* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-111-2/+3
|
* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-112-2/+142
|
* [MIR] Parse one-ordering compare-exchange MMOsRichard-Qin-X2026-08-112-43/+42
|
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-1111-58/+2900
|
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-1130-623/+1739
|
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1050-2871/+7754
|
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-0921-45/+4393
|
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-0921-1/+3982
|
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0943-37/+9871
|
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-0916-7/+2659
|
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0935-154/+2955
|
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-096-32/+1931
|
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-089-49/+1796
|
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-084-0/+3862
|
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-078-0/+5577
|
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-076-55/+5144
|
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-078-7/+1629
| | | | Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-0720-179/+9288
| | | | Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-048-13/+4745
| | | | Parse MachineFunction bodies in two passes and serialize the same MachineIR model in complete or readable form. Extend instruction attachments and memory operands required by the fixed LLVM MIR grammar, and cover deterministic parse-print round trips.
* [MIR] Add machine instruction lexerRichard-Qin-X2026-08-032-2/+957
|
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-038-21/+643
|
* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-038-1/+600
|
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-30 09:58:05 +0000