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* [GlobalISel] Preserve worklists when moving CSE instructionsRichard-Qin-X2026-08-152-7/+29
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* [GlobalISel] Lower three-way integer comparisonsRichard-Qin-X2026-08-151-16/+102
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* [GlobalISel] Lower integer min/max operationsRichard-Qin-X2026-08-151-0/+66
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* [GlobalISel] Widen scalar memory operationsRichard-Qin-X2026-08-151-0/+39
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* [GlobalISel] Legalize scalar floating comparisonsRichard-Qin-X2026-08-151-0/+26
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* [GlobalISel] Legalize scalar pointer castsRichard-Qin-X2026-08-151-0/+57
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* [GlobalISel] Narrow scalar shiftsRichard-Qin-X2026-08-151-2/+913
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* [MIR] Print target generic operand typesRichard-Qin-X2026-08-151-2/+2
| | | | Use the instruction descriptor's Generic flag when deduplicating LLT annotations so target-specific generic pseudos follow LLVM MIR spelling.
* [GlobalISel] Narrow scalar selectsRichard-Qin-X2026-08-151-10/+86
| | | | Match LLVM's narrowScalarSelect lowering for wide scalar values. Build widened sources from LLT destinations so CSE hits reuse the actual result register instead of introducing copies.
* [GlobalISel] Narrow scalar bitwise operationsRichard-Qin-X2026-08-151-0/+78
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* [GlobalISel] Legalize constants and implicit definitionsRichard-Qin-X2026-08-153-34/+195
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* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-1510-252/+1198
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* [GlobalISel] Legalize G_ABDS and G_ABDURichard-Qin-X2026-08-144-178/+168
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* [GlobalISel] Legalize G_ABSRichard-Qin-X2026-08-147-10/+307
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* [RISCV] Legalize va_copy intrinsicsRichard-Qin-X2026-08-143-0/+155
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* [MIR] Normalize explicit successor probabilitiesRichard-Qin-X2026-08-142-2/+37
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* [GlobalISel] Match LLVM legalization value trackingRichard-Qin-X2026-08-1411-52/+2180
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* [CodeGen] Match LLVM Legalizer ownershipRichard-Qin-X2026-08-1414-3221/+2094
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* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-1319-766/+651
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* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-136-150/+487
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* [CodeGen] Match LLVM branch relaxation semanticsRichard-Qin-X2026-08-134-15/+87
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* [RISCV] Model non-ISA subtarget featuresRichard-Qin-X2026-08-131-7/+70
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* [RISCV] Match LLVM register bank mappingsRichard-Qin-X2026-08-135-64/+480
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* [MIR] Omit predictable successors in simplified outputRichard-Qin-X2026-08-132-24/+69
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* [CodeGen] Preserve LLT annotations on generic opcodesRichard-Qin-X2026-08-131-2/+3
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* [CodeGen] Derive quality inputs from source listRichard-Qin-X2026-08-131-163/+12
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* [RISCV] Preserve wide carry instruction orderRichard-Qin-X2026-08-131-10/+18
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* [RISCV] Centralize legalizer register type queriesRichard-Qin-X2026-08-131-118/+97
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* [MIR] Qualify pointer iteratorsRichard-Qin-X2026-08-131-3/+3
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* [Tooling] Avoid unchecked pipeline selectorsRichard-Qin-X2026-08-131-3/+2
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* [CodeGen] Reuse register diagnostic formattingRichard-Qin-X2026-08-131-2/+1
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* [TableGen] Fix quality tool source pathsRichard-Qin-X2026-08-131-0/+1
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* [Tooling] Remove the duplicate output kindRichard-Qin-X2026-08-134-118/+66
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* [RISCV] Remove physical register forwarding helpersRichard-Qin-X2026-08-133-57/+39
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* [RISCV] Use the generated opcode conversionRichard-Qin-X2026-08-138-194/+164
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* [Support] Centralize error context handlingRichard-Qin-X2026-08-1329-234/+117
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* [CodeGen] Remove the unused property queryRichard-Qin-X2026-08-131-4/+0
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* [TableGen] Split the target description generatorRichard-Qin-X2026-08-137-3102/+1281
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* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-1316-2268/+2168
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* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-1315-1852/+1785
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* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-1325-4921/+4633
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* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-1341-673/+284
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* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-1338-1195/+1310
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* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-134-487/+634
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* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-1231-6674/+6892
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* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-128-761/+964
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* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-1213-243/+166
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* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-1210-23/+35
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* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-121-14/+0
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* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-1210-129/+359
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