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* [CodeGen] Separate pass instrumentation ownershipRichard-Qin-X2026-08-284-476/+410
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* [CodeGen] Remove pass instrumentation snapshotsRichard-Qin-X2026-08-281-90/+10
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* [CodeGen] Centralize machine instruction erasureRichard-Qin-X2026-08-2828-473/+145
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* [GlobalISel] Generate floating memory selectionRichard-Qin-X2026-08-274-143/+138
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* [RISCV] Generate atomic RMW selectionRichard-Qin-X2026-08-273-95/+366
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* [RISCV] Remove unused selector helpersRichard-Qin-X2026-08-271-80/+0
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* [GlobalISel] Select each instruction onceRichard-Qin-X2026-08-272-87/+0
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* [CodeGen] Remove machine action replayRichard-Qin-X2026-08-274-172/+16
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* [CodeGen] Run machine optimizations onceRichard-Qin-X2026-08-2711-215/+17
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* [CodeGen] Run scheduling transformations onceRichard-Qin-X2026-08-265-136/+27
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* [CodeGen] Remove transactional register allocationRichard-Qin-X2026-08-268-169/+42
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* [CodeGen] Run SSA exit transformations onceRichard-Qin-X2026-08-262-55/+18
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* [GlobalISel] Run machine transformations onceRichard-Qin-X2026-08-263-75/+14
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* [CodeGen] Centralize machine pass property validationRichard-Qin-X2026-08-2624-169/+0
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* [RISCV] Implement push-pop optimizationRichard-Qin-X2026-08-269-23/+312
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* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-267-4/+627
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* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-267-43/+463
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* [RISCV] Optimize W instructionsRichard-Qin-X2026-08-264-0/+642
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* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-2514-41/+438
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* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-259-4/+485
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* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-257-6/+1047
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* [RISCV] Implement base offset mergingRichard-Qin-X2026-08-254-0/+522
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* [RISCV] Implement Zcmp move mergingRichard-Qin-X2026-08-258-0/+391
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* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-244-1/+443
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* [RISCV] Implement save and restore libcallsRichard-Qin-X2026-08-243-75/+347
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* [CodeGen] Match LLVM callee-save live-insRichard-Qin-X2026-08-241-1/+1
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* [RISCV] Match LLVM compressed stack frame loweringRichard-Qin-X2026-08-244-98/+83
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* [RISCV] Match LLVM large call frame loweringRichard-Qin-X2026-08-243-209/+290
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* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-2410-221/+373
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* [CodeGen] Match LLVM machine combiner semanticsRichard-Qin-X2026-08-244-297/+173
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* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-2411-151/+140
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* [CodeGen] Implement RISC-V peephole branch optimizationRichard-Qin-X2026-08-244-1/+324
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* [RISCV] Generate MC pseudo loweringRichard-Qin-X2026-08-226-195/+145
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* [CodeGen] Match LLVM machine debug strippingRichard-Qin-X2026-08-225-1/+62
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* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-2219-78/+830
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* [CodeGen] Match LLVM final verifier contractRichard-Qin-X2026-08-191-2/+2
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* [CodeGen] Match LLVM finalization contractRichard-Qin-X2026-08-191-2/+2
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* [CodeGen] Match LLVM late pseudo contractRichard-Qin-X2026-08-191-2/+2
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* [CodeGen] Remove RCC fallthrough normalizationRichard-Qin-X2026-08-193-169/+0
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* [CodeGen] Match LLVM block placement contractRichard-Qin-X2026-08-191-6/+2
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* [CodeGen] Unify LLVM branch folding pipelineRichard-Qin-X2026-08-194-424/+304
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* [CodeGen] Match LLVM tail duplication contractRichard-Qin-X2026-08-191-9/+1
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* [CodeGen] Match LLVM post-machine scheduler contractRichard-Qin-X2026-08-191-7/+1
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* [CodeGen] Match LLVM post-RA pseudo expansion contractRichard-Qin-X2026-08-191-7/+1
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* [CodeGen] Remove non-LLVM machine DCE placementsRichard-Qin-X2026-08-191-6/+0
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* [CodeGen] Remove unsupported post-frame combinerRichard-Qin-X2026-08-193-24/+1
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* [CodeGen] Remove unsupported pre-PEI pseudo expansionRichard-Qin-X2026-08-192-39/+2
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* [CodeGen] Match LLVM shrink wrapping contractRichard-Qin-X2026-08-191-7/+1
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* [CodeGen] Match LLVM post-RA sink contractRichard-Qin-X2026-08-191-3/+1
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* [CodeGen] Match LLVM post-RA LICM contractRichard-Qin-X2026-08-191-3/+1
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generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 08:47:22 +0000