rcc-project - An optimizing compiler for C.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[MIRTool] Parse LLVM code generation options	Richard-Qin-X	2026-08-13	1	-0/+85
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*	[MIRTool] Read stdin when no input path is given	Richard-Qin-X	2026-08-13	1	-2/+2
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*	[Tooling] Remove the duplicate output kind	Richard-Qin-X	2026-08-13	1	-41/+14
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*	[TableGen] Split the target description generator	Richard-Qin-X	2026-08-13	3	-150/+0
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*	[RISCV] Split the GlobalISel target components	Richard-Qin-X	2026-08-12	1	-1/+6
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*	[Tooling] Remove the duplicate assembly emitter	Richard-Qin-X	2026-08-12	5	-373/+0
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*	[Testing] Add the LLVM MIR RUN executor	Richard-Qin-X	2026-08-12	1	-0/+682
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*	[Tooling] Complete the LLVM MIR command-line contract	Richard-Qin-X	2026-08-12	5	-155/+176
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*	[Tooling] Adopt LLVM MIR command-line spellings	Richard-Qin-X	2026-08-12	4	-70/+142
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*	[MIR] Remove alternate layout and float APIs	Richard-Qin-X	2026-08-12	1	-1/+0
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*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	1	-0/+19
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*	[MIR] Accept fixed-baseline LLVM syntax	Richard-Qin-X	2026-08-11	2	-3/+23
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*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	7	-70/+1617
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	4	-7/+186
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*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	4	-0/+263
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	1	-3/+8
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	1	-7/+15
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	3	-0/+139
	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.