rcc-project - An optimizing compiler for C.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[RISCV] Remove obsolete codegen tests	Richard-Qin-X	2026-08-15	1	-7/+0
\|
*	[TableGen] Split the target description generator	Richard-Qin-X	2026-08-13	1	-9/+6
\|
*	[RISCV] Split the GlobalISel target components	Richard-Qin-X	2026-08-12	1	-8/+2
\|
*	[RISCV] Consolidate instruction behavior in RISCVInstrInfo	Richard-Qin-X	2026-08-12	1	-0/+8
\|
*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	1	-0/+30
\|
*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	1	-0/+13
\|
*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	1	-0/+13
\|
*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	1	-0/+13
\|
*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	1	-0/+13
\|
*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	1	-0/+7
\|
*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	1	-0/+7
\|
*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	1	-0/+7
\|
*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	1	-1/+20
\| \| \| \|	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
*	[CodeGen] Add target register descriptions	Richard-Qin-X	2026-08-01	1	-0/+17
	Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.