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path: root/backend/unittests/Target/DescriptionGeneratorTest.cpp
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* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-091-1/+1
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* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-091-1/+1
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* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-091-16/+17
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* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-071-21/+104
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* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-071-0/+118
Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.