| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [CodeGen] Align pass manager ownership | Richard-Qin-X | 2026-08-13 | 1 | -25/+25 |
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| * | [CodeGen] Split machine liveness components | Richard-Qin-X | 2026-08-13 | 1 | -1/+1 |
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| * | [RISCV] Split the GlobalISel target components | Richard-Qin-X | 2026-08-12 | 1 | -1/+1 |
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| * | [RISCV] Consolidate instruction behavior in RISCVInstrInfo | Richard-Qin-X | 2026-08-12 | 1 | -21/+34 |
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| * | [CodeGen] Add TargetInstrInfo ownership | Richard-Qin-X | 2026-08-12 | 1 | -1/+1 |
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| * | [RISCV] Model FFLAGS accesses | Richard-Qin-X | 2026-08-12 | 1 | -2/+18 |
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| * | [RISCV] Model typed floating-point register views | Richard-Qin-X | 2026-08-11 | 1 | -1/+2 |
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| * | [RISCV] Add LP64 calling-convention facts | Richard-Qin-X | 2026-08-11 | 1 | -1/+1 |
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| * | [CodeGen] Remove redundant numeric call-site IDs | Richard-Qin-X | 2026-08-11 | 1 | -2/+1 |
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| * | [Tooling] Complete backend tooling and validation | Richard-Qin-X | 2026-08-10 | 1 | -1/+2 |
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| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -0/+1432 |
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