rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[RISCV] Make target memory operands optional	Richard-Qin-X	2026-08-12	1	-2/+12
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*	[RISCV] Legalize G_PTR_ADD with s64 offsets	Richard-Qin-X	2026-08-12	1	-0/+27
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*	[RISCV] Legalize G_FRAME_INDEX for p0	Richard-Qin-X	2026-08-12	1	-0/+50
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*	[RISCV] Legalize G_VAARG	Richard-Qin-X	2026-08-12	1	-0/+89
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*	[RISCV] Accept symbolic low operands in loads and stores	Richard-Qin-X	2026-08-12	1	-0/+32
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*	[RISCV] Legalize llvm.va_copy	Richard-Qin-X	2026-08-12	1	-0/+81
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*	[RISCV] Allow frame indices in ADDI	Richard-Qin-X	2026-08-12	1	-4/+5
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*	[RISCV] Model dynamic rounding-mode state	Richard-Qin-X	2026-08-12	1	-7/+15
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*	[RISCV] Model FFLAGS accesses	Richard-Qin-X	2026-08-12	2	-6/+29
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*	[RISCV] Describe the GPR select pseudo	Richard-Qin-X	2026-08-12	1	-1/+1
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*	[RISCV] Model target-specific generic opcodes	Richard-Qin-X	2026-08-12	1	-1/+1
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*	[RISCV] Support absolute address operand flags	Richard-Qin-X	2026-08-12	2	-3/+51
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*	[RISCV] Model typed floating-point register views	Richard-Qin-X	2026-08-11	7	-78/+120
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*	[RISCV] Order call operands like LLVM MIR	Richard-Qin-X	2026-08-11	1	-7/+20
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*	[RISCV] Add LP64 calling-convention facts	Richard-Qin-X	2026-08-11	4	-13/+47
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*	[CodeGen] Remove redundant numeric call-site IDs	Richard-Qin-X	2026-08-11	3	-9/+4
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*	[RISCV] Derive the generated instruction count in tests	Richard-Qin-X	2026-08-11	1	-1/+5
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*	[RISCV] Match LLVM call-frame pseudo semantics	Richard-Qin-X	2026-08-11	2	-11/+47
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*	[RISCV] Use canonical copies for full ABI values	Richard-Qin-X	2026-08-11	1	-3/+5
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*	[RISCV] Lower multiply without M through libcalls	Richard-Qin-X	2026-08-11	1	-0/+59
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*	[RISCV] Accept generic scalars in call lowering	Richard-Qin-X	2026-08-11	1	-0/+16
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*	[RISCV] Fold narrow binary artifact chains	Richard-Qin-X	2026-08-11	1	-0/+69
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*	[RISCV] Preserve folded constant placement	Richard-Qin-X	2026-08-11	1	-3/+20
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*	[RISCV] Reuse compare operand extensions	Richard-Qin-X	2026-08-11	1	-0/+43
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*	[RISCV] Legalize integer compares to RV64 containers	Richard-Qin-X	2026-08-11	1	-16/+53
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*	[RISCV] Preserve live constants when folding extensions	Richard-Qin-X	2026-08-11	1	-0/+49
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*	[RISCV] Lower cmpxchg with success	Richard-Qin-X	2026-08-11	1	-1/+37
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*	[RISCV] Preserve narrow cmpxchg results when widening	Richard-Qin-X	2026-08-11	1	-0/+37
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*	[RISCV] Legalize narrow atomic compare exchange	Richard-Qin-X	2026-08-11	1	-0/+86
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*	[RISCV] Legalize fixed-baseline RV64 MachineIR	Richard-Qin-X	2026-08-11	4	-6/+6
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*	[Tooling] Complete backend tooling and validation	Richard-Qin-X	2026-08-10	1	-1/+2
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*	[MC] Implement RV64GC object emission	Richard-Qin-X	2026-08-09	6	-1/+1509
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*	[MC] Implement RV64GC assembly emission	Richard-Qin-X	2026-08-09	5	-0/+235
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	4	-3/+1448
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*	[CodeGen] Implement RV64GC frame lowering	Richard-Qin-X	2026-08-09	3	-0/+1416
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	3	-16/+521
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*	[CodeGen] Implement machine liveness analysis	Richard-Qin-X	2026-08-09	1	-2/+11
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*	[CodeGen] Implement machine SSA exit	Richard-Qin-X	2026-08-08	2	-0/+353
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*	[CodeGen] Implement RV64GC legalization and instruction selection	Richard-Qin-X	2026-08-08	2	-0/+1115
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*	[CodeGen] Complete machine pass and ABI lowering infrastructure	Richard-Qin-X	2026-08-07	2	-0/+809
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	2	-23/+199
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	4	-2/+249
\| \| \| \|	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
*	[CodeGen] Add target MIR text schema	Richard-Qin-X	2026-08-03	2	-1/+42
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*	[CodeGen] Add target register descriptions	Richard-Qin-X	2026-08-01	3	-0/+258
	Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.