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A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.
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Author
Age
Files
Lines
*
[CodeGen] Split PHI elimination and two-address rewriting
Richard-Qin-X
2026-08-13
1
-1
/
+1
|
*
[RISCV] Split the GlobalISel target components
Richard-Qin-X
2026-08-12
7
-201
/
+171
|
*
[RISCV] Consolidate instruction behavior in RISCVInstrInfo
Richard-Qin-X
2026-08-12
3
-35
/
+113
|
*
[CodeGen] Add TargetInstrInfo ownership
Richard-Qin-X
2026-08-12
1
-1
/
+1
|
*
[RISCV] Describe vector tuple registers
Richard-Qin-X
2026-08-12
1
-2
/
+13
|
*
[RISCV] Describe vector physical registers
Richard-Qin-X
2026-08-12
1
-3
/
+12
|
*
[RISCV] Add Zba and Zbb instruction descriptions
Richard-Qin-X
2026-08-12
3
-6
/
+39
|
*
[RISCV] Make call-preserved masks optional
Richard-Qin-X
2026-08-12
1
-1
/
+5
|
*
[RISCV] Make target memory operands optional
Richard-Qin-X
2026-08-12
1
-2
/
+12
|
*
[RISCV] Legalize G_PTR_ADD with s64 offsets
Richard-Qin-X
2026-08-12
1
-0
/
+27
|
*
[RISCV] Legalize G_FRAME_INDEX for p0
Richard-Qin-X
2026-08-12
1
-0
/
+50
|
*
[RISCV] Legalize G_VAARG
Richard-Qin-X
2026-08-12
1
-0
/
+89
|
*
[RISCV] Accept symbolic low operands in loads and stores
Richard-Qin-X
2026-08-12
1
-0
/
+32
|
*
[RISCV] Legalize llvm.va_copy
Richard-Qin-X
2026-08-12
1
-0
/
+81
|
*
[RISCV] Allow frame indices in ADDI
Richard-Qin-X
2026-08-12
1
-4
/
+5
|
*
[RISCV] Model dynamic rounding-mode state
Richard-Qin-X
2026-08-12
1
-7
/
+15
|
*
[RISCV] Model FFLAGS accesses
Richard-Qin-X
2026-08-12
2
-6
/
+29
|
*
[RISCV] Describe the GPR select pseudo
Richard-Qin-X
2026-08-12
1
-1
/
+1
|
*
[RISCV] Model target-specific generic opcodes
Richard-Qin-X
2026-08-12
1
-1
/
+1
|
*
[RISCV] Support absolute address operand flags
Richard-Qin-X
2026-08-12
2
-3
/
+51
|
*
[RISCV] Model typed floating-point register views
Richard-Qin-X
2026-08-11
7
-78
/
+120
|
*
[RISCV] Order call operands like LLVM MIR
Richard-Qin-X
2026-08-11
1
-7
/
+20
|
*
[RISCV] Add LP64 calling-convention facts
Richard-Qin-X
2026-08-11
4
-13
/
+47
|
*
[CodeGen] Remove redundant numeric call-site IDs
Richard-Qin-X
2026-08-11
3
-9
/
+4
|
*
[RISCV] Derive the generated instruction count in tests
Richard-Qin-X
2026-08-11
1
-1
/
+5
|
*
[RISCV] Match LLVM call-frame pseudo semantics
Richard-Qin-X
2026-08-11
2
-11
/
+47
|
*
[RISCV] Use canonical copies for full ABI values
Richard-Qin-X
2026-08-11
1
-3
/
+5
|
*
[RISCV] Lower multiply without M through libcalls
Richard-Qin-X
2026-08-11
1
-0
/
+59
|
*
[RISCV] Accept generic scalars in call lowering
Richard-Qin-X
2026-08-11
1
-0
/
+16
|
*
[RISCV] Fold narrow binary artifact chains
Richard-Qin-X
2026-08-11
1
-0
/
+69
|
*
[RISCV] Preserve folded constant placement
Richard-Qin-X
2026-08-11
1
-3
/
+20
|
*
[RISCV] Reuse compare operand extensions
Richard-Qin-X
2026-08-11
1
-0
/
+43
|
*
[RISCV] Legalize integer compares to RV64 containers
Richard-Qin-X
2026-08-11
1
-16
/
+53
|
*
[RISCV] Preserve live constants when folding extensions
Richard-Qin-X
2026-08-11
1
-0
/
+49
|
*
[RISCV] Lower cmpxchg with success
Richard-Qin-X
2026-08-11
1
-1
/
+37
|
*
[RISCV] Preserve narrow cmpxchg results when widening
Richard-Qin-X
2026-08-11
1
-0
/
+37
|
*
[RISCV] Legalize narrow atomic compare exchange
Richard-Qin-X
2026-08-11
1
-0
/
+86
|
*
[RISCV] Legalize fixed-baseline RV64 MachineIR
Richard-Qin-X
2026-08-11
4
-6
/
+6
|
*
[Tooling] Complete backend tooling and validation
Richard-Qin-X
2026-08-10
1
-1
/
+2
|
*
[MC] Implement RV64GC object emission
Richard-Qin-X
2026-08-09
6
-1
/
+1509
|
*
[MC] Implement RV64GC assembly emission
Richard-Qin-X
2026-08-09
5
-0
/
+235
|
*
[CodeGen] Implement machine optimization and scheduling
Richard-Qin-X
2026-08-09
4
-3
/
+1448
|
*
[CodeGen] Implement RV64GC frame lowering
Richard-Qin-X
2026-08-09
3
-0
/
+1416
|
*
[CodeGen] Complete register allocation infrastructure
Richard-Qin-X
2026-08-09
3
-16
/
+521
|
*
[CodeGen] Implement machine liveness analysis
Richard-Qin-X
2026-08-09
1
-2
/
+11
|
*
[CodeGen] Implement machine SSA exit
Richard-Qin-X
2026-08-08
2
-0
/
+353
|
*
[CodeGen] Implement RV64GC legalization and instruction selection
Richard-Qin-X
2026-08-08
2
-0
/
+1115
|
*
[CodeGen] Complete machine pass and ABI lowering infrastructure
Richard-Qin-X
2026-08-07
2
-0
/
+809
|
*
[RISCV] Complete RV64GC instruction description
Richard-Qin-X
2026-08-07
2
-23
/
+199
|
*
[RISCV] Add generated RV64GC register description
Richard-Qin-X
2026-08-07
4
-2
/
+249
|
|
|
|
Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
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