aboutsummaryrefslogtreecommitdiff
path: root/backend/utils
Commit message (Collapse)AuthorAgeFilesLines
* [TableGen] Assert normalized MC pseudo operandsRichard-Qin-X2026-08-291-0/+2
|
* [TableGen] Preserve optional target description valuesRichard-Qin-X2026-08-291-4/+5
|
* [Support] Use standard power-of-two checksRichard-Qin-X2026-08-283-8/+5
|
* [CMake] Remove unused clang-tidy file registrationRichard-Qin-X2026-08-281-4/+0
|
* [GlobalISel] Generate floating memory selectionRichard-Qin-X2026-08-273-15/+38
|
* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-261-1/+2
|
* [RISCV] Generate MC pseudo loweringRichard-Qin-X2026-08-228-12/+232
|
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-227-5/+339
|
* [CodeGen] Remove unsupported pre-PEI pseudo expansionRichard-Qin-X2026-08-191-2/+1
|
* [GlobalISel] Generate prelegalizer combiner rulesRichard-Qin-X2026-08-197-6/+512
|
* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-191-1/+2
|
* [RISCV][GlobalISel] Generate integer load selectionRichard-Qin-X2026-08-193-5/+28
|
* [RISCV][GlobalISel] Match floating comparisonsRichard-Qin-X2026-08-193-4/+68
|
* [RISCV][GlobalISel] Generate indirect branch selectionRichard-Qin-X2026-08-193-0/+28
|
* [RISCV][GlobalISel] Generate conditional branch selectionRichard-Qin-X2026-08-173-2/+24
|
* [RISCV][GlobalISel] Generate implicit-def selectionRichard-Qin-X2026-08-171-5/+10
|
* [RISCV][GlobalISel] Generate integer extension selectionsRichard-Qin-X2026-08-173-68/+109
|
* [RISCV][GlobalISel] Generate shift selectionsRichard-Qin-X2026-08-163-14/+181
|
* [RISCV][GlobalISel] Generate integer comparisonsRichard-Qin-X2026-08-163-73/+256
|
* [RISCV][GlobalISel] Select comparisons against zeroRichard-Qin-X2026-08-163-3/+232
|
* tablegen: Generate GlobalISel match tablesRichard-Qin-X2026-08-167-20/+469
|
* [RISCV][GlobalISel] Legalize floating-point to integer conversionsRichard-Qin-X2026-08-153-1/+24
|
* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-131-1/+2
|
* [CodeGen] Match LLVM branch relaxation semanticsRichard-Qin-X2026-08-133-2/+9
|
* [TableGen] Fix quality tool source pathsRichard-Qin-X2026-08-131-0/+1
|
* [RISCV] Use the generated opcode conversionRichard-Qin-X2026-08-131-1/+4
|
* [TableGen] Split the target description generatorRichard-Qin-X2026-08-1316-0/+2073