aboutsummaryrefslogtreecommitdiff
path: root/rv64cpu/rtl/core
Commit message (Collapse)AuthorAgeFilesLines
* Hazard unit and testsRichard Qin2026-03-181-0/+152
|
* refactor(core): address WB stage architectural and naming review feedbackRichard Qin2026-03-171-12/+17
| | | | | | | | - Renamed `wb_reg_write_data` and `wb_reg_write_addr` to `wb_rd_wdata` and `wb_rd_addr` respectively to comply with `docs/naming_convention.md`. - Removed the 64-bit adder for `mem_wb_pc + 64'd4` from the WB stage to improve timing. Introduced a new `mem_wb_pc_plus_4` pipeline input instead. - Added a `has_trap` signal to gate architectural state updates (`wb_reg_write_en` and `csr_req`) upon exceptions, ensuring precise exceptions without corrupting the register file or CSRs. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
* Write Back stage unit and testsRichard Qin2026-03-181-0/+116
|
* docs: Finalized Richard CPU RTL architectural and naming convention audit ↵Richard Qin2026-03-177-17/+595
| | | | | | | | report. No source code changes were made; this branch serves as the finalized state for the provided audit. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
* Execute Stage unit and testsRichard Qin2026-03-171-0/+114
|
* ID/EX Pipeline Register and testsRichard Qin2026-03-171-0/+174
|
* IF/ID RegFile and testsRichard Qin2026-03-171-0/+57
|
* Instruction Decoder Stage unit and testsRichard Qin2026-03-171-0/+142
|
* Instruction fetching stage unit and testRichard Qin2026-03-161-0/+60
|
* branch unit and testRichard Qin2026-03-162-0/+65
|
* fix naming problemsRichard Qin2026-03-163-39/+39
|
* Decoder unit and testRichard Qin2026-03-161-0/+390
|
* Register file unit and testRichard Qin2026-03-161-0/+60
|
* Add and test alu unitRichard Qin2026-03-152-0/+160
|
* initial commit: project architectureRichard Qin2026-03-156-0/+0
generated by cgit v1.2.3 (git 2.46.0) at 2026-11-09 23:10:02 +0000