rcc-project - A collection of systems software, from virtual machines and compilers to developer tools and terminal applications.

	Commit message (Collapse)	Author	Age	Files	Lines
*	refactor: reorganize RTL directory structure	Richard Qin	3 days	1	-0/+0
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*	checkpoint: preserve current RV64 CPU development state	Richard Qin	3 days	1	-12/+28
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*	refactor: standardize interrupt signal naming across the codebase	Richard Qin	2026-04-07	1	-9/+9
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*	refactor: standardize interrupt signal naming across the codebase	Richard Qin	2026-04-07	1	-12/+12
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*	feat: Complete CSR/privileged/exception interrupt path and fill in strict ↵	Richard Qin	2026-04-01	1	-7/+418
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	acceptance tests - Refactor trap/CSR data path in the Core, unified with trap_ctrl interface to drive CSR update and return process - Improve critical paths for exception/interrupt handling: ecall, illegal, load fault, external interrupt, mret/sret return - Adjust pipeline stage registers with flush/stall coordination, fix residual control signal issues in trap scenarios - Enhance decode and related pipeline module behavior consistency, fill in missing control signal propagation across registers - Expand core integration testing, add trap/interrupt scenarios and CLI dispatch that can be executed per case - Extend CSR unit test coverage: read/write semantics, privilege switching, delegation and nested returns, illegal access protection, etc. - Register new core scenario cases in CTest to form a regression-capable P2 strict acceptance suite Verification: - Build passed - Full CTest passed (22/22)
*	Add fibonacci tests and fix bugs	Richard Qin	2026-03-18	1	-0/+61
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*	fixed vm_trace bug	Richard Qin	2026-03-18	1	-6/+6
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*	CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard Unit	Richard Qin	2026-03-18	1	-0/+648
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*	initial commit: project architecture	Richard Qin	2026-03-15	1	-0/+0