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* test(trap_ctrl): add store page fault unit test caseRichard Qin2026-03-311-2/+10
| | | | | | | | | Added a specific test scenario for Store Page Fault in tb/unit/tb_trap_ctrl.cc. - Defined EXC_STORE_PAGE_FAULT (15) constant. - Implemented a test case that asserts trap_store_page_fault and verifies mcause and mtval. - Improved clarity by renaming existing page fault test labels to LoadPageFault. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
* feat: Complete CSR/privileged/exception interrupt path and fill in strict ↵Richard Qin2026-04-018-66/+859
| | | | | | | | | | | | | | | | | acceptance tests - Refactor trap/CSR data path in the Core, unified with trap_ctrl interface to drive CSR update and return process - Improve critical paths for exception/interrupt handling: ecall, illegal, load fault, external interrupt, mret/sret return - Adjust pipeline stage registers with flush/stall coordination, fix residual control signal issues in trap scenarios - Enhance decode and related pipeline module behavior consistency, fill in missing control signal propagation across registers - Expand core integration testing, add trap/interrupt scenarios and CLI dispatch that can be executed per case - Extend CSR unit test coverage: read/write semantics, privilege switching, delegation and nested returns, illegal access protection, etc. - Register new core scenario cases in CTest to form a regression-capable P2 strict acceptance suite Verification: - Build passed - Full CTest passed (22/22)
* Trap Control unit and testsRichard Qin2026-03-192-0/+202
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* CSR unit and testsRichard Qin2026-03-192-9/+346
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* Add fibonacci tests and fix bugsRichard Qin2026-03-182-6/+68
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* fixed vm_trace bugRichard Qin2026-03-181-6/+6
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* CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-184-8/+696
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* Hazard unit and testsRichard Qin2026-03-182-0/+294
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* test(core): fix WB stage tests after naming and logic refactorRichard Qin2026-03-171-5/+8
| | | | | | | | | - Renamed `wb_reg_write_data` to `wb_rd_wdata` in all assertions to match the updated module ports. - Renamed `wb_reg_write_addr` to `wb_rd_addr` in all assertions. - Initialized the new `mem_wb_pc_plus_4` input in the testbench setup to correctly test the JAL/JALR datapath. - Added assertions to explicitly test that `wb_reg_write_en` and `csr_req` are gated when an exception occurs. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
* Write Back stage unit and testsRichard Qin2026-03-182-0/+124
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* docs: Finalized Richard CPU RTL architectural and naming convention audit ↵Richard Qin2026-03-176-3/+595
| | | | | | | | report. No source code changes were made; this branch serves as the finalized state for the provided audit. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
* Execute Stage unit and testsRichard Qin2026-03-172-0/+229
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* ID/EX Pipeline Register and testsRichard Qin2026-03-172-0/+180
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* IF/ID RegFile and testsRichard Qin2026-03-172-0/+136
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* Instruction Decoder Stage unit and testsRichard Qin2026-03-172-0/+203
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* Instruction fetching stage unit and testRichard Qin2026-03-162-0/+120
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* branch unit and testRichard Qin2026-03-162-0/+109
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* format outputRichard Qin2026-03-163-13/+20
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* expand tests and format outputRichard Qin2026-03-163-9/+124
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* fix naming problemsRichard Qin2026-03-163-37/+37
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* Decoder unit and testRichard Qin2026-03-162-9/+307
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* Register file unit and testRichard Qin2026-03-162-13/+112
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* LicenseRichard Qin2026-03-151-0/+17
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* Add and test alu unitRichard Qin2026-03-152-8/+75
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* initial commit: project architectureRichard Qin2026-03-157-0/+135
generated by cgit v1.2.3 (git 2.46.0) at 2026-11-09 23:35:31 +0000