From 64c0360a6646dd1d3f75b8d1ed11ec4da825256b Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Wed, 12 Aug 2026 04:07:06 +0800 Subject: [ThirdParty] Vendor LLVM RISC-V MIR tests --- third_party/llvm/LICENSE.TXT | 279 +++ third_party/llvm/README.md | 16 + .../llvm/test/CodeGen/RISCV/GlobalISel/combine.mir | 138 ++ .../GlobalISel/instruction-select/alu-rv32.mir | 572 +++++ .../GlobalISel/instruction-select/alu-rv64.mir | 603 +++++ .../GlobalISel/instruction-select/alu_m-rv32.mir | 188 ++ .../GlobalISel/instruction-select/alu_m-rv64.mir | 260 +++ .../instruction-select/atomic-cmpxchg-rv32.mir | 119 + .../instruction-select/atomic-cmpxchg-rv64.mir | 144 ++ .../instruction-select/atomicrmw-add-sub-rv32.mir | 153 ++ .../instruction-select/atomicrmw-add-sub-rv64.mir | 203 ++ .../GlobalISel/instruction-select/brcond-rv32.mir | 188 ++ .../GlobalISel/instruction-select/brcond-rv64.mir | 188 ++ .../instruction-select/brindirect-rv32.mir | 45 + .../instruction-select/brindirect-rv64.mir | 45 + .../GlobalISel/instruction-select/bswap-rv32.mir | 23 + .../GlobalISel/instruction-select/bswap-rv64.mir | 23 + .../GlobalISel/instruction-select/constant32.mir | 126 + .../GlobalISel/instruction-select/constant64.mir | 211 ++ .../RISCV/GlobalISel/instruction-select/copy32.mir | 71 + .../RISCV/GlobalISel/instruction-select/copy64.mir | 71 + .../GlobalISel/instruction-select/ctlz-rv32.mir | 22 + .../GlobalISel/instruction-select/ctlz-rv64.mir | 38 + .../GlobalISel/instruction-select/ctpop-rv32.mir | 22 + .../GlobalISel/instruction-select/ctpop-rv64.mir | 22 + .../GlobalISel/instruction-select/cttz-rv32.mir | 22 + .../GlobalISel/instruction-select/cttz-rv64.mir | 38 + .../instruction-select/fcmp-f16-rv32.mir | 355 +++ .../instruction-select/fcmp-f16-rv64.mir | 355 +++ .../GlobalISel/instruction-select/fcmp-rv32.mir | 706 ++++++ .../GlobalISel/instruction-select/fcmp-rv64.mir | 706 ++++++ .../GlobalISel/instruction-select/fp-arith-f16.mir | 366 +++ .../GlobalISel/instruction-select/fp-arith.mir | 576 +++++ .../instruction-select/fp-constant-f16.mir | 87 + .../GlobalISel/instruction-select/fp-constant.mir | 210 ++ .../instruction-select/fp-ext-trunc-f16.mir | 94 + .../GlobalISel/instruction-select/fp-ext-trunc.mir | 50 + .../instruction-select/fp-load-store.mir | 140 ++ .../instruction-select/fp-select-rv32.mir | 62 + .../instruction-select/fp-select-rv64.mir | 64 + .../instruction-select/fptoi-f16-rv32.mir | 48 + .../instruction-select/fptoi-f16-rv64.mir | 92 + .../GlobalISel/instruction-select/fptoi-rv32.mir | 92 + .../GlobalISel/instruction-select/fptoi-rv64.mir | 180 ++ .../instruction-select/frame-index-rv32.mir | 32 + .../instruction-select/frame-index-rv64.mir | 32 + .../instruction-select/global-value32.mir | 129 ++ .../instruction-select/global-value64.mir | 128 ++ .../GlobalISel/instruction-select/icmp-rv32.mir | 1117 +++++++++ .../GlobalISel/instruction-select/icmp-rv64.mir | 1117 +++++++++ .../instruction-select/implicit-def-rv32.mir | 59 + .../instruction-select/implicit-def-rv64.mir | 59 + .../instruction-select/int-ptr-cast-rv32.mir | 46 + .../instruction-select/int-ptr-cast-rv64.mir | 46 + .../instruction-select/is-fpclass-f16-rv32.mir | 82 + .../instruction-select/is-fpclass-f16-rv64.mir | 82 + .../instruction-select/is-fpclass-rv32.mir | 160 ++ .../instruction-select/is-fpclass-rv64.mir | 160 ++ .../instruction-select/itofp-f16-rv32.mir | 48 + .../instruction-select/itofp-f16-rv64.mir | 48 + .../GlobalISel/instruction-select/itofp-rv32.mir | 92 + .../GlobalISel/instruction-select/itofp-rv64.mir | 92 + .../GlobalISel/instruction-select/load-rv32.mir | 294 +++ .../GlobalISel/instruction-select/load-rv64.mir | 426 ++++ .../instruction-select/merge-unmerge-rv32.mir | 44 + .../GlobalISel/instruction-select/minmax-rv32.mir | 81 + .../GlobalISel/instruction-select/minmax-rv64.mir | 81 + .../GlobalISel/instruction-select/phi-rv32.mir | 88 + .../GlobalISel/instruction-select/phi-rv64.mir | 88 + .../GlobalISel/instruction-select/ptradd-rv32.mir | 50 + .../GlobalISel/instruction-select/ptradd-rv64.mir | 50 + .../GlobalISel/instruction-select/ptrmask-rv32.mir | 47 + .../GlobalISel/instruction-select/ptrmask-rv64.mir | 47 + .../GlobalISel/instruction-select/rotate-rv32.mir | 96 + .../GlobalISel/instruction-select/rotate-rv64.mir | 192 ++ .../GlobalISel/instruction-select/rvv/add.mir | 774 +++++++ .../GlobalISel/instruction-select/rvv/anyext.mir | 902 ++++++++ .../GlobalISel/instruction-select/rvv/icmp.mir | 534 +++++ .../instruction-select/rvv/render-vlop-rv32.mir | 76 + .../instruction-select/rvv/render-vlop-rv64.mir | 76 + .../GlobalISel/instruction-select/rvv/select.mir | 323 +++ .../GlobalISel/instruction-select/rvv/sext.mir | 900 ++++++++ .../GlobalISel/instruction-select/rvv/sub.mir | 774 +++++++ .../instruction-select/rvv/vmclr-rv32.mir | 124 + .../instruction-select/rvv/vmclr-rv64.mir | 124 + .../GlobalISel/instruction-select/rvv/vscale32.mir | 300 +++ .../GlobalISel/instruction-select/rvv/vscale64.mir | 139 ++ .../GlobalISel/instruction-select/rvv/zext.mir | 900 ++++++++ .../GlobalISel/instruction-select/select-rv32.mir | 175 ++ .../GlobalISel/instruction-select/select-rv64.mir | 205 ++ .../GlobalISel/instruction-select/sext-rv64.mir | 37 + .../GlobalISel/instruction-select/shift-rv32.mir | 246 ++ .../GlobalISel/instruction-select/shift-rv64.mir | 273 +++ .../GlobalISel/instruction-select/store-rv32.mir | 214 ++ .../GlobalISel/instruction-select/store-rv64.mir | 317 +++ .../RISCV/GlobalISel/instruction-select/trap.mir | 34 + .../GlobalISel/instruction-select/zba-rv32.mir | 152 ++ .../GlobalISel/instruction-select/zba-rv64.mir | 250 ++ .../GlobalISel/instruction-select/zext-rv64.mir | 31 + .../RISCV/GlobalISel/knownbits-copy-crash.mir | 36 + .../RISCV/GlobalISel/legalizer-info-validation.mir | 977 ++++++++ .../legalizer/legalize-abs-diff-rv32.mir | 316 +++ .../legalizer/legalize-abs-diff-rv64.mir | 344 +++ .../GlobalISel/legalizer/legalize-abs-rv32.mir | 132 ++ .../GlobalISel/legalizer/legalize-abs-rv64.mir | 135 ++ .../GlobalISel/legalizer/legalize-add-rv32.mir | 190 ++ .../GlobalISel/legalizer/legalize-add-rv64.mir | 211 ++ .../legalizer/legalize-addo-subo-rv32.mir | 553 +++++ .../legalizer/legalize-addo-subo-rv64.mir | 500 ++++ .../GlobalISel/legalizer/legalize-and-rv32.mir | 171 ++ .../GlobalISel/legalizer/legalize-and-rv64.mir | 191 ++ .../GlobalISel/legalizer/legalize-ashr-rv32.mir | 272 +++ .../GlobalISel/legalizer/legalize-ashr-rv64.mir | 321 +++ .../legalizer/legalize-atomic-cmpxchg-rv32.mir | 155 ++ .../legalizer/legalize-atomic-cmpxchg-rv64.mir | 240 ++ .../legalizer/legalize-atomicrmw-add-sub-rv32.mir | 198 ++ .../legalizer/legalize-atomicrmw-add-sub-rv64.mir | 264 +++ .../legalizer/legalize-bitreverse-rv32.mir | 478 ++++ .../legalizer/legalize-bitreverse-rv64.mir | 474 ++++ .../legalizer/legalize-brindirect-rv32.mir | 42 + .../legalizer/legalize-brindirect-rv64.mir | 42 + .../GlobalISel/legalizer/legalize-bswap-rv32.mir | 135 ++ .../GlobalISel/legalizer/legalize-bswap-rv64.mir | 143 ++ .../GlobalISel/legalizer/legalize-const-rv32.mir | 126 + .../GlobalISel/legalizer/legalize-const-rv64.mir | 194 ++ .../legalizer/legalize-constbarrier-rv32.mir | 84 + .../legalizer/legalize-constbarrier-rv64.mir | 122 + .../GlobalISel/legalizer/legalize-ctls-rv32.mir | 412 ++++ .../GlobalISel/legalizer/legalize-ctls-rv64.mir | 386 ++++ .../GlobalISel/legalizer/legalize-ctlz-rv32.mir | 602 +++++ .../GlobalISel/legalizer/legalize-ctlz-rv64.mir | 556 +++++ .../GlobalISel/legalizer/legalize-ctpop-rv32.mir | 231 ++ .../GlobalISel/legalizer/legalize-ctpop-rv64.mir | 330 +++ .../GlobalISel/legalizer/legalize-cttz-rv32.mir | 506 ++++ .../GlobalISel/legalizer/legalize-cttz-rv64.mir | 454 ++++ .../GlobalISel/legalizer/legalize-div-rv32.mir | 629 +++++ .../GlobalISel/legalizer/legalize-div-rv64.mir | 698 ++++++ .../legalizer/legalize-dyn-alloca-rv64.mir | 40 + .../GlobalISel/legalizer/legalize-ext-rv64.mir | 161 ++ .../GlobalISel/legalizer/legalize-extload-rv32.mir | 261 +++ .../GlobalISel/legalizer/legalize-extload-rv64.mir | 279 +++ .../legalizer/legalize-fcmp-f16-rv32.mir | 312 +++ .../legalizer/legalize-fcmp-f16-rv64.mir | 312 +++ .../GlobalISel/legalizer/legalize-fcmp-rv32.mir | 620 +++++ .../GlobalISel/legalizer/legalize-fcmp-rv64.mir | 620 +++++ .../GlobalISel/legalizer/legalize-fp-arith-f16.mir | 359 +++ .../GlobalISel/legalizer/legalize-fp-arith.mir | 586 +++++ .../legalizer/legalize-fp-ext-trunc-f16.mir | 82 + .../GlobalISel/legalizer/legalize-fp-ext-trunc.mir | 44 + .../legalizer/legalize-fp-load-store.mir | 82 + .../legalizer/legalize-fp-select-rv32.mir | 31 + .../legalizer/legalize-fptoi-f16-rv32.mir | 142 ++ .../legalizer/legalize-fptoi-f16-rv64.mir | 202 ++ .../legalizer/legalize-fptoi-rv32-libcall.mir | 395 ++++ .../GlobalISel/legalizer/legalize-fptoi-rv32.mir | 320 +++ .../legalizer/legalize-fptoi-rv64-libcall.mir | 471 ++++ .../GlobalISel/legalizer/legalize-fptoi-rv64.mir | 400 ++++ .../legalizer/legalize-frame-index-rv32.mir | 29 + .../legalizer/legalize-frame-index-rv64.mir | 29 + .../GlobalISel/legalizer/legalize-freeze-rv32.mir | 62 + .../GlobalISel/legalizer/legalize-freeze-rv64.mir | 96 + .../GlobalISel/legalizer/legalize-frem-rv32.mir | 130 ++ .../GlobalISel/legalizer/legalize-frem-rv64.mir | 130 ++ .../legalizer/legalize-fshl-fshr-rv32.mir | 364 +++ .../legalizer/legalize-fshl-fshr-rv64.mir | 294 +++ .../GlobalISel/legalizer/legalize-global-rv32.mir | 33 + .../GlobalISel/legalizer/legalize-global-rv64.mir | 33 + .../GlobalISel/legalizer/legalize-icmp-rv32.mir | 1585 +++++++++++++ .../GlobalISel/legalizer/legalize-icmp-rv64.mir | 1803 +++++++++++++++ .../legalizer/legalize-implicit-def-rv32.mir | 109 + .../legalizer/legalize-implicit-def-rv64.mir | 123 + .../legalizer/legalize-inttoptr-rv32.mir | 131 ++ .../legalizer/legalize-inttoptr-rv64.mir | 153 ++ .../legalizer/legalize-is-fpclass-f16-rv32.mir | 28 + .../legalizer/legalize-is-fpclass-f16-rv64.mir | 28 + .../legalizer/legalize-is-fpclass-rv32.mir | 52 + .../legalizer/legalize-is-fpclass-rv64.mir | 52 + .../legalizer/legalize-itofp-f16-rv32.mir | 185 ++ .../legalizer/legalize-itofp-f16-rv64.mir | 230 ++ .../GlobalISel/legalizer/legalize-itofp-rv32.mir | 366 +++ .../GlobalISel/legalizer/legalize-itofp-rv64.mir | 456 ++++ .../legalize-jump-table-brjt-medium-rv64.mir | 162 ++ .../legalize-jump-table-brjt-pic-rv32.mir | 158 ++ .../legalize-jump-table-brjt-pic-rv64.mir | 163 ++ .../legalizer/legalize-jump-table-brjt-rv32.mir | 159 ++ .../legalize-jump-table-brjt-small-rv64.mir | 163 ++ .../GlobalISel/legalizer/legalize-load-rv32.mir | 431 ++++ .../GlobalISel/legalizer/legalize-load-rv64.mir | 637 +++++ .../GlobalISel/legalizer/legalize-lshr-rv32.mir | 259 +++ .../GlobalISel/legalizer/legalize-lshr-rv64.mir | 332 +++ .../legalizer/legalize-memcpy-inline.mir | 48 + .../GlobalISel/legalizer/legalize-mul-ext-rv32.mir | 230 ++ .../GlobalISel/legalizer/legalize-mul-ext-rv64.mir | 248 ++ .../GlobalISel/legalizer/legalize-mul-rv32.mir | 161 ++ .../GlobalISel/legalizer/legalize-mul-rv64.mir | 186 ++ .../GlobalISel/legalizer/legalize-mulo-rv32.mir | 336 +++ .../GlobalISel/legalizer/legalize-mulo-rv64.mir | 438 ++++ .../GlobalISel/legalizer/legalize-or-rv32.mir | 171 ++ .../GlobalISel/legalizer/legalize-or-rv64.mir | 191 ++ .../GlobalISel/legalizer/legalize-phi-rv32.mir | 622 +++++ .../GlobalISel/legalizer/legalize-phi-rv64.mir | 703 ++++++ .../GlobalISel/legalizer/legalize-ptrmask-rv32.mir | 22 + .../GlobalISel/legalizer/legalize-ptrmask-rv64.mir | 22 + .../legalizer/legalize-ptrtoint-rv32.mir | 125 + .../legalizer/legalize-ptrtoint-rv64.mir | 145 ++ .../GlobalISel/legalizer/legalize-rem-rv32.mir | 539 +++++ .../GlobalISel/legalizer/legalize-rem-rv64.mir | 610 +++++ .../GlobalISel/legalizer/legalize-rotate-rv32.mir | 338 +++ .../GlobalISel/legalizer/legalize-rotate-rv64.mir | 300 +++ .../GlobalISel/legalizer/legalize-sadde-rv32.mir | 184 ++ .../GlobalISel/legalizer/legalize-sadde-rv64.mir | 225 ++ .../GlobalISel/legalizer/legalize-sat-rv32.mir | 573 +++++ .../GlobalISel/legalizer/legalize-sat-rv64.mir | 475 ++++ .../GlobalISel/legalizer/legalize-select-rv32.mir | 219 ++ .../GlobalISel/legalizer/legalize-select-rv64.mir | 256 +++ .../GlobalISel/legalizer/legalize-shl-rv32.mir | 234 ++ .../GlobalISel/legalizer/legalize-shl-rv64.mir | 280 +++ .../GlobalISel/legalizer/legalize-smax-rv32.mir | 131 ++ .../GlobalISel/legalizer/legalize-smax-rv64.mir | 144 ++ .../GlobalISel/legalizer/legalize-smin-rv32.mir | 131 ++ .../GlobalISel/legalizer/legalize-smin-rv64.mir | 144 ++ .../GlobalISel/legalizer/legalize-ssube-rv32.mir | 180 ++ .../GlobalISel/legalizer/legalize-ssube-rv64.mir | 220 ++ .../GlobalISel/legalizer/legalize-store-rv32.mir | 362 +++ .../GlobalISel/legalizer/legalize-store-rv64.mir | 461 ++++ .../GlobalISel/legalizer/legalize-sub-rv32.mir | 183 ++ .../GlobalISel/legalizer/legalize-sub-rv64.mir | 204 ++ .../legalizer/legalize-threeway-cmp-rv32.mir | 50 + .../legalizer/legalize-threeway-cmp-rv64.mir | 61 + .../GlobalISel/legalizer/legalize-uadde-rv32.mir | 184 ++ .../GlobalISel/legalizer/legalize-uadde-rv64.mir | 228 ++ .../GlobalISel/legalizer/legalize-umax-rv32.mir | 127 + .../GlobalISel/legalizer/legalize-umax-rv64.mir | 142 ++ .../GlobalISel/legalizer/legalize-umin-rv32.mir | 127 + .../GlobalISel/legalizer/legalize-umin-rv64.mir | 142 ++ .../GlobalISel/legalizer/legalize-vaarg-rv32.mir | 70 + .../GlobalISel/legalizer/legalize-vaarg-rv64.mir | 64 + .../RISCV/GlobalISel/legalizer/legalize-vacopy.mir | 23 + .../GlobalISel/legalizer/legalize-vastart-rv32.mir | 29 + .../GlobalISel/legalizer/legalize-vastart-rv64.mir | 29 + .../GlobalISel/legalizer/legalize-xor-rv32.mir | 171 ++ .../GlobalISel/legalizer/legalize-xor-rv64.mir | 191 ++ .../GlobalISel/legalizer/merge-unmerge-rv32.mir | 133 ++ .../GlobalISel/legalizer/merge-unmerge-rv32d.mir | 38 + .../GlobalISel/legalizer/merge-unmerge-rv64.mir | 119 + .../legalizer/rvv/legalize-add-zve32x.mir | 274 +++ .../GlobalISel/legalizer/rvv/legalize-add.mir | 399 ++++ .../GlobalISel/legalizer/rvv/legalize-and.mir | 399 ++++ .../GlobalISel/legalizer/rvv/legalize-anyext.mir | 1545 +++++++++++++ .../GlobalISel/legalizer/rvv/legalize-bitcast.mir | 356 +++ .../legalizer/rvv/legalize-extract-subvector.mir | 484 ++++ .../GlobalISel/legalizer/rvv/legalize-icmp.mir | 712 ++++++ .../legalizer/rvv/legalize-implicit-def.mir | 410 ++++ .../legalizer/rvv/legalize-insert-subvector.mir | 826 +++++++ .../legalizer/rvv/legalize-insertelement-rv32.mir | 1742 ++++++++++++++ .../legalizer/rvv/legalize-insertelement-rv64.mir | 1731 ++++++++++++++ .../legalizer/rvv/legalize-load-rv32.mir | 79 + .../legalizer/rvv/legalize-load-rv64.mir | 60 + .../GlobalISel/legalizer/rvv/legalize-load.mir | 971 ++++++++ .../RISCV/GlobalISel/legalizer/rvv/legalize-or.mir | 399 ++++ .../GlobalISel/legalizer/rvv/legalize-select.mir | 400 ++++ .../GlobalISel/legalizer/rvv/legalize-sext.mir | 1545 +++++++++++++ .../legalizer/rvv/legalize-splatvector-rv32.mir | 701 ++++++ .../legalizer/rvv/legalize-splatvector-rv64.mir | 788 +++++++ .../rvv/legalize-splatvector-s64-rv32.mir | 112 + .../legalizer/rvv/legalize-store-rv32.mir | 79 + .../legalizer/rvv/legalize-store-rv64.mir | 60 + .../GlobalISel/legalizer/rvv/legalize-store.mir | 971 ++++++++ .../GlobalISel/legalizer/rvv/legalize-sub.mir | 399 ++++ .../legalizer/rvv/legalize-vscale-rv32.mir | 226 ++ .../legalizer/rvv/legalize-vscale-rv64.mir | 109 + .../GlobalISel/legalizer/rvv/legalize-xor.mir | 399 ++++ .../GlobalISel/legalizer/rvv/legalize-zext.mir | 1545 +++++++++++++ .../RISCV/GlobalISel/regbankselect/alu-rv32.mir | 461 ++++ .../RISCV/GlobalISel/regbankselect/alu-rv64.mir | 482 ++++ .../RISCV/GlobalISel/regbankselect/copy-rv32.mir | 71 + .../RISCV/GlobalISel/regbankselect/copy-rv64.mir | 71 + .../GlobalISel/regbankselect/ext-trunc-rv64.mir | 71 + .../GlobalISel/regbankselect/fcmp-f16-rv32.mir | 27 + .../GlobalISel/regbankselect/fcmp-f16-rv64.mir | 27 + .../RISCV/GlobalISel/regbankselect/fcmp-rv32.mir | 49 + .../RISCV/GlobalISel/regbankselect/fcmp-rv64.mir | 49 + .../GlobalISel/regbankselect/fp-arith-f16.mir | 349 +++ .../RISCV/GlobalISel/regbankselect/fp-arith.mir | 552 +++++ .../GlobalISel/regbankselect/fp-ext-trunc-f16.mir | 92 + .../GlobalISel/regbankselect/fp-ext-trunc.mir | 50 + .../GlobalISel/regbankselect/fp-load-store.mir | 202 ++ .../GlobalISel/regbankselect/fp-select-rv32.mir | 181 ++ .../GlobalISel/regbankselect/fp-select-rv64.mir | 245 ++ .../GlobalISel/regbankselect/fptoi-f16-rv32.mir | 47 + .../GlobalISel/regbankselect/fptoi-f16-rv64.mir | 89 + .../RISCV/GlobalISel/regbankselect/fptoi-rv32.mir | 89 + .../RISCV/GlobalISel/regbankselect/fptoi-rv64.mir | 173 ++ .../RISCV/GlobalISel/regbankselect/frame-index.mir | 33 + .../RISCV/GlobalISel/regbankselect/global-rv32.mir | 28 + .../RISCV/GlobalISel/regbankselect/global-rv64.mir | 28 + .../GlobalISel/regbankselect/implicit-def-rv32.mir | 55 + .../GlobalISel/regbankselect/implicit-def-rv64.mir | 52 + .../regbankselect/is-fpclass-f16-rv32.mir | 31 + .../regbankselect/is-fpclass-f16-rv64.mir | 31 + .../GlobalISel/regbankselect/is-fpclass-rv32.mir | 58 + .../GlobalISel/regbankselect/is-fpclass-rv64.mir | 58 + .../GlobalISel/regbankselect/itofp-f16-rv32.mir | 47 + .../GlobalISel/regbankselect/itofp-f16-rv64.mir | 47 + .../RISCV/GlobalISel/regbankselect/itofp-rv32.mir | 89 + .../RISCV/GlobalISel/regbankselect/itofp-rv64.mir | 89 + .../regbankselect/jump-table-brjt-rv32.mir | 154 ++ .../regbankselect/jump-table-brjt-rv64.mir | 159 ++ .../RISCV/GlobalISel/regbankselect/load-rv32.mir | 173 ++ .../RISCV/GlobalISel/regbankselect/load-rv64.mir | 242 ++ .../regbankselect/merge-unmerge-rv32.mir | 40 + .../RISCV/GlobalISel/regbankselect/minmax-rv32.mir | 77 + .../RISCV/GlobalISel/regbankselect/minmax-rv64.mir | 77 + .../RISCV/GlobalISel/regbankselect/phi-rv32.mir | 89 + .../RISCV/GlobalISel/regbankselect/phi-rv64.mir | 89 + .../GlobalISel/regbankselect/ptrmask-rv32.mir | 24 + .../GlobalISel/regbankselect/ptrmask-rv64.mir | 24 + .../RISCV/GlobalISel/regbankselect/rvv/add.mir | 513 +++++ .../RISCV/GlobalISel/regbankselect/rvv/anyext.mir | 596 +++++ .../RISCV/GlobalISel/regbankselect/rvv/icmp.mir | 501 ++++ .../GlobalISel/regbankselect/rvv/implicit-def.mir | 315 +++ .../RISCV/GlobalISel/regbankselect/rvv/load.mir | 1134 +++++++++ .../RISCV/GlobalISel/regbankselect/rvv/select.mir | 404 ++++ .../RISCV/GlobalISel/regbankselect/rvv/sext.mir | 596 +++++ .../regbankselect/rvv/splatvector-rv32.mir | 549 +++++ .../regbankselect/rvv/splatvector-rv64.mir | 583 +++++ .../RISCV/GlobalISel/regbankselect/rvv/store.mir | 1134 +++++++++ .../RISCV/GlobalISel/regbankselect/rvv/sub.mir | 513 +++++ .../GlobalISel/regbankselect/rvv/vmclr-rv32.mir | 125 + .../GlobalISel/regbankselect/rvv/vmclr-rv64.mir | 125 + .../GlobalISel/regbankselect/rvv/vscale-rv32.mir | 48 + .../GlobalISel/regbankselect/rvv/vscale-rv64.mir | 25 + .../RISCV/GlobalISel/regbankselect/rvv/zext.mir | 596 +++++ .../RISCV/GlobalISel/regbankselect/select-rv32.mir | 63 + .../RISCV/GlobalISel/regbankselect/select-rv64.mir | 63 + .../RISCV/GlobalISel/regbankselect/store-rv32.mir | 89 + .../RISCV/GlobalISel/regbankselect/store-rv64.mir | 113 + .../GlobalISel/regbankselect/vec-args-ret.mir | 1259 ++++++++++ .../test/CodeGen/RISCV/MachineSink-implicit-x0.mir | 34 + .../llvm/llvm/test/CodeGen/RISCV/branch-opt.mir | 376 +++ .../llvm/llvm/test/CodeGen/RISCV/branch-rel.mir | 39 + .../test/CodeGen/RISCV/cfi-multiple-locations.mir | 36 + .../llvm/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.mir | 48 + .../llvm/test/CodeGen/RISCV/copy-frameindex.mir | 64 + .../test/CodeGen/RISCV/fold-addi-loadstore-cpi.mir | 76 + .../llvm/test/CodeGen/RISCV/fold-mem-offset.mir | 43 + .../CodeGen/RISCV/instruction-count-remark.mir | 75 + .../llvm/llvm/test/CodeGen/RISCV/live-sp.mir | 91 + .../llvm/test/CodeGen/RISCV/machine-combiner.mir | 87 + .../RISCV/machine-copyprop-noop-removal.mir | 78 + .../RISCV/machine-copyprop-simplifyinstruction.mir | 828 +++++++ .../llvm/llvm/test/CodeGen/RISCV/machine-cp.mir | 34 + .../machine-outliner-call-reg-live-across.mir | 354 +++ .../RISCV/machine-outliner-call-x5-liveout.mir | 136 ++ .../test/CodeGen/RISCV/machine-outliner-cfi.mir | 257 +++ .../CodeGen/RISCV/machine-outliner-position.mir | 96 + .../RISCV/machine-outliner-reserved-regs.mir | 166 ++ .../RISCV/machine-outliner-x5-regsave-rv32e.mir | 250 ++ .../CodeGen/RISCV/machine-outliner-x5-regsave.mir | 116 + .../CodeGen/RISCV/machineoutliner-jumptable.mir | 65 + .../CodeGen/RISCV/machineoutliner-pcrel-lo.mir | 383 ++++ .../llvm/test/CodeGen/RISCV/machineoutliner-x5.mir | 54 + .../llvm/test/CodeGen/RISCV/machineoutliner.mir | 147 ++ .../test/CodeGen/RISCV/macro-fusion-add-mem.mir | 102 + .../CodeGen/RISCV/macro-fusion-logic-imm-reg.mir | 62 + .../CodeGen/RISCV/macro-fusion-logic-reg-imm.mir | 62 + .../CodeGen/RISCV/macro-fusion-logic-reg-reg.mir | 64 + .../test/CodeGen/RISCV/macro-fusion-mul-add.mir | 67 + .../RISCV/macro-fusion-shift-bit-extract.mir | 132 ++ .../llvm/llvm/test/CodeGen/RISCV/macro-fusions.mir | 1552 +++++++++++++ .../RISCV/make-compressible-for-store-address.mir | 47 + .../test/CodeGen/RISCV/make-compressible-rv64.mir | 341 +++ .../test/CodeGen/RISCV/make-compressible-xqci.mir | 586 +++++ .../CodeGen/RISCV/make-compressible-zbc-zhinx.mir | 249 ++ .../test/CodeGen/RISCV/make-compressible-zbc.mir | 584 +++++ .../test/CodeGen/RISCV/make-compressible-zfinx.mir | 296 +++ .../test/CodeGen/RISCV/make-compressible-zilsd.mir | 370 +++ .../llvm/test/CodeGen/RISCV/make-compressible.mir | 1380 +++++++++++ .../test/CodeGen/RISCV/misched-mem-clustering.mir | 89 + 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285 +++ .../CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir | 523 +++++ .../RISCV/rvv/stack-coloring-scalablevec.mir | 39 + .../test/CodeGen/RISCV/rvv/stack-slot-coloring.mir | 324 +++ .../RISCV/rvv/subregister-undef-early-clobber.mir | 773 +++++++ .../RISCV/rvv/tail-agnostic-impdef-copy.mir | 65 + .../CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir | 89 + .../llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 2425 ++++++++++++++++++++ .../CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir | 15 + .../llvm/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir | 1110 +++++++++ .../RISCV/rvv/vl-optimizer-subreg-assert.mir | 32 + .../test/CodeGen/RISCV/rvv/vlopt-volatile-ld.mir | 13 + .../test/CodeGen/RISCV/rvv/vmerge-peephole.mir | 271 +++ .../llvm/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir | 334 +++ .../test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir | 190 ++ .../test/CodeGen/RISCV/rvv/vmv0-elimination.mir | 22 + .../CodeGen/RISCV/rvv/vsetvli-insert-coalesce.mir | 69 + .../CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir | 1109 +++++++++ .../CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir | 37 + .../llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir | 699 ++++++ .../llvm/llvm/test/CodeGen/RISCV/rvv/vxrm.mir | 30 + .../rvv/wrong-stack-offset-for-rvv-object.mir | 201 ++ .../CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir | 94 + .../CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir | 51 + .../CodeGen/RISCV/rvv/xsfmm-insert-vsetvl-TMTK.mir | 195 ++ .../llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir | 267 +++ .../llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir | 117 + .../CodeGen/RISCV/rvy/rvy-invalid-operands.mir | 34 + .../CodeGen/RISCV/select-optimize-multiple.mir | 212 ++ .../test/CodeGen/RISCV/sextw-removal-debug.mir | 59 + .../CodeGen/RISCV/sifive7-enable-intervals.mir | 57 + .../test/CodeGen/RISCV/sink-and-fold-crash.mir | 39 + .../test/CodeGen/RISCV/spacemitx60-sched-copy.mir | 60 + .../test/CodeGen/RISCV/stack-inst-compress.mir | 346 +++ .../CodeGen/RISCV/stack-probing-frame-setup.mir | 198 ++ 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IN NO EVENT SHALL THE +CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE +SOFTWARE. + diff --git a/third_party/llvm/README.md b/third_party/llvm/README.md new file mode 100644 index 0000000..3395260 --- /dev/null +++ b/third_party/llvm/README.md @@ -0,0 +1,16 @@ +# LLVM RISC-V MIR Test Assets + +This directory contains unmodified LLVM test assets used to verify RCC MachineIR compatibility. + +- Upstream project: https://github.com/llvm/llvm-project +- Upstream revision: `2b40c303e79f64c5c7642032554eda026594d604` +- Upstream path: `llvm/test/CodeGen/RISCV` +- Vendored files: all 462 `.mir` files below `llvm/test/CodeGen/RISCV` +- License: Apache License v2.0 with LLVM Exceptions; see `LICENSE.TXT` +- Sorted path-list SHA-256: `5b4dce23ecdca0b1c66eb98e4fa1c9ab41d86ec72a04770f56a451364ead3b5f` +- Aggregate content SHA-256: `6fffb35c378e290a030e4dff07d5a3dbb3d0e16f81012925891872cb051299c9` + +The aggregate content digest is the SHA-256 of the sorted, relative-path `sha256sum` output for +all vendored `.mir` files. Test inputs, `RUN:` directives, and FileCheck assertions must remain +unchanged. RCC-specific classifications and acceptance results live under +`docs/compiler-architecture/` rather than in these upstream files. diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/combine.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/combine.mir new file mode 100644 index 0000000..0d12e83 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/combine.mir @@ -0,0 +1,138 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -run-pass=riscv-prelegalizer-combiner -mtriple riscv64 %s -o - | FileCheck %s --check-prefix=RV64 + +--- +name: nneg_zext +body: | + bb.0: + + ; RV64-LABEL: name: nneg_zext + ; RV64: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; RV64-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; RV64-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %2:_(s32) = G_TRUNC %0 + %3:_(s64) = nneg G_ZEXT %2 + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... + +--- +name: binop_left_to_zero_shl +body: | + bb.0: + ; RV64-LABEL: name: binop_left_to_zero_shl + ; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: $x10 = COPY [[C]](s64) + ; RV64-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_CONSTANT i64 0 + %1:_(s64) = COPY $x10 + %2:_(s64) = G_SHL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... + +--- +name: binop_left_to_zero_lshr +body: | + bb.0: + ; RV64-LABEL: name: binop_left_to_zero_lshr + ; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: $x10 = COPY [[C]](s64) + ; RV64-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_CONSTANT i64 0 + %1:_(s64) = COPY $x10 + %2:_(s64) = G_LSHR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... + +--- +name: binop_left_to_zero_ashr +body: | + bb.0: + ; RV64-LABEL: name: binop_left_to_zero_ashr + ; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: $x10 = COPY [[C]](s64) + ; RV64-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_CONSTANT i64 0 + %1:_(s64) = COPY $x10 + %2:_(s64) = G_ASHR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... + +--- +name: binop_left_to_zero_sdiv +body: | + bb.0: + ; RV64-LABEL: name: binop_left_to_zero_sdiv + ; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: $x10 = COPY [[C]](s64) + ; RV64-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_CONSTANT i64 0 + %1:_(s64) = COPY $x10 + %2:_(s64) = G_SDIV %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... + +--- +name: binop_left_to_zero_udiv +body: | + bb.0: + ; RV64-LABEL: name: binop_left_to_zero_udiv + ; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: $x10 = COPY [[C]](s64) + ; RV64-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_CONSTANT i64 0 + %1:_(s64) = COPY $x10 + %2:_(s64) = G_UDIV %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... + +--- +name: binop_left_to_zero_srem +body: | + bb.0: + ; RV64-LABEL: name: binop_left_to_zero_srem + ; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: $x10 = COPY [[C]](s64) + ; RV64-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_CONSTANT i64 0 + %1:_(s64) = COPY $x10 + %2:_(s64) = G_SREM %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... + +--- +name: binop_left_to_zero_urem +body: | + bb.0: + ; RV64-LABEL: name: binop_left_to_zero_urem + ; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: $x10 = COPY [[C]](s64) + ; RV64-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_CONSTANT i64 0 + %1:_(s64) = COPY $x10 + %2:_(s64) = G_UREM %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... + +--- +name: binop_left_to_zero_mul +body: | + bb.0: + ; RV64-LABEL: name: binop_left_to_zero_mul + ; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: $x10 = COPY [[C]](s64) + ; RV64-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_CONSTANT i64 0 + %1:_(s64) = COPY $x10 + %2:_(s64) = G_MUL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir new file mode 100644 index 0000000..e21be2a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir @@ -0,0 +1,572 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s + +--- +name: add_i8_signext +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: add_i8_signext + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 24 + ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[SLLI]], 24 + ; RV32I-NEXT: $x10 = COPY [[SRAI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ADD %0, %1 + %3:gprb(s32) = G_CONSTANT i32 24 + %4:gprb(s32) = G_SHL %2, %3(s32) + %5:gprb(s32) = G_ASHR %4, %3(s32) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: add_i8_zeroext +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: add_i8_zeroext + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[ADD]], 255 + ; RV32I-NEXT: $x10 = COPY [[ANDI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ADD %0, %1 + %3:gprb(s32) = G_CONSTANT i32 255 + %4:gprb(s32) = G_AND %2, %3 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: add_i16_signext +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: add_i16_signext + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 16 + ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[SLLI]], 16 + ; RV32I-NEXT: $x10 = COPY [[SRAI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ADD %0, %1 + %3:gprb(s32) = G_CONSTANT i32 16 + %4:gprb(s32) = G_SHL %2, %3(s32) + %5:gprb(s32) = G_ASHR %4, %3(s32) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: add_i16_zeroext +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: add_i16_zeroext + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 16 + ; RV32I-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[SLLI]], 16 + ; RV32I-NEXT: $x10 = COPY [[SRLI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ADD %0, %1 + %3:gprb(s32) = G_CONSTANT i32 65535 + %4:gprb(s32) = G_AND %2, %3 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: add_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: add_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[ADD]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ADD %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: addi_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: addi_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 1234 + ; RV32I-NEXT: $x10 = COPY [[ADDI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 1234 + %2:gprb(s32) = G_ADD %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: sub_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: sub_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SUB]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_SUB %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: subi_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: subi_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1234 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[ADDI]] + ; RV32I-NEXT: $x10 = COPY [[SUB]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 -1234 + %2:gprb(s32) = G_SUB %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: sll_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: sll_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SLL]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_SHL %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: slli_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: slli_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 31 + ; RV32I-NEXT: $x10 = COPY [[SLLI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 31 + %2:gprb(s32) = G_SHL %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: sra_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: sra_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SRA:%[0-9]+]]:gpr = SRA [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SRA]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ASHR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: srai_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: srai_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[COPY]], 31 + ; RV32I-NEXT: $x10 = COPY [[SRAI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 31 + %2:gprb(s32) = G_ASHR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: srl_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: srl_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SRL]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_LSHR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: srli_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: srli_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 31 + ; RV32I-NEXT: $x10 = COPY [[SRLI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 31 + %2:gprb(s32) = G_LSHR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: and_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: and_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[AND]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_AND %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: andi_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: andi_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1234 + ; RV32I-NEXT: $x10 = COPY [[ANDI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 1234 + %2:gprb(s32) = G_AND %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: or_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: or_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[OR:%[0-9]+]]:gpr = OR [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[OR]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_OR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: ori_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: ori_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ORI:%[0-9]+]]:gpr = ORI [[COPY]], 1234 + ; RV32I-NEXT: $x10 = COPY [[ORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 1234 + %2:gprb(s32) = G_OR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: xor_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: xor_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[XOR]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_XOR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: xori_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: xori_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY]], 1234 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 1234 + %2:gprb(s32) = G_XOR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: add_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12, $x13 + + ; RV32I-LABEL: name: add_i64 + ; RV32I: liveins: $x10, $x11, $x12, $x13 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13 + ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY2]] + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADD]], [[COPY2]] + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY3]] + ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1 + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD1]], [[ANDI]] + ; RV32I-NEXT: $x10 = COPY [[ADD]] + ; RV32I-NEXT: $x11 = COPY [[ADD2]] + ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = COPY $x12 + %3:gprb(s32) = COPY $x13 + %4:gprb(s32) = G_ADD %0, %2 + %5:gprb(s32) = G_ICMP intpred(ult), %4(s32), %2 + %6:gprb(s32) = G_ADD %1, %3 + %7:gprb(s32) = G_CONSTANT i32 1 + %8:gprb(s32) = G_AND %5, %7 + %9:gprb(s32) = G_ADD %6, %8 + $x10 = COPY %4(s32) + $x11 = COPY %9(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sub_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12, $x13 + + ; RV32I-LABEL: name: sub_i64 + ; RV32I: liveins: $x10, $x11, $x12, $x13 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY2]] + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY2]] + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:gpr = SUB [[COPY1]], [[COPY3]] + ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1 + ; RV32I-NEXT: [[SUB2:%[0-9]+]]:gpr = SUB [[SUB1]], [[ANDI]] + ; RV32I-NEXT: $x10 = COPY [[SUB]] + ; RV32I-NEXT: $x11 = COPY [[SUB2]] + ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = COPY $x12 + %3:gprb(s32) = COPY $x13 + %4:gprb(s32) = G_SUB %0, %2 + %5:gprb(s32) = G_ICMP intpred(ult), %0(s32), %2 + %6:gprb(s32) = G_SUB %1, %3 + %7:gprb(s32) = G_CONSTANT i32 1 + %8:gprb(s32) = G_AND %5, %7 + %9:gprb(s32) = G_SUB %6, %8 + $x10 = COPY %4(s32) + $x11 = COPY %9(s32) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir new file mode 100644 index 0000000..90d92b6 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir @@ -0,0 +1,603 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV64I %s + +--- +name: sll_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: sll_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[SLLW:%[0-9]+]]:gpr = SLLW [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SLLW]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SLLW %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: slli_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: slli_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 31 + ; RV64I-NEXT: $x10 = COPY [[SLLI]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 31 + %2:gprb(s64) = G_SHL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sra_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: sra_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[SRAW:%[0-9]+]]:gpr = SRAW [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SRAW]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SRAW %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: srai_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: srai_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[SRAIW:%[0-9]+]]:gpr = SRAIW [[COPY]], 31 + ; RV64I-NEXT: $x10 = COPY [[SRAIW]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 31 + %2:gprb(s64) = G_SEXT_INREG %0, 32 + %3:gprb(s64) = G_ASHR %2, %1(s64) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: srl_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: srl_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[SRLW:%[0-9]+]]:gpr = SRLW [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SRLW]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SRLW %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: srli_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: srli_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[SRLIW:%[0-9]+]]:gpr = SRLIW [[COPY]], 31 + ; RV64I-NEXT: $x10 = COPY [[SRLIW]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 31 + %2:gprb(s64) = G_CONSTANT i64 4294967295 + %3:gprb(s64) = G_AND %0, %2 + %4:gprb(s64) = G_LSHR %3, %1(s64) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: add_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: add_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[ADD]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ADD %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: addi_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: addi_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 1234 + ; RV64I-NEXT: $x10 = COPY [[ADDI]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 1234 + %2:gprb(s64) = G_ADD %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sub_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: sub_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SUB]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SUB %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: subi_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: subi_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1234 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[ADDI]] + ; RV64I-NEXT: $x10 = COPY [[SUB]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 -1234 + %2:gprb(s64) = G_SUB %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sll_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: sll_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SLL]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SHL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: slli_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: slli_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 63 + ; RV64I-NEXT: $x10 = COPY [[SLLI]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 63 + %2:gprb(s64) = G_SHL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sra_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: sra_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[SRA:%[0-9]+]]:gpr = SRA [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SRA]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ASHR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: srai_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: srai_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[COPY]], 63 + ; RV64I-NEXT: $x10 = COPY [[SRAI]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 63 + %2:gprb(s64) = G_ASHR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: lshr_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: lshr_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SRL]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_LSHR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: srli_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: srli_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 63 + ; RV64I-NEXT: $x10 = COPY [[SRLI]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 63 + %2:gprb(s64) = G_LSHR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: and_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: and_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[AND]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_AND %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: andi_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: andi_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1234 + ; RV64I-NEXT: $x10 = COPY [[ANDI]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 1234 + %2:gprb(s64) = G_AND %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: or_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: or_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[OR:%[0-9]+]]:gpr = OR [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[OR]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_OR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: ori_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: ori_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[ORI:%[0-9]+]]:gpr = ORI [[COPY]], 1234 + ; RV64I-NEXT: $x10 = COPY [[ORI]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 1234 + %2:gprb(s64) = G_OR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: xor_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: xor_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[XOR]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_XOR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: xori_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: xori_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY]], 1234 + ; RV64I-NEXT: $x10 = COPY [[XORI]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 1234 + %2:gprb(s64) = G_XOR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: add_i128 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12, $x13 + + ; RV64I-LABEL: name: add_i128 + ; RV64I: liveins: $x10, $x11, $x12, $x13 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13 + ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY2]] + ; RV64I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADD]], [[COPY2]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY3]] + ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1 + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD1]], [[ANDI]] + ; RV64I-NEXT: $x10 = COPY [[ADD]] + ; RV64I-NEXT: $x11 = COPY [[ADD2]] + ; RV64I-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = COPY $x12 + %3:gprb(s64) = COPY $x13 + %4:gprb(s64) = G_ADD %0, %2 + %5:gprb(s64) = G_ICMP intpred(ult), %4(s64), %2 + %6:gprb(s64) = G_ADD %1, %3 + %7:gprb(s64) = G_CONSTANT i64 1 + %8:gprb(s64) = G_AND %5, %7 + %9:gprb(s64) = G_ADD %6, %8 + $x10 = COPY %4(s64) + $x11 = COPY %9(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sub_i128 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12, $x13 + + ; RV64I-LABEL: name: sub_i128 + ; RV64I: liveins: $x10, $x11, $x12, $x13 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY2]] + ; RV64I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY2]] + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:gpr = SUB [[COPY1]], [[COPY3]] + ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1 + ; RV64I-NEXT: [[SUB2:%[0-9]+]]:gpr = SUB [[SUB1]], [[ANDI]] + ; RV64I-NEXT: $x10 = COPY [[SUB]] + ; RV64I-NEXT: $x11 = COPY [[SUB2]] + ; RV64I-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = COPY $x12 + %3:gprb(s64) = COPY $x13 + %4:gprb(s64) = G_SUB %0, %2 + %5:gprb(s64) = G_ICMP intpred(ult), %0(s64), %2 + %6:gprb(s64) = G_SUB %1, %3 + %7:gprb(s64) = G_CONSTANT i64 1 + %8:gprb(s64) = G_AND %5, %7 + %9:gprb(s64) = G_SUB %6, %8 + $x10 = COPY %4(s64) + $x11 = COPY %9(s64) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir new file mode 100644 index 0000000..868bc2c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir @@ -0,0 +1,188 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s + +--- +name: mul_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: mul_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[MUL]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_MUL %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: sdiv_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[DIV:%[0-9]+]]:gpr = DIV [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[DIV]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_SDIV %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: srem_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: srem_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[REM:%[0-9]+]]:gpr = REM [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[REM]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_SREM %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: smulh_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: smulh_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[MULH:%[0-9]+]]:gpr = MULH [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[MULH]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_SMULH %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: udiv_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: udiv_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[DIVU:%[0-9]+]]:gpr = DIVU [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[DIVU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_UDIV %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: urem_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: urem_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[REMU:%[0-9]+]]:gpr = REMU [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[REMU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_UREM %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: mul_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12, $x13 + + ; RV32I-LABEL: name: mul_i64 + ; RV32I: liveins: $x10, $x11, $x12, $x13 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY2]] + ; RV32I-NEXT: [[MUL1:%[0-9]+]]:gpr = MUL [[COPY1]], [[COPY2]] + ; RV32I-NEXT: [[MUL2:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY3]] + ; RV32I-NEXT: [[MULHU:%[0-9]+]]:gpr = MULHU [[COPY]], [[COPY2]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[MUL1]], [[MUL2]] + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[MULHU]] + ; RV32I-NEXT: $x10 = COPY [[MUL]] + ; RV32I-NEXT: $x11 = COPY [[ADD1]] + ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = COPY $x12 + %3:gprb(s32) = COPY $x13 + %4:gprb(s32) = G_MUL %0, %2 + %5:gprb(s32) = G_MUL %1, %2 + %6:gprb(s32) = G_MUL %0, %3 + %7:gprb(s32) = G_UMULH %0, %2 + %8:gprb(s32) = G_ADD %5, %6 + %9:gprb(s32) = G_ADD %8, %7 + $x10 = COPY %4(s32) + $x11 = COPY %9(s32) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir new file mode 100644 index 0000000..18b2fca --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir @@ -0,0 +1,260 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV64I %s + +--- +name: sdiv_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: sdiv_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[DIVW:%[0-9]+]]:gpr = DIVW [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[DIVW]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_DIVW %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: udiv_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: udiv_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[DIVUW:%[0-9]+]]:gpr = DIVUW [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[DIVUW]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_DIVUW %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: urem_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: urem_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[REMUW:%[0-9]+]]:gpr = REMUW [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[REMUW]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_REMUW %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: mul_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[MUL]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_MUL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: sdiv_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[DIV:%[0-9]+]]:gpr = DIV [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[DIV]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SDIV %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: srem_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: srem_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[REM:%[0-9]+]]:gpr = REM [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[REM]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SREM %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: smulh_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: smulh_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[MULH:%[0-9]+]]:gpr = MULH [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[MULH]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SMULH %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: udiv_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: udiv_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[DIVU:%[0-9]+]]:gpr = DIVU [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[DIVU]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_UDIV %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: urem_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: urem_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[REMU:%[0-9]+]]:gpr = REMU [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[REMU]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_UREM %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i128 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12, $x13 + + ; RV64I-LABEL: name: mul_i128 + ; RV64I: liveins: $x10, $x11, $x12, $x13 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY2]] + ; RV64I-NEXT: [[MUL1:%[0-9]+]]:gpr = MUL [[COPY1]], [[COPY2]] + ; RV64I-NEXT: [[MUL2:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY3]] + ; RV64I-NEXT: [[MULHU:%[0-9]+]]:gpr = MULHU [[COPY]], [[COPY2]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[MUL1]], [[MUL2]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[MULHU]] + ; RV64I-NEXT: $x10 = COPY [[MUL]] + ; RV64I-NEXT: $x11 = COPY [[ADD1]] + ; RV64I-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = COPY $x12 + %3:gprb(s64) = COPY $x13 + %4:gprb(s64) = G_MUL %0, %2 + %5:gprb(s64) = G_MUL %1, %2 + %6:gprb(s64) = G_MUL %0, %3 + %7:gprb(s64) = G_UMULH %0, %2 + %8:gprb(s64) = G_ADD %5, %6 + %9:gprb(s64) = G_ADD %8, %7 + $x10 = COPY %4(s64) + $x11 = COPY %9(s64) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv32.mir new file mode 100644 index 0000000..e2d3bff --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv32.mir @@ -0,0 +1,119 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+a,+zacas,+zabha -run-pass=instruction-select %s -o - \ +# RUN: | FileCheck %s --check-prefixes=RV32IA-ZABHA + +--- +name: cmpxchg_i8 +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_i8 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV32IA-ZABHA-NEXT: [[AMOCAS_B:%[0-9]+]]:gpr = AMOCAS_B [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s8)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_B]] + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + %0:gpr(p0) = COPY $x10 + %1:gpr(s32) = G_CONSTANT i32 0 + %2:gpr(s32) = G_CONSTANT i32 1 + %3:gpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s8)) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_i16 +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_i16 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV32IA-ZABHA-NEXT: [[AMOCAS_H:%[0-9]+]]:gpr = AMOCAS_H [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s16)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_H]] + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + %0:gpr(p0) = COPY $x10 + %1:gpr(s32) = G_CONSTANT i32 0 + %2:gpr(s32) = G_CONSTANT i32 1 + %3:gpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s16)) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_i32 +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_i32 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV32IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s32)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_W]] + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + %0:gpr(p0) = COPY $x10 + %1:gpr(s32) = G_CONSTANT i32 0 + %2:gpr(s32) = G_CONSTANT i32 1 + %3:gpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s32)) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_with_success_i32 +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_with_success_i32 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV32IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s32)) + ; RV32IA-ZABHA-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[AMOCAS_W]], 1 + ; RV32IA-ZABHA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_W]] + ; RV32IA-ZABHA-NEXT: $x11 = COPY [[SLTIU]] + ; RV32IA-ZABHA-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV32IA-ZABHA-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-ZABHA-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[COPY2]] + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 0 + %2:gprb(s32) = G_CONSTANT i32 1 + %3:gprb(s32) = G_ATOMIC_CMPXCHG %0(p0), %1, %2 :: (load store monotonic (s32)) + %4:gprb(s32) = G_ICMP intpred(eq), %3(s32), %1 + %5:gprb(s32) = COPY %3(s32) + ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + $x10 = COPY %5(s32) + $x11 = COPY %4(s32) + PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + %6:gprb(s32) = COPY $x10 + $x10 = COPY %6(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv64.mir new file mode 100644 index 0000000..ab537ea --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv64.mir @@ -0,0 +1,144 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+a,+zacas,+zabha -run-pass=instruction-select %s -o - \ +# RUN: | FileCheck %s --check-prefixes=RV64IA-ZABHA + +--- +name: cmpxchg_i8 +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $x10 + + ; RV64IA-ZABHA-LABEL: name: cmpxchg_i8 + ; RV64IA-ZABHA: liveins: $x10 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV64IA-ZABHA-NEXT: [[AMOCAS_B:%[0-9]+]]:gpr = AMOCAS_B [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s8)) + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_B]] + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + %0:gpr(p0) = COPY $x10 + %1:gpr(s64) = G_CONSTANT i64 0 + %2:gpr(s64) = G_CONSTANT i64 1 + %3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s8)) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_i16 +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $x10 + + ; RV64IA-ZABHA-LABEL: name: cmpxchg_i16 + ; RV64IA-ZABHA: liveins: $x10 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV64IA-ZABHA-NEXT: [[AMOCAS_H:%[0-9]+]]:gpr = AMOCAS_H [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s16)) + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_H]] + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + %0:gpr(p0) = COPY $x10 + %1:gpr(s64) = G_CONSTANT i64 0 + %2:gpr(s64) = G_CONSTANT i64 1 + %3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s16)) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_i32 +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $x10 + + ; RV64IA-ZABHA-LABEL: name: cmpxchg_i32 + ; RV64IA-ZABHA: liveins: $x10 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV64IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s32)) + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_W]] + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + %0:gpr(p0) = COPY $x10 + %1:gpr(s64) = G_CONSTANT i64 0 + %2:gpr(s64) = G_CONSTANT i64 1 + %3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s32)) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_i64 +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $x10 + + ; RV64IA-ZABHA-LABEL: name: cmpxchg_i64 + ; RV64IA-ZABHA: liveins: $x10 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV64IA-ZABHA-NEXT: [[AMOCAS_D_RV64_:%[0-9]+]]:gpr = AMOCAS_D_RV64 [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s64)) + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_D_RV64_]] + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + %0:gpr(p0) = COPY $x10 + %1:gpr(s64) = G_CONSTANT i64 0 + %2:gpr(s64) = G_CONSTANT i64 1 + %3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s64)) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_with_success_i64 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10 + + ; RV64IA-ZABHA-LABEL: name: cmpxchg_with_success_i64 + ; RV64IA-ZABHA: liveins: $x10 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV64IA-ZABHA-NEXT: [[AMOCAS_D_RV64_:%[0-9]+]]:gpr = AMOCAS_D_RV64 [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s64)) + ; RV64IA-ZABHA-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[AMOCAS_D_RV64_]], 1 + ; RV64IA-ZABHA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_D_RV64_]] + ; RV64IA-ZABHA-NEXT: $x11 = COPY [[SLTIU]] + ; RV64IA-ZABHA-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV64IA-ZABHA-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV64IA-ZABHA-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[COPY2]] + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 0 + %2:gprb(s64) = G_CONSTANT i64 1 + %3:gprb(s64) = G_ATOMIC_CMPXCHG %0(p0), %1, %2 :: (load store monotonic (s64)) + %4:gprb(s64) = G_ICMP intpred(eq), %3(s64), %1 + %5:gprb(s64) = COPY %3(s64) + %6:gprb(s64) = COPY %4(s64) + ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + $x10 = COPY %5(s64) + $x11 = COPY %6(s64) + PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + %7:gprb(s64) = COPY $x10 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir new file mode 100644 index 0000000..e547972 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir @@ -0,0 +1,153 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+a,+zabha -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: atomicrmw_add_i8_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_add_i8_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY1]], [[COPY]] :: (load store monotonic (s8)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_B]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ATOMICRMW_ADD %0(p0), %1 :: (load store monotonic (s8)) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_add_i16_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_add_i16_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[COPY1]], [[COPY]] :: (load store monotonic (s16)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ATOMICRMW_ADD %0(p0), %1 :: (load store monotonic (s16)) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_add_i32_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_add_i32_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[AMOADD_W:%[0-9]+]]:gpr = AMOADD_W [[COPY1]], [[COPY]] :: (load store monotonic (s32)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_W]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ATOMICRMW_ADD %0(p0), %1 :: (load store monotonic (s32)) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i8_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_sub_i8_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] + ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[SUB]], [[COPY]] :: (load store monotonic (s8)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_B]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 0 + %3:gprb(s32) = G_SUB %2(s32), %1(s32) + %4:gprb(s32) = G_ATOMICRMW_ADD %0(p0), %3 :: (load store monotonic (s8)) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i16_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_sub_i16_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] + ; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[SUB]], [[COPY]] :: (load store monotonic (s16)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 0 + %3:gprb(s32) = G_SUB %2(s32), %1(s32) + %4:gprb(s32) = G_ATOMICRMW_ADD %0(p0), %3 :: (load store monotonic (s16)) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i32_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_sub_i32_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] + ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[SUB]], [[COPY]] :: (load store monotonic (s8)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_B]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 0 + %3:gprb(s32) = G_SUB %2(s32), %1(s32) + %4:gprb(s32) = G_ATOMICRMW_ADD %0(p0), %3 :: (load store monotonic (s8)) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir new file mode 100644 index 0000000..f34826c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir @@ -0,0 +1,203 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+a,+zabha -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: atomicrmw_add_i8_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_add_i8_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY1]], [[COPY]] :: (load store monotonic (s8)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_B]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ATOMICRMW_ADD %0(p0), %1 :: (load store monotonic (s8)) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_add_i16_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_add_i16_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[COPY1]], [[COPY]] :: (load store monotonic (s16)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ATOMICRMW_ADD %0(p0), %1 :: (load store monotonic (s16)) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_add_i32_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_add_i32_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[AMOADD_W:%[0-9]+]]:gpr = AMOADD_W [[COPY1]], [[COPY]] :: (load store monotonic (s32)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_W]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ATOMICRMW_ADD %0(p0), %1 :: (load store monotonic (s32)) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_add_i64_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_add_i64_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[AMOADD_D:%[0-9]+]]:gpr = AMOADD_D [[COPY1]], [[COPY]] :: (load store monotonic (s64)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ATOMICRMW_ADD %0(p0), %1 :: (load store monotonic (s64)) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i8_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_sub_i8_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] + ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[SUB]], [[COPY]] :: (load store monotonic (s8)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_B]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 0 + %3:gprb(s64) = G_SUB %2(s64), %1(s64) + %4:gprb(s64) = G_ATOMICRMW_ADD %0(p0), %3 :: (load store monotonic (s8)) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i16_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_sub_i16_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] + ; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[SUB]], [[COPY]] :: (load store monotonic (s16)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 0 + %3:gprb(s64) = G_SUB %2(s64), %1(s64) + %4:gprb(s64) = G_ATOMICRMW_ADD %0(p0), %3 :: (load store monotonic (s16)) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i32_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_sub_i32_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] + ; CHECK-NEXT: [[AMOADD_W:%[0-9]+]]:gpr = AMOADD_W [[SUB]], [[COPY]] :: (load store monotonic (s32)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_W]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 0 + %3:gprb(s64) = G_SUB %2(s64), %1(s64) + %4:gprb(s64) = G_ATOMICRMW_ADD %0(p0), %3 :: (load store monotonic (s32)) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i64_monotonic +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: atomicrmw_sub_i64_monotonic + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]] + ; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[SUB]], [[COPY]] :: (load store monotonic (s8)) + ; CHECK-NEXT: $x10 = COPY [[AMOADD_B]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 0 + %3:gprb(s64) = G_SUB %2(s64), %1(s64) + %4:gprb(s64) = G_ATOMICRMW_ADD %0(p0), %3 :: (load store monotonic (s8)) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv32.mir new file mode 100644 index 0000000..13c4d49 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv32.mir @@ -0,0 +1,188 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s + +--- +name: brcond +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + ; RV32I-LABEL: name: brcond + ; RV32I: bb.0: + ; RV32I-NEXT: liveins: $x10, $x11, $x12 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; RV32I-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: BEQ [[LW]], [[COPY]], %bb.14 + ; RV32I-NEXT: PseudoBR %bb.1 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.1: + ; RV32I-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: BNE [[LW1]], [[COPY]], %bb.14 + ; RV32I-NEXT: PseudoBR %bb.2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.2: + ; RV32I-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: BLT [[LW2]], [[COPY]], %bb.14 + ; RV32I-NEXT: PseudoBR %bb.3 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.3: + ; RV32I-NEXT: [[LW3:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: BGE [[LW3]], [[COPY]], %bb.14 + ; RV32I-NEXT: PseudoBR %bb.4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.4: + ; RV32I-NEXT: [[LW4:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: BLTU [[LW4]], [[COPY]], %bb.14 + ; RV32I-NEXT: PseudoBR %bb.5 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.5: + ; RV32I-NEXT: [[LW5:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: BGEU [[LW5]], [[COPY]], %bb.14 + ; RV32I-NEXT: PseudoBR %bb.6 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.6: + ; RV32I-NEXT: [[LW6:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: BLT [[COPY]], [[LW6]], %bb.14 + ; RV32I-NEXT: PseudoBR %bb.7 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.7: + ; RV32I-NEXT: [[LW7:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: BGE [[COPY]], [[LW7]], %bb.14 + ; RV32I-NEXT: PseudoBR %bb.8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.8: + ; RV32I-NEXT: [[LW8:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: BLTU [[COPY]], [[LW8]], %bb.14 + ; RV32I-NEXT: PseudoBR %bb.9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.9: + ; RV32I-NEXT: [[LW9:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: BGEU [[COPY]], [[LW9]], %bb.14 + ; RV32I-NEXT: PseudoBR %bb.10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.10: + ; RV32I-NEXT: [[LW10:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1 + ; RV32I-NEXT: BNE [[ANDI]], $x0, %bb.14 + ; RV32I-NEXT: PseudoBR %bb.11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.11: + ; RV32I-NEXT: successors: %bb.14(0x50000000), %bb.12(0x30000000) + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[LW11:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: BGE [[LW11]], $x0, %bb.14 + ; RV32I-NEXT: PseudoBR %bb.12 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.12: + ; RV32I-NEXT: successors: %bb.14(0x30000000), %bb.13(0x50000000) + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[LW12:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: BGE $x0, [[LW12]], %bb.14 + ; RV32I-NEXT: PseudoBR %bb.13 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.13: + ; RV32I-NEXT: [[LW13:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32)) + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.14: + ; RV32I-NEXT: PseudoRET + bb.1: + liveins: $x10, $x11, $x12 + + %0:gprb(s32) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %3:gprb(s32) = COPY $x12 + %26:gprb(s32) = G_CONSTANT i32 -1 + %29:gprb(s32) = G_CONSTANT i32 1 + %4:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %56:gprb(s32) = G_ICMP intpred(eq), %4(s32), %0 + G_BRCOND %56(s32), %bb.15 + G_BR %bb.2 + + bb.2: + %6:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %54:gprb(s32) = G_ICMP intpred(ne), %6(s32), %0 + G_BRCOND %54(s32), %bb.15 + G_BR %bb.3 + + bb.3: + %8:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %52:gprb(s32) = G_ICMP intpred(slt), %8(s32), %0 + G_BRCOND %52(s32), %bb.15 + G_BR %bb.4 + + bb.4: + %10:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %50:gprb(s32) = G_ICMP intpred(sge), %10(s32), %0 + G_BRCOND %50(s32), %bb.15 + G_BR %bb.5 + + bb.5: + %12:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %48:gprb(s32) = G_ICMP intpred(ult), %12(s32), %0 + G_BRCOND %48(s32), %bb.15 + G_BR %bb.6 + + bb.6: + %14:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %46:gprb(s32) = G_ICMP intpred(uge), %14(s32), %0 + G_BRCOND %46(s32), %bb.15 + G_BR %bb.7 + + bb.7: + %16:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %44:gprb(s32) = G_ICMP intpred(sgt), %16(s32), %0 + G_BRCOND %44(s32), %bb.15 + G_BR %bb.8 + + bb.8: + %18:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %42:gprb(s32) = G_ICMP intpred(sle), %18(s32), %0 + G_BRCOND %42(s32), %bb.15 + G_BR %bb.9 + + bb.9: + %20:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %40:gprb(s32) = G_ICMP intpred(ugt), %20(s32), %0 + G_BRCOND %40(s32), %bb.15 + G_BR %bb.10 + + bb.10: + %22:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %38:gprb(s32) = G_ICMP intpred(ule), %22(s32), %0 + G_BRCOND %38(s32), %bb.15 + G_BR %bb.11 + + bb.11: + %24:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %57:gprb(s32) = G_CONSTANT i32 1 + %36:gprb(s32) = G_AND %3, %57 + G_BRCOND %36(s32), %bb.15 + G_BR %bb.12 + + bb.12: + successors: %bb.15(0x50000000), %bb.13(0x30000000) + + %25:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %35:gprb(s32) = G_ICMP intpred(sgt), %25(s32), %26 + G_BRCOND %35(s32), %bb.15 + G_BR %bb.13 + + bb.13: + successors: %bb.15(0x30000000), %bb.14(0x50000000) + + %28:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + %33:gprb(s32) = G_ICMP intpred(slt), %28(s32), %29 + G_BRCOND %33(s32), %bb.15 + G_BR %bb.14 + + bb.14: + %31:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32)) + + bb.15: + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv64.mir new file mode 100644 index 0000000..de13516 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv64.mir @@ -0,0 +1,188 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV64I %s + +--- +name: brcond +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + ; RV64I-LABEL: name: brcond + ; RV64I: bb.0: + ; RV64I-NEXT: liveins: $x10, $x11, $x12 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; RV64I-NEXT: [[LD:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: BEQ [[LD]], [[COPY]], %bb.14 + ; RV64I-NEXT: PseudoBR %bb.1 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.1: + ; RV64I-NEXT: [[LD1:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: BNE [[LD1]], [[COPY]], %bb.14 + ; RV64I-NEXT: PseudoBR %bb.2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.2: + ; RV64I-NEXT: [[LD2:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: BLT [[LD2]], [[COPY]], %bb.14 + ; RV64I-NEXT: PseudoBR %bb.3 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.3: + ; RV64I-NEXT: [[LD3:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: BGE [[LD3]], [[COPY]], %bb.14 + ; RV64I-NEXT: PseudoBR %bb.4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.4: + ; RV64I-NEXT: [[LD4:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: BLTU [[LD4]], [[COPY]], %bb.14 + ; RV64I-NEXT: PseudoBR %bb.5 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.5: + ; RV64I-NEXT: [[LD5:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: BGEU [[LD5]], [[COPY]], %bb.14 + ; RV64I-NEXT: PseudoBR %bb.6 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.6: + ; RV64I-NEXT: [[LD6:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: BLT [[COPY]], [[LD6]], %bb.14 + ; RV64I-NEXT: PseudoBR %bb.7 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.7: + ; RV64I-NEXT: [[LD7:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: BGE [[COPY]], [[LD7]], %bb.14 + ; RV64I-NEXT: PseudoBR %bb.8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.8: + ; RV64I-NEXT: [[LD8:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: BLTU [[COPY]], [[LD8]], %bb.14 + ; RV64I-NEXT: PseudoBR %bb.9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.9: + ; RV64I-NEXT: [[LD9:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: BGEU [[COPY]], [[LD9]], %bb.14 + ; RV64I-NEXT: PseudoBR %bb.10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.10: + ; RV64I-NEXT: [[LD10:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1 + ; RV64I-NEXT: BNE [[ANDI]], $x0, %bb.14 + ; RV64I-NEXT: PseudoBR %bb.11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.11: + ; RV64I-NEXT: successors: %bb.14(0x50000000), %bb.12(0x30000000) + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[LD11:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: BGE [[LD11]], $x0, %bb.14 + ; RV64I-NEXT: PseudoBR %bb.12 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.12: + ; RV64I-NEXT: successors: %bb.14(0x30000000), %bb.13(0x50000000) + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[LD12:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: BGE $x0, [[LD12]], %bb.14 + ; RV64I-NEXT: PseudoBR %bb.13 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.13: + ; RV64I-NEXT: [[LD13:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64)) + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.14: + ; RV64I-NEXT: PseudoRET + bb.1: + liveins: $x10, $x11, $x12 + + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %3:gprb(s64) = COPY $x12 + %26:gprb(s64) = G_CONSTANT i64 -1 + %29:gprb(s64) = G_CONSTANT i64 1 + %4:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %56:gprb(s64) = G_ICMP intpred(eq), %4(s64), %0 + G_BRCOND %56(s64), %bb.15 + G_BR %bb.2 + + bb.2: + %6:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %54:gprb(s64) = G_ICMP intpred(ne), %6(s64), %0 + G_BRCOND %54(s64), %bb.15 + G_BR %bb.3 + + bb.3: + %8:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %52:gprb(s64) = G_ICMP intpred(slt), %8(s64), %0 + G_BRCOND %52(s64), %bb.15 + G_BR %bb.4 + + bb.4: + %10:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %50:gprb(s64) = G_ICMP intpred(sge), %10(s64), %0 + G_BRCOND %50(s64), %bb.15 + G_BR %bb.5 + + bb.5: + %12:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %48:gprb(s64) = G_ICMP intpred(ult), %12(s64), %0 + G_BRCOND %48(s64), %bb.15 + G_BR %bb.6 + + bb.6: + %14:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %46:gprb(s64) = G_ICMP intpred(uge), %14(s64), %0 + G_BRCOND %46(s64), %bb.15 + G_BR %bb.7 + + bb.7: + %16:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %44:gprb(s64) = G_ICMP intpred(sgt), %16(s64), %0 + G_BRCOND %44(s64), %bb.15 + G_BR %bb.8 + + bb.8: + %18:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %42:gprb(s64) = G_ICMP intpred(sle), %18(s64), %0 + G_BRCOND %42(s64), %bb.15 + G_BR %bb.9 + + bb.9: + %20:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %40:gprb(s64) = G_ICMP intpred(ugt), %20(s64), %0 + G_BRCOND %40(s64), %bb.15 + G_BR %bb.10 + + bb.10: + %22:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %38:gprb(s64) = G_ICMP intpred(ule), %22(s64), %0 + G_BRCOND %38(s64), %bb.15 + G_BR %bb.11 + + bb.11: + %24:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %57:gprb(s64) = G_CONSTANT i64 1 + %36:gprb(s64) = G_AND %3, %57 + G_BRCOND %36(s64), %bb.15 + G_BR %bb.12 + + bb.12: + successors: %bb.15(0x50000000), %bb.13(0x30000000) + + %25:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %35:gprb(s64) = G_ICMP intpred(sgt), %25(s64), %26 + G_BRCOND %35(s64), %bb.15 + G_BR %bb.13 + + bb.13: + successors: %bb.15(0x30000000), %bb.14(0x50000000) + + %28:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + %33:gprb(s64) = G_ICMP intpred(slt), %28(s64), %29 + G_BRCOND %33(s64), %bb.15 + G_BR %bb.14 + + bb.14: + %31:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64)) + + bb.15: + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir new file mode 100644 index 0000000..b159ba6 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv32.mir @@ -0,0 +1,45 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s + +--- +name: indirectbr +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + ; RV32I-LABEL: name: indirectbr + ; RV32I: bb.0: + ; RV32I-NEXT: successors: %bb.1, %bb.2 + ; RV32I-NEXT: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprjalrnonx7 = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; RV32I-NEXT: PseudoBRIND [[COPY]], 0 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.1: + ; RV32I-NEXT: $x10 = COPY [[COPY1]] + ; RV32I-NEXT: PseudoRET implicit $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.2: + ; RV32I-NEXT: $x10 = COPY [[ADDI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + bb.1: + successors: %bb.2, %bb.3 + liveins: $x10 + + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 1 + %2:gprb(s32) = G_CONSTANT i32 0 + G_BRINDIRECT %0(p0) + + bb.2: + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + + bb.3: + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv64.mir new file mode 100644 index 0000000..27419b2 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brindirect-rv64.mir @@ -0,0 +1,45 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s + +--- +name: indirectbr +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + ; RV64I-LABEL: name: indirectbr + ; RV64I: bb.0: + ; RV64I-NEXT: successors: %bb.1, %bb.2 + ; RV64I-NEXT: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprjalrnonx7 = COPY $x10 + ; RV64I-NEXT: PseudoBRIND [[COPY]], 0 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.1: + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; RV64I-NEXT: $x10 = COPY [[COPY1]] + ; RV64I-NEXT: PseudoRET implicit $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.2: + ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV64I-NEXT: $x10 = COPY [[ADDI]] + ; RV64I-NEXT: PseudoRET implicit $x10 + bb.1: + successors: %bb.2, %bb.3 + liveins: $x10 + + %0:gprb(p0) = COPY $x10 + G_BRINDIRECT %0(p0) + + bb.2: + %4:gprb(s64) = G_CONSTANT i64 0 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + + bb.3: + %2:gprb(s64) = G_CONSTANT i64 1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir new file mode 100644 index 0000000..721721c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir @@ -0,0 +1,23 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: bswap_s32 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bswap_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[REV8_RV32_:%[0-9]+]]:gpr = REV8_RV32 [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[REV8_RV32_]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_BSWAP %0 + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir new file mode 100644 index 0000000..6cdfb76 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir @@ -0,0 +1,23 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: bswap_s64 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bswap_s64 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[REV8_RV64_:%[0-9]+]]:gpr = REV8_RV64 [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[REV8_RV64_]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_BSWAP %0 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant32.mir new file mode 100644 index 0000000..cb66c30 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant32.mir @@ -0,0 +1,126 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \ +# RUN: | FileCheck %s +--- +name: const_i32_INT_MIN +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i32_INT_MIN + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288 + ; CHECK-NEXT: $x10 = COPY [[LUI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = G_CONSTANT i32 -2147483648 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: const_i32_neg_2147483000 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i32_neg_2147483000 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 648 + ; CHECK-NEXT: $x10 = COPY [[ADDI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = G_CONSTANT i32 -2147483000 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: const_i32_INT_MAX +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i32_INT_MAX + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -1 + ; CHECK-NEXT: $x10 = COPY [[ADDI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = G_CONSTANT i32 2147483647 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: const_i32_2147483000 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i32_2147483000 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -648 + ; CHECK-NEXT: $x10 = COPY [[ADDI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = G_CONSTANT i32 2147483000 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: const_i32_256 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i32_256 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 256 + ; CHECK-NEXT: $x10 = COPY [[ADDI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = G_CONSTANT i32 256 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: const_i32_0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i32_0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = G_CONSTANT i32 0 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir new file mode 100644 index 0000000..0f00bd0 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir @@ -0,0 +1,211 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \ +# RUN: | FileCheck %s +--- +name: const_i64_INT_MIN +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i64_INT_MIN + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 63 + ; CHECK-NEXT: $x10 = COPY [[SLLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_CONSTANT i64 -9223372036854775808 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i64_neg_9223372036854775000 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i64_neg_9223372036854775000 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 63 + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[SLLI]], 808 + ; CHECK-NEXT: $x10 = COPY [[ADDI1]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_CONSTANT i64 -9223372036854775000 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i64_INT_MAX +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i64_INT_MAX + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[ADDI]], 1 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_CONSTANT i64 9223372036854775807 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i64_9223372036854775000 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i64_9223372036854775000 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1615 + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[ADDI]], 1 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_CONSTANT i64 9223372036854775000 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i64_256 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i64_256 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 256 + ; CHECK-NEXT: $x10 = COPY [[ADDI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_CONSTANT i64 256 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i64_0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i64_0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_CONSTANT i64 0 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i32_INT_MIN +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i32_INT_MIN + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288 + ; CHECK-NEXT: $x10 = COPY [[LUI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_CONSTANT i64 -2147483648 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i32_neg_2147483000 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i32_neg_2147483000 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 648 + ; CHECK-NEXT: $x10 = COPY [[ADDI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_CONSTANT i64 -2147483000 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i32_INT_MAX +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i32_INT_MAX + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288 + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], -1 + ; CHECK-NEXT: $x10 = COPY [[ADDIW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_CONSTANT i64 2147483647 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i32_2147483000 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: const_i32_2147483000 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288 + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], -648 + ; CHECK-NEXT: $x10 = COPY [[ADDIW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_CONSTANT i64 2147483000 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir new file mode 100644 index 0000000..a0ec98b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir @@ -0,0 +1,71 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s + +--- +name: virt_to_phys +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + + ; RV32I-LABEL: name: virt_to_phys + ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV32I-NEXT: $x10 = COPY [[ADDI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = G_CONSTANT i32 1 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: phys_to_phys +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: phys_to_phys + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: $x10 = COPY $x11 + ; RV32I-NEXT: PseudoRET implicit $x10 + $x10 = COPY $x11 + PseudoRET implicit $x10 + +... +--- +name: virt_to_virt +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + + ; RV32I-LABEL: name: virt_to_virt + ; RV32I: PseudoRET + %0:gprb(s32) = G_CONSTANT i32 1 + %1:gprb(s32) = COPY %0(s32) + PseudoRET + +... +--- +name: phys_to_virt +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: phys_to_virt + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: PseudoRET + %0:gprb(s32) = COPY $x10 + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir new file mode 100644 index 0000000..bb15aa5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir @@ -0,0 +1,71 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV64I %s + +--- +name: virt_to_phys +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + + ; RV64I-LABEL: name: virt_to_phys + ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; RV64I-NEXT: $x10 = COPY [[ADDI]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_CONSTANT i64 1 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: phys_to_phys +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: phys_to_phys + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: $x10 = COPY $x11 + ; RV64I-NEXT: PseudoRET implicit $x10 + $x10 = COPY $x11 + PseudoRET implicit $x10 + +... +--- +name: virt_to_virt +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + + ; RV64I-LABEL: name: virt_to_virt + ; RV64I: PseudoRET + %0:gprb(s64) = G_CONSTANT i64 1 + %1:gprb(s64) = COPY %0(s64) + PseudoRET + +... +--- +name: phys_to_virt +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: phys_to_virt + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: PseudoRET + %0:gprb(s64) = COPY $x10 + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv32.mir new file mode 100644 index 0000000..ff5740f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv32.mir @@ -0,0 +1,22 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s + +--- +name: ctlz_s32 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: ctlz_s32 + ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[CLZ:%[0-9]+]]:gpr = CLZ [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[CLZ]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CTLZ %0 + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir new file mode 100644 index 0000000..f6e04a9 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir @@ -0,0 +1,38 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV64I %s + +--- +name: ctlz_s32 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: ctlz_s32 + ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[CLZW:%[0-9]+]]:gpr = CLZW [[COPY]] + ; RV64I-NEXT: $x10 = COPY [[CLZW]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CLZW %0 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: ctlz_s64 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: ctlz_s64 + ; RV64I: [[CLZ:%[0-9]+]]:gpr = CLZ [[CLZ]] + ; RV64I-NEXT: $x10 = COPY [[CLZ]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CTLZ %1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv32.mir new file mode 100644 index 0000000..548a921 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv32.mir @@ -0,0 +1,22 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s + +--- +name: ctpop_s32 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: ctpop_s32 + ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[CPOP:%[0-9]+]]:gpr = CPOP [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[CPOP]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CTPOP %0 + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv64.mir new file mode 100644 index 0000000..f91f029 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv64.mir @@ -0,0 +1,22 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV64I %s + +--- +name: ctpop_s64 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: ctpop_s64 + ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[CPOP:%[0-9]+]]:gpr = CPOP [[COPY]] + ; RV64I-NEXT: $x10 = COPY [[CPOP]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CTPOP %0 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv32.mir new file mode 100644 index 0000000..f9ebd0b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv32.mir @@ -0,0 +1,22 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s + +--- +name: cttz_s32 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: cttz_s32 + ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[CTZ:%[0-9]+]]:gpr = CTZ [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[CTZ]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CTTZ %0 + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir new file mode 100644 index 0000000..17fb381 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir @@ -0,0 +1,38 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV64I %s + +--- +name: cttz_s32 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: cttz_s32 + ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[CTZW:%[0-9]+]]:gpr = CTZW [[COPY]] + ; RV64I-NEXT: $x10 = COPY [[CTZW]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CTZW %0 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: cttz_s64 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: cttz_s64 + ; RV64I: [[CTZ:%[0-9]+]]:gpr = CTZ [[CTZ]] + ; RV64I-NEXT: $x10 = COPY [[CTZ]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CTTZ %1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv32.mir new file mode 100644 index 0000000..6fdfd65 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv32.mir @@ -0,0 +1,355 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fcmp_oeq_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_oeq_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = nofpexcept FEQ_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FEQ_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(oeq), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ogt_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ogt_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLT_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(ogt), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oge_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_oge_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLE_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(oge), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_olt_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_olt_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = nofpexcept FLT_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FLT_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(olt), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ole_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ole_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = nofpexcept FLE_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FLE_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(ole), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_one_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_one_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[FLT_H1:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_H]], [[FLT_H1]] + ; CHECK-NEXT: $x10 = COPY [[OR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(one), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ord_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ord_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = FEQ_H [[COPY]], [[COPY]] + ; CHECK-NEXT: [[FEQ_H1:%[0-9]+]]:gpr = FEQ_H [[COPY1]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_H]], [[FEQ_H1]] + ; CHECK-NEXT: $x10 = COPY [[AND]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(ord), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ueq_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ueq_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[FLT_H1:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_H]], [[FLT_H1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[OR]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(ueq), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ugt_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ugt_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_H]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(ugt), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uge_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_uge_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_H]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(uge), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ult_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ult_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_H]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(ult), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ule_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ule_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_H]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(ule), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_une_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_une_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = FEQ_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FEQ_H]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(une), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uno_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_uno_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = FEQ_H [[COPY]], [[COPY]] + ; CHECK-NEXT: [[FEQ_H1:%[0-9]+]]:gpr = FEQ_H [[COPY1]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_H]], [[FEQ_H1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[AND]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s32) = G_FCMP floatpred(uno), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv64.mir new file mode 100644 index 0000000..827d3e5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv64.mir @@ -0,0 +1,355 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fcmp_oeq_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_oeq_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = nofpexcept FEQ_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FEQ_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(oeq), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ogt_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ogt_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLT_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(ogt), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oge_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_oge_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLE_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(oge), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_olt_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_olt_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = nofpexcept FLT_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FLT_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(olt), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ole_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ole_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = nofpexcept FLE_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FLE_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(ole), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_one_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_one_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[FLT_H1:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_H]], [[FLT_H1]] + ; CHECK-NEXT: $x10 = COPY [[OR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(one), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ord_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ord_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = FEQ_H [[COPY]], [[COPY]] + ; CHECK-NEXT: [[FEQ_H1:%[0-9]+]]:gpr = FEQ_H [[COPY1]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_H]], [[FEQ_H1]] + ; CHECK-NEXT: $x10 = COPY [[AND]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(ord), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ueq_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ueq_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[FLT_H1:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_H]], [[FLT_H1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[OR]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(ueq), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ugt_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ugt_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_H]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(ugt), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uge_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_uge_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_H]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(uge), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ult_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ult_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_H]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(ult), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ule_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ule_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_H]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(ule), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_une_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_une_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = FEQ_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FEQ_H]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(une), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uno_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_uno_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = FEQ_H [[COPY]], [[COPY]] + ; CHECK-NEXT: [[FEQ_H1:%[0-9]+]]:gpr = FEQ_H [[COPY1]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_H]], [[FEQ_H1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[AND]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %4:gprb(s64) = G_FCMP floatpred(uno), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-rv32.mir new file mode 100644 index 0000000..285a35f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-rv32.mir @@ -0,0 +1,706 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fcmp_oeq_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_oeq_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FEQ_S:%[0-9]+]]:gpr = nofpexcept FEQ_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FEQ_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(oeq), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ogt_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ogt_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLT_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(ogt), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oge_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_oge_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = FLE_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLE_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(oge), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_olt_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_olt_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = nofpexcept FLT_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FLT_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(olt), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ole_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ole_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = nofpexcept FLE_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FLE_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(ole), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_one_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_one_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[FLT_S1:%[0-9]+]]:gpr = FLT_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_S]], [[FLT_S1]] + ; CHECK-NEXT: $x10 = COPY [[OR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(one), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ord_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ord_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FEQ_S:%[0-9]+]]:gpr = FEQ_S [[COPY]], [[COPY]] + ; CHECK-NEXT: [[FEQ_S1:%[0-9]+]]:gpr = FEQ_S [[COPY1]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_S]], [[FEQ_S1]] + ; CHECK-NEXT: $x10 = COPY [[AND]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(ord), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ueq_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ueq_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[FLT_S1:%[0-9]+]]:gpr = FLT_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_S]], [[FLT_S1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[OR]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(ueq), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ugt_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ugt_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = FLE_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_S]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(ugt), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uge_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_uge_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_S]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(uge), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ult_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ult_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = FLE_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_S]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(ult), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ule_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ule_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_S]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(ule), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_une_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_une_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FEQ_S:%[0-9]+]]:gpr = FEQ_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FEQ_S]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(une), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uno_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_uno_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FEQ_S:%[0-9]+]]:gpr = FEQ_S [[COPY]], [[COPY]] + ; CHECK-NEXT: [[FEQ_S1:%[0-9]+]]:gpr = FEQ_S [[COPY1]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_S]], [[FEQ_S1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[AND]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s32) = G_FCMP floatpred(uno), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oeq_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_oeq_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FEQ_D:%[0-9]+]]:gpr = nofpexcept FEQ_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FEQ_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(oeq), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ogt_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ogt_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLT_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(ogt), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oge_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_oge_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLE_D:%[0-9]+]]:gpr = FLE_D [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLE_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(oge), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_olt_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_olt_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = nofpexcept FLT_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FLT_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(olt), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ole_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ole_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLE_D:%[0-9]+]]:gpr = nofpexcept FLE_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FLE_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(ole), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_one_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_one_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[FLT_D1:%[0-9]+]]:gpr = FLT_D [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_D]], [[FLT_D1]] + ; CHECK-NEXT: $x10 = COPY [[OR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(one), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ord_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ord_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FEQ_D:%[0-9]+]]:gpr = FEQ_D [[COPY]], [[COPY]] + ; CHECK-NEXT: [[FEQ_D1:%[0-9]+]]:gpr = FEQ_D [[COPY1]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_D]], [[FEQ_D1]] + ; CHECK-NEXT: $x10 = COPY [[AND]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(ord), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ueq_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ueq_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[FLT_D1:%[0-9]+]]:gpr = FLT_D [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_D]], [[FLT_D1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[OR]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(ueq), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ugt_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ugt_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLE_D:%[0-9]+]]:gpr = FLE_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_D]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(ugt), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uge_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_uge_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_D]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(uge), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ult_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ult_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLE_D:%[0-9]+]]:gpr = FLE_D [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_D]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(ult), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ule_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ule_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_D]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(ule), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_une_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_une_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FEQ_D:%[0-9]+]]:gpr = FEQ_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FEQ_D]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(une), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uno_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_uno_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FEQ_D:%[0-9]+]]:gpr = FEQ_D [[COPY]], [[COPY]] + ; CHECK-NEXT: [[FEQ_D1:%[0-9]+]]:gpr = FEQ_D [[COPY1]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_D]], [[FEQ_D1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[AND]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s32) = G_FCMP floatpred(uno), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-rv64.mir new file mode 100644 index 0000000..8b7c4a0 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-rv64.mir @@ -0,0 +1,706 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fcmp_oeq_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_oeq_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FEQ_S:%[0-9]+]]:gpr = nofpexcept FEQ_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FEQ_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(oeq), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ogt_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ogt_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLT_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(ogt), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oge_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_oge_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = FLE_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLE_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(oge), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_olt_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_olt_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = nofpexcept FLT_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FLT_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(olt), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ole_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ole_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = nofpexcept FLE_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FLE_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(ole), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_one_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_one_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[FLT_S1:%[0-9]+]]:gpr = FLT_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_S]], [[FLT_S1]] + ; CHECK-NEXT: $x10 = COPY [[OR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(one), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ord_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ord_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FEQ_S:%[0-9]+]]:gpr = FEQ_S [[COPY]], [[COPY]] + ; CHECK-NEXT: [[FEQ_S1:%[0-9]+]]:gpr = FEQ_S [[COPY1]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_S]], [[FEQ_S1]] + ; CHECK-NEXT: $x10 = COPY [[AND]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(ord), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ueq_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ueq_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[FLT_S1:%[0-9]+]]:gpr = FLT_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_S]], [[FLT_S1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[OR]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(ueq), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ugt_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ugt_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = FLE_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_S]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(ugt), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uge_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_uge_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_S]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(uge), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ult_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ult_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = FLE_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_S]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(ult), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ule_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ule_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FLT_S:%[0-9]+]]:gpr = FLT_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_S]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(ule), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_une_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_une_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FEQ_S:%[0-9]+]]:gpr = FEQ_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FEQ_S]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(une), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uno_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_uno_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FEQ_S:%[0-9]+]]:gpr = FEQ_S [[COPY]], [[COPY]] + ; CHECK-NEXT: [[FEQ_S1:%[0-9]+]]:gpr = FEQ_S [[COPY1]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_S]], [[FEQ_S1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[AND]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %4:gprb(s64) = G_FCMP floatpred(uno), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oeq_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_oeq_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FEQ_D:%[0-9]+]]:gpr = nofpexcept FEQ_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FEQ_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(oeq), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ogt_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ogt_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLT_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(ogt), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oge_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_oge_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLE_D:%[0-9]+]]:gpr = FLE_D [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLE_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(oge), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_olt_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_olt_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = nofpexcept FLT_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FLT_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(olt), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ole_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ole_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLE_D:%[0-9]+]]:gpr = nofpexcept FLE_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FLE_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(ole), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_one_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_one_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[FLT_D1:%[0-9]+]]:gpr = FLT_D [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_D]], [[FLT_D1]] + ; CHECK-NEXT: $x10 = COPY [[OR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(one), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ord_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ord_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FEQ_D:%[0-9]+]]:gpr = FEQ_D [[COPY]], [[COPY]] + ; CHECK-NEXT: [[FEQ_D1:%[0-9]+]]:gpr = FEQ_D [[COPY1]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_D]], [[FEQ_D1]] + ; CHECK-NEXT: $x10 = COPY [[AND]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(ord), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ueq_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ueq_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[FLT_D1:%[0-9]+]]:gpr = FLT_D [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_D]], [[FLT_D1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[OR]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(ueq), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ugt_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ugt_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLE_D:%[0-9]+]]:gpr = FLE_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_D]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(ugt), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uge_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_uge_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_D]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(uge), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ult_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ult_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLE_D:%[0-9]+]]:gpr = FLE_D [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_D]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(ult), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ule_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ule_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FLT_D:%[0-9]+]]:gpr = FLT_D [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_D]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(ule), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_une_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_une_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FEQ_D:%[0-9]+]]:gpr = FEQ_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FEQ_D]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(une), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uno_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_uno_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FEQ_D:%[0-9]+]]:gpr = FEQ_D [[COPY]], [[COPY]] + ; CHECK-NEXT: [[FEQ_D1:%[0-9]+]]:gpr = FEQ_D [[COPY1]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_D]], [[FEQ_D1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[AND]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %4:gprb(s64) = G_FCMP floatpred(uno), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir new file mode 100644 index 0000000..855764a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir @@ -0,0 +1,366 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fadd_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fadd_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FADD_H:%[0-9]+]]:fpr16 = nofpexcept FADD_H [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FADD_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %2:fprb(s16) = G_FADD %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fsub_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fsub_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FSUB_H:%[0-9]+]]:fpr16 = nofpexcept FSUB_H [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FSUB_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %2:fprb(s16) = G_FSUB %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fmul_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fmul_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FMUL_H:%[0-9]+]]:fpr16 = nofpexcept FMUL_H [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FMUL_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %2:fprb(s16) = G_FMUL %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fdiv_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fdiv_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FDIV_H:%[0-9]+]]:fpr16 = nofpexcept FDIV_H [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FDIV_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %2:fprb(s16) = G_FDIV %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fma_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h, $f12_h + + ; CHECK-LABEL: name: fma_f16 + ; CHECK: liveins: $f10_h, $f11_h, $f12_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $f12_h + ; CHECK-NEXT: [[FMADD_H:%[0-9]+]]:fpr16 = nofpexcept FMADD_H [[COPY]], [[COPY1]], [[COPY2]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FMADD_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %2:fprb(s16) = COPY $f12_h + %3:fprb(s16) = G_FMA %0, %1, %2 + $f10_h = COPY %3(s16) + PseudoRET implicit $f10_h + +... +--- +name: fneg_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h, $f12_h + + ; CHECK-LABEL: name: fneg_f16 + ; CHECK: liveins: $f10_h, $f11_h, $f12_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FSGNJN_H:%[0-9]+]]:fpr16 = FSGNJN_H [[COPY]], [[COPY]] + ; CHECK-NEXT: $f10_h = COPY [[FSGNJN_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = G_FNEG %0 + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: fabs_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h, $f12_h + + ; CHECK-LABEL: name: fabs_f16 + ; CHECK: liveins: $f10_h, $f11_h, $f12_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FSGNJX_H:%[0-9]+]]:fpr16 = FSGNJX_H [[COPY]], [[COPY]] + ; CHECK-NEXT: $f10_h = COPY [[FSGNJX_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = G_FABS %0 + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: fsqrt_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h, $f12_h + + ; CHECK-LABEL: name: fsqrt_f16 + ; CHECK: liveins: $f10_h, $f11_h, $f12_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FSQRT_H:%[0-9]+]]:fpr16 = nofpexcept FSQRT_H [[COPY]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FSQRT_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = G_FSQRT %0 + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: fmaxnum_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fmaxnum_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FMAX_H:%[0-9]+]]:fpr16 = nofpexcept FMAX_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FMAX_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %2:fprb(s16) = G_FMAXNUM %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fminnum_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fminnum_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FMIN_H:%[0-9]+]]:fpr16 = nofpexcept FMIN_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FMIN_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %2:fprb(s16) = G_FMINNUM %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fcopysign_f16_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcopysign_f16_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = COPY $f11_h + %2:fprb(s16) = G_FCOPYSIGN %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fcopysign_f16_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_f + + ; CHECK-LABEL: name: fcopysign_f16_f32 + ; CHECK: liveins: $f10_h, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FCVT_H_S:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_S [[COPY1]], 7 + ; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[FCVT_H_S]] + ; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s32) = COPY $f11_f + %2:fprb(s16) = G_FCOPYSIGN %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fcopysign_f32_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_h + + ; CHECK-LABEL: name: fcopysign_f32_f16 + ; CHECK: liveins: $f10_f, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FCVT_S_H:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_H [[COPY1]], 0 + ; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[FCVT_S_H]] + ; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s16) = COPY $f11_h + %2:fprb(s32) = G_FCOPYSIGN %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fcopysign_f16_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_d + + ; CHECK-LABEL: name: fcopysign_f16_f64 + ; CHECK: liveins: $f10_h, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FCVT_H_D:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_D [[COPY1]], 7 + ; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[FCVT_H_D]] + ; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s64) = COPY $f11_d + %2:fprb(s16) = G_FCOPYSIGN %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fcopysign_f64_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_h + + ; CHECK-LABEL: name: fcopysign_f64_f16 + ; CHECK: liveins: $f10_d, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h + ; CHECK-NEXT: [[FCVT_D_H:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_H [[COPY1]], 0 + ; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[FCVT_D_H]] + ; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s16) = COPY $f11_h + %2:fprb(s64) = G_FCOPYSIGN %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir new file mode 100644 index 0000000..45cba58 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir @@ -0,0 +1,576 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fadd_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fadd_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_f = COPY [[FADD_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %2:fprb(s32) = G_FADD %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fsub_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fsub_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FSUB_S:%[0-9]+]]:fpr32 = nofpexcept FSUB_S [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_f = COPY [[FSUB_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %2:fprb(s32) = G_FSUB %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fmul_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fmul_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FMUL_S:%[0-9]+]]:fpr32 = nofpexcept FMUL_S [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_f = COPY [[FMUL_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %2:fprb(s32) = G_FMUL %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fdiv_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fdiv_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FDIV_S:%[0-9]+]]:fpr32 = nofpexcept FDIV_S [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_f = COPY [[FDIV_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %2:fprb(s32) = G_FDIV %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fma_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f, $f12_f + + ; CHECK-LABEL: name: fma_f32 + ; CHECK: liveins: $f10_f, $f11_f, $f12_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f12_f + ; CHECK-NEXT: [[FMADD_S:%[0-9]+]]:fpr32 = nofpexcept FMADD_S [[COPY]], [[COPY1]], [[COPY2]], 7 + ; CHECK-NEXT: $f10_f = COPY [[FMADD_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %2:fprb(s32) = COPY $f12_f + %3:fprb(s32) = G_FMA %0, %1, %2 + $f10_f = COPY %3(s32) + PseudoRET implicit $f10_f + +... +--- +name: fneg_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f, $f12_f + + ; CHECK-LABEL: name: fneg_f32 + ; CHECK: liveins: $f10_f, $f11_f, $f12_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FSGNJN_S:%[0-9]+]]:fpr32 = FSGNJN_S [[COPY]], [[COPY]] + ; CHECK-NEXT: $f10_f = COPY [[FSGNJN_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = G_FNEG %0 + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fabs_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f, $f12_f + + ; CHECK-LABEL: name: fabs_f32 + ; CHECK: liveins: $f10_f, $f11_f, $f12_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FSGNJX_S:%[0-9]+]]:fpr32 = FSGNJX_S [[COPY]], [[COPY]] + ; CHECK-NEXT: $f10_f = COPY [[FSGNJX_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = G_FABS %0 + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fsqrt_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f, $f12_f + + ; CHECK-LABEL: name: fsqrt_f32 + ; CHECK: liveins: $f10_f, $f11_f, $f12_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FSQRT_S:%[0-9]+]]:fpr32 = nofpexcept FSQRT_S [[COPY]], 7 + ; CHECK-NEXT: $f10_f = COPY [[FSQRT_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = G_FSQRT %0 + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fmaxnum_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fmaxnum_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FMAX_S:%[0-9]+]]:fpr32 = nofpexcept FMAX_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FMAX_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %2:fprb(s32) = G_FMAXNUM %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fminnum_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fminnum_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FMIN_S:%[0-9]+]]:fpr32 = nofpexcept FMIN_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FMIN_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %2:fprb(s32) = G_FMINNUM %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fcopysign_f32_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcopysign_f32_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = COPY $f11_f + %2:fprb(s32) = G_FCOPYSIGN %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fcopysign_f32_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_d + + ; CHECK-LABEL: name: fcopysign_f32_f64 + ; CHECK: liveins: $f10_f, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FCVT_S_D:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_D [[COPY1]], 7 + ; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[FCVT_S_D]] + ; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s64) = COPY $f11_d + %2:fprb(s32) = G_FCOPYSIGN %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fadd_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fadd_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_d = COPY [[FADD_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %2:fprb(s64) = G_FADD %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fsub_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fsub_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FSUB_D:%[0-9]+]]:fpr64 = nofpexcept FSUB_D [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_d = COPY [[FSUB_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %2:fprb(s64) = G_FSUB %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fmul_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fmul_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FMUL_D:%[0-9]+]]:fpr64 = nofpexcept FMUL_D [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_d = COPY [[FMUL_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %2:fprb(s64) = G_FMUL %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fdiv_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fdiv_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FDIV_D:%[0-9]+]]:fpr64 = nofpexcept FDIV_D [[COPY]], [[COPY1]], 7 + ; CHECK-NEXT: $f10_d = COPY [[FDIV_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %2:fprb(s64) = G_FDIV %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fma_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d, $f12_d + + ; CHECK-LABEL: name: fma_f64 + ; CHECK: liveins: $f10_d, $f11_d, $f12_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f12_d + ; CHECK-NEXT: [[FMADD_D:%[0-9]+]]:fpr64 = nofpexcept FMADD_D [[COPY]], [[COPY1]], [[COPY2]], 7 + ; CHECK-NEXT: $f10_d = COPY [[FMADD_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %2:fprb(s64) = COPY $f12_d + %3:fprb(s64) = G_FMA %0, %1, %2 + $f10_d = COPY %3(s64) + PseudoRET implicit $f10_d + +... +--- +name: fneg_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: fneg_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FSGNJN_D:%[0-9]+]]:fpr64 = FSGNJN_D [[COPY]], [[COPY]] + ; CHECK-NEXT: $f10_d = COPY [[FSGNJN_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = G_FNEG %0 + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fabs_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: fabs_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FSGNJX_D:%[0-9]+]]:fpr64 = FSGNJX_D [[COPY]], [[COPY]] + ; CHECK-NEXT: $f10_d = COPY [[FSGNJX_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = G_FABS %0 + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fsqrt_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: fsqrt_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FSQRT_D:%[0-9]+]]:fpr64 = nofpexcept FSQRT_D [[COPY]], 7 + ; CHECK-NEXT: $f10_d = COPY [[FSQRT_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = G_FSQRT %0 + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fmaxnum_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fmaxnum_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FMAX_D:%[0-9]+]]:fpr64 = nofpexcept FMAX_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FMAX_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %2:fprb(s64) = G_FMAXNUM %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fminnum_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fminnum_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FMIN_D:%[0-9]+]]:fpr64 = nofpexcept FMIN_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FMIN_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %2:fprb(s64) = G_FMINNUM %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fcopysign_f64_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcopysign_f64_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = COPY $f11_d + %2:fprb(s64) = G_FCOPYSIGN %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fcopysign_f64_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_f + + ; CHECK-LABEL: name: fcopysign_f64_f32 + ; CHECK: liveins: $f10_d, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[FCVT_D_S:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_S [[COPY1]], 0 + ; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[FCVT_D_S]] + ; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s32) = COPY $f11_f + %2:fprb(s64) = G_FCOPYSIGN %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant-f16.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant-f16.mir new file mode 100644 index 0000000..a688153 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant-f16.mir @@ -0,0 +1,87 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: half_imm +legalized: true +regBankSelected: true +body: | + bb.1: + ; CHECK-LABEL: name: half_imm + ; CHECK: [[LUI:%[0-9]+]]:gpr = LUI 4 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 584 + ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[ADDI]] + ; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = G_FCONSTANT half 0xH4248 + $f10_h = COPY %0(s16) + PseudoRET implicit $f10_h + +... +--- +name: half_imm_op +legalized: true +regBankSelected: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: half_imm_op + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 15 + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 10 + ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[SLLI]] + ; CHECK-NEXT: [[FADD_H:%[0-9]+]]:fpr16 = nofpexcept FADD_H [[COPY]], [[FMV_H_X]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FADD_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s16) = COPY $f10_h + %1:fprb(s16) = G_FCONSTANT half 1.000000e+00 + %2:fprb(s16) = G_FADD %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: half_positive_zero +legalized: true +regBankSelected: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: half_positive_zero + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X $x0 + ; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:fprb(s16) = G_FCONSTANT half 0.000000e+00 + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: half_negative_zero +legalized: true +regBankSelected: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: half_negative_zero + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1048568 + ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[LUI]] + ; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:fprb(s16) = G_FCONSTANT half -0.000000e+00 + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant.mir new file mode 100644 index 0000000..7dde777 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant.mir @@ -0,0 +1,210 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV32 +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV64 + +--- +name: float_imm +legalized: true +regBankSelected: true +body: | + bb.1: + ; CHECK-LABEL: name: float_imm + ; CHECK: [[LUI:%[0-9]+]]:gpr = LUI 263313 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -37 + ; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[ADDI]] + ; CHECK-NEXT: $f10_f = COPY [[FMV_W_X]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = G_FCONSTANT float 0x400921FB60000000 + $f10_f = COPY %0(s32) + PseudoRET implicit $f10_f + +... +--- +name: float_imm_op +legalized: true +regBankSelected: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: float_imm_op + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 260096 + ; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[LUI]] + ; CHECK-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[COPY]], [[FMV_W_X]], 7 + ; CHECK-NEXT: $f10_f = COPY [[FADD_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s32) = COPY $f10_f + %1:fprb(s32) = G_FCONSTANT float 1.000000e+00 + %2:fprb(s32) = G_FADD %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: float_positive_zero +legalized: true +regBankSelected: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: float_positive_zero + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X $x0 + ; CHECK-NEXT: $f10_f = COPY [[FMV_W_X]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:fprb(s32) = G_FCONSTANT float 0.000000e+00 + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: float_negative_zero +legalized: true +regBankSelected: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: float_negative_zero + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288 + ; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[LUI]] + ; CHECK-NEXT: $f10_f = COPY [[FMV_W_X]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:fprb(s32) = G_FCONSTANT float -0.000000e+00 + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: double_imm +legalized: true +regBankSelected: true +body: | + bb.1: + ; RV32-LABEL: name: double_imm + ; RV32: [[LUI:%[0-9]+]]:gpr = LUI 262290 + ; RV32-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 507 + ; RV32-NEXT: [[LUI1:%[0-9]+]]:gpr = LUI 345155 + ; RV32-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[LUI1]], -744 + ; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[ADDI1]], [[ADDI]] + ; RV32-NEXT: $f10_d = COPY [[BuildPairF64Pseudo]] + ; RV32-NEXT: PseudoRET implicit $f10_d + ; + ; RV64-LABEL: name: double_imm + ; RV64: [[LUI:%[0-9]+]]:gpr = LUI 512 + ; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 1169 + ; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 15 + ; RV64-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[SLLI]], -299 + ; RV64-NEXT: [[SLLI1:%[0-9]+]]:gpr = SLLI [[ADDI1]], 14 + ; RV64-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI [[SLLI1]], 1091 + ; RV64-NEXT: [[SLLI2:%[0-9]+]]:gpr = SLLI [[ADDI2]], 12 + ; RV64-NEXT: [[ADDI3:%[0-9]+]]:gpr = ADDI [[SLLI2]], -744 + ; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[ADDI3]] + ; RV64-NEXT: $f10_d = COPY [[FMV_D_X]] + ; RV64-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = G_FCONSTANT double 0x400921FB54442D18 + $f10_d = COPY %0(s64) + PseudoRET implicit $f10_d + +... +--- +name: double_imm_op +legalized: true +regBankSelected: true +body: | + bb.1: + liveins: $f10_d + + ; RV32-LABEL: name: double_imm_op + ; RV32: liveins: $f10_d + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; RV32-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 261888 + ; RV32-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY1]], [[LUI]] + ; RV32-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[BuildPairF64Pseudo]], 7 + ; RV32-NEXT: $f10_d = COPY [[FADD_D]] + ; RV32-NEXT: PseudoRET implicit $f10_d + ; + ; RV64-LABEL: name: double_imm_op + ; RV64: liveins: $f10_d + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1023 + ; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 52 + ; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[SLLI]] + ; RV64-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[FMV_D_X]], 7 + ; RV64-NEXT: $f10_d = COPY [[FADD_D]] + ; RV64-NEXT: PseudoRET implicit $f10_d + %0:fprb(s64) = COPY $f10_d + %1:fprb(s64) = G_FCONSTANT double 1.000000e+00 + %2:fprb(s64) = G_FADD %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: double_positive_zero +legalized: true +regBankSelected: true +body: | + bb.1: + liveins: $x10 + + ; RV32-LABEL: name: double_positive_zero + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W $x0, 0 + ; RV32-NEXT: $f10_d = COPY [[FCVT_D_W]] + ; RV32-NEXT: PseudoRET implicit $f10_d + ; + ; RV64-LABEL: name: double_positive_zero + ; RV64: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X $x0 + ; RV64-NEXT: $f10_d = COPY [[FMV_D_X]] + ; RV64-NEXT: PseudoRET implicit $f10_d + %1:fprb(s64) = G_FCONSTANT double 0.000000e+00 + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: double_negative_zero +legalized: true +regBankSelected: true +body: | + bb.1: + liveins: $x10 + + ; RV32-LABEL: name: double_negative_zero + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288 + ; RV32-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY]], [[LUI]] + ; RV32-NEXT: $f10_d = COPY [[BuildPairF64Pseudo]] + ; RV32-NEXT: PseudoRET implicit $f10_d + ; + ; RV64-LABEL: name: double_negative_zero + ; RV64: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 + ; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 63 + ; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[SLLI]] + ; RV64-NEXT: $f10_d = COPY [[FMV_D_X]] + ; RV64-NEXT: PseudoRET implicit $f10_d + %1:fprb(s64) = G_FCONSTANT double -0.000000e+00 + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-ext-trunc-f16.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-ext-trunc-f16.mir new file mode 100644 index 0000000..966604c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-ext-trunc-f16.mir @@ -0,0 +1,94 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fpext_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fpext_f32 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCVT_S_H:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_H [[COPY]], 0 + ; CHECK-NEXT: $f10_f = COPY [[FCVT_S_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s16) = COPY $f10_h + %1:fprb(s32) = G_FPEXT %0(s16) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fptrunc_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptrunc_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCVT_H_S:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_S [[COPY]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s32) = COPY $f10_f + %1:fprb(s16) = G_FPTRUNC %0(s32) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: fpext_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fpext_f64 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCVT_D_H:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_H [[COPY]], 0 + ; CHECK-NEXT: $f10_d = COPY [[FCVT_D_H]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s16) = COPY $f10_h + %1:fprb(s64) = G_FPEXT %0(s16) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fptrunc_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptrunc_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCVT_H_D:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_D [[COPY]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:fprb(s64) = COPY $f10_d + %1:fprb(s16) = G_FPTRUNC %0(s64) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-ext-trunc.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-ext-trunc.mir new file mode 100644 index 0000000..9f0de60 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-ext-trunc.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fpext +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fpext + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCVT_D_S:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_S [[COPY]], 0 + ; CHECK-NEXT: $f10_d = COPY [[FCVT_D_S]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:fprb(s32) = COPY $f10_f + %1:fprb(s64) = G_FPEXT %0(s32) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fptrunc +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptrunc + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCVT_S_D:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_D [[COPY]], 7 + ; CHECK-NEXT: $f10_f = COPY [[FCVT_S_D]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:fprb(s64) = COPY $f10_d + %1:fprb(s32) = G_FPTRUNC %0(s64) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir new file mode 100644 index 0000000..b137b64 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir @@ -0,0 +1,140 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=instruction-select %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=instruction-select %s -o - \ +# RUN: | FileCheck %s + +--- +name: fp_store_f32 +legalized: true +regBankSelected: true +selected: false +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $f10_f + + ; CHECK-LABEL: name: fp_store_f32 + ; CHECK: liveins: $x10, $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: FSW [[COPY1]], [[COPY]], 0 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + %0:gprb(p0) = COPY $x10 + %1:fprb(s32) = COPY $f10_f + G_STORE %1(s32), %0(p0) :: (store (s32)) + PseudoRET + +... +--- +name: fp_store_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $f10_d + + ; CHECK-LABEL: name: fp_store_f64 + ; CHECK: liveins: $x10, $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: FSD [[COPY1]], [[COPY]], 0 :: (store (s64)) + ; CHECK-NEXT: PseudoRET + %0:gprb(p0) = COPY $x10 + %1:fprb(s64) = COPY $f10_d + G_STORE %1(s64), %0(p0) :: (store (s64)) + PseudoRET + +... +--- +name: fp_load_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: fp_load_f32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FLW:%[0-9]+]]:fpr32 = FLW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: $f10_f = COPY [[FLW]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:gprb(p0) = COPY $x10 + %1:fprb(s32) = G_LOAD %0(p0) :: (load (s32)) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fp_load_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: fp_load_f64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FLD:%[0-9]+]]:fpr64 = FLD [[COPY]], 0 :: (load (s64)) + ; CHECK-NEXT: $f10_d = COPY [[FLD]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:gprb(p0) = COPY $x10 + %1:fprb(s64) = G_LOAD %0(p0) :: (load (s64)) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fp_store_f16 +legalized: true +regBankSelected: true +selected: false +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $f10_h + + ; CHECK-LABEL: name: fp_store_f16 + ; CHECK: liveins: $x10, $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: FSH [[COPY1]], [[COPY]], 0 :: (store (s16)) + ; CHECK-NEXT: PseudoRET + %0:gprb(p0) = COPY $x10 + %1:fprb(s16) = COPY $f10_h + G_STORE %1(s16), %0(p0) :: (store (s16)) + PseudoRET + +... +--- +name: fp_load_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: fp_load_f16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FLH:%[0-9]+]]:fpr16 = FLH [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: $f10_h = COPY [[FLH]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:gprb(p0) = COPY $x10 + %1:fprb(s16) = G_LOAD %0(p0) :: (load (s16)) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv32.mir new file mode 100644 index 0000000..9d898c4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv32.mir @@ -0,0 +1,62 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fp_select_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_f, $f11_f + + ; CHECK-LABEL: name: fp_select_s32 + ; CHECK: liveins: $x10, $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1 + ; CHECK-NEXT: [[Select_FPR32_Using_CC_GPR:%[0-9]+]]:fpr32 = Select_FPR32_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $f10_f = COPY [[Select_FPR32_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:gprb(s32) = COPY $x10 + %1:fprb(s32) = COPY $f10_f + %2:fprb(s32) = COPY $f11_f + %3:gprb(s32) = G_CONSTANT i32 1 + %4:gprb(s32) = G_AND %0, %3 + %5:fprb(s32) = G_SELECT %4(s32), %1, %2 + $f10_f = COPY %5(s32) + PseudoRET implicit $f10_f + +... +--- +name: fp_select_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_d, $f11_d + + ; CHECK-LABEL: name: fp_select_s64 + ; CHECK: liveins: $x10, $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1 + ; CHECK-NEXT: [[Select_FPR64_Using_CC_GPR:%[0-9]+]]:fpr64 = Select_FPR64_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $f10_d = COPY [[Select_FPR64_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:gprb(s32) = COPY $x10 + %1:fprb(s64) = COPY $f10_d + %2:fprb(s64) = COPY $f11_d + %3:gprb(s32) = G_CONSTANT i32 1 + %4:gprb(s32) = G_AND %0, %3 + %5:fprb(s64) = G_SELECT %4(s32), %1, %2 + $f10_d = COPY %5(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv64.mir new file mode 100644 index 0000000..e291c35 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv64.mir @@ -0,0 +1,64 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fp_select_s32 +alignment: 1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_d, $f11_d + + ; CHECK-LABEL: name: fp_select_s32 + ; CHECK: liveins: $x10, $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1 + ; CHECK-NEXT: [[Select_FPR32_Using_CC_GPR:%[0-9]+]]:fpr32 = Select_FPR32_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $f10_f = COPY [[Select_FPR32_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:gprb(s64) = COPY $x10 + %1:fprb(s32) = COPY $f10_f + %2:fprb(s32) = COPY $f11_f + %3:gprb(s64) = G_CONSTANT i64 1 + %4:gprb(s64) = G_AND %0, %3 + %5:fprb(s32) = G_SELECT %4(s64), %1, %2 + $f10_f = COPY %5(s32) + PseudoRET implicit $f10_f + +... +--- +name: fp_select_s64 +alignment: 1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_d, $f11_d + + ; CHECK-LABEL: name: fp_select_s64 + ; CHECK: liveins: $x10, $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f11_d + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1 + ; CHECK-NEXT: [[Select_FPR64_Using_CC_GPR:%[0-9]+]]:fpr64 = Select_FPR64_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $f10_d = COPY [[Select_FPR64_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:gprb(s64) = COPY $x10 + %1:fprb(s64) = COPY $f10_d + %2:fprb(s64) = COPY $f11_d + %3:gprb(s64) = G_CONSTANT i64 1 + %4:gprb(s64) = G_AND %0, %3 + %5:fprb(s64) = G_SELECT %4(s64), %1, %2 + $f10_d = COPY %5(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv32.mir new file mode 100644 index 0000000..13dac86 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv32.mir @@ -0,0 +1,48 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fptosi_s32_s16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s32_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCVT_W_H:%[0-9]+]]:gpr = nofpexcept FCVT_W_H [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:gprb(s32) = G_FPTOSI %0(s16) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s32_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCVT_WU_H:%[0-9]+]]:gpr = nofpexcept FCVT_WU_H [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:gprb(s32) = G_FPTOUI %0(s16) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir new file mode 100644 index 0000000..eb5558b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir @@ -0,0 +1,92 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fptosi_s32_s16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s32_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCVT_W_H:%[0-9]+]]:gpr = nofpexcept FCVT_W_H [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:gprb(s64) = G_FCVT_W_RV64 %0(s16), 1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s32_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCVT_WU_H:%[0-9]+]]:gpr = nofpexcept FCVT_WU_H [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:gprb(s64) = G_FCVT_WU_RV64 %0(s16), 1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s64_s16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s64_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCVT_L_H:%[0-9]+]]:gpr = nofpexcept FCVT_L_H [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_L_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:gprb(s64) = G_FPTOSI %0(s16) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s64_s16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s64_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCVT_LU_H:%[0-9]+]]:gpr = nofpexcept FCVT_LU_H [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_LU_H]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %1:gprb(s64) = G_FPTOUI %0(s16) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv32.mir new file mode 100644 index 0000000..ab737be --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv32.mir @@ -0,0 +1,92 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fptosi_s32_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s32_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCVT_W_S:%[0-9]+]]:gpr = nofpexcept FCVT_W_S [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:gprb(s32) = G_FPTOSI %0(s32) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s32_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCVT_WU_S:%[0-9]+]]:gpr = nofpexcept FCVT_WU_S [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:gprb(s32) = G_FPTOUI %0(s32) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s32_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCVT_W_D:%[0-9]+]]:gpr = nofpexcept FCVT_W_D [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:gprb(s32) = G_FPTOSI %0(s64) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s32_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCVT_WU_D:%[0-9]+]]:gpr = nofpexcept FCVT_WU_D [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:gprb(s32) = G_FPTOUI %0(s64) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir new file mode 100644 index 0000000..9c3b306 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir @@ -0,0 +1,180 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: fptosi_s32_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s32_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCVT_W_S:%[0-9]+]]:gpr = nofpexcept FCVT_W_S [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:gprb(s64) = G_FCVT_W_RV64 %0(s32), 1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s32_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCVT_WU_S:%[0-9]+]]:gpr = nofpexcept FCVT_WU_S [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:gprb(s64) = G_FCVT_WU_RV64 %0(s32), 1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s64_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s64_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCVT_L_S:%[0-9]+]]:gpr = nofpexcept FCVT_L_S [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_L_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:gprb(s64) = G_FPTOSI %0(s32) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s64_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s64_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCVT_LU_S:%[0-9]+]]:gpr = nofpexcept FCVT_LU_S [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_LU_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %1:gprb(s64) = G_FPTOUI %0(s32) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s32_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCVT_W_D:%[0-9]+]]:gpr = nofpexcept FCVT_W_D [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:gprb(s64) = G_FCVT_W_RV64 %0(s64), 1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s32_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCVT_WU_D:%[0-9]+]]:gpr = nofpexcept FCVT_WU_D [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:gprb(s64) = G_FCVT_WU_RV64 %0(s64), 1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s64_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s64_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCVT_L_D:%[0-9]+]]:gpr = nofpexcept FCVT_L_D [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_L_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:gprb(s64) = G_FPTOSI %0(s64) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s64_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s64_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCVT_LU_D:%[0-9]+]]:gpr = nofpexcept FCVT_LU_D [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_LU_D]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:gprb(s64) = G_FPTOUI %0(s64) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir new file mode 100644 index 0000000..20747bd --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir @@ -0,0 +1,32 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \ +# RUN: | FileCheck %s +--- | + define ptr @frame_index() { + entry: + %x = alloca i32, align 4 + ret ptr %x + } + +... +--- +name: frame_index +legalized: true +regBankSelected: true +registers: + - { id: 0, class: gprb, preferred-register: '' } +stack: + - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.1.entry: + ; CHECK-LABEL: name: frame_index + ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0 + ; CHECK-NEXT: $x10 = COPY [[ADDI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = G_FRAME_INDEX %stack.0.x + $x10 = COPY %0(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir new file mode 100644 index 0000000..dc265bd --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir @@ -0,0 +1,32 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \ +# RUN: | FileCheck %s +--- | + define ptr @frame_index() { + entry: + %x = alloca i32, align 4 + ret ptr %x + } + +... +--- +name: frame_index +legalized: true +regBankSelected: true +registers: + - { id: 0, class: gprb, preferred-register: '' } +stack: + - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.1.entry: + ; CHECK-LABEL: name: frame_index + ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0 + ; CHECK-NEXT: $x10 = COPY [[ADDI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = G_FRAME_INDEX %stack.0.x + $x10 = COPY %0(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value32.mir new file mode 100644 index 0000000..8b4be5e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value32.mir @@ -0,0 +1,129 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -relocation-model=pic \ +# RUN: %s -o - | FileCheck --check-prefix=RV32-PIE %s +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select \ +# RUN: -mattr=+tagged-globals %s -o - | FileCheck \ +# RUN: --check-prefix=RV32-NOPIE-TAG %s +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -code-model=small \ +# RUN: %s -o - | FileCheck --check-prefix=RV32-SMALL-NOPIE-NOTAG %s +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -code-model=medium \ +# RUN: %s -o - | FileCheck --check-prefix=RV32-MED %s + + +--- | + @x = global i32 0, align 4 + define ptr @global_addr() { + entry: + ret ptr @x + } + @y = extern_weak global i32, align 4 + define ptr @extern_weak_global_addr() { + entry: + ret ptr @y + } + @z = dso_local global i32 0, align 4 + define ptr @local_global_addr() { + entry: + ret ptr @z + } +... +--- +name: global_addr +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gprb, preferred-register: '' } +body: | + bb.1.entry: + ; RV32-PIE-LABEL: name: global_addr + ; RV32-PIE: [[PseudoLGA:%[0-9]+]]:gpr = PseudoLGA @x :: (dereferenceable invariant load (p0) from got) + ; RV32-PIE-NEXT: $x10 = COPY [[PseudoLGA]] + ; RV32-PIE-NEXT: PseudoRET implicit $x10 + ; + ; RV32-NOPIE-TAG-LABEL: name: global_addr + ; RV32-NOPIE-TAG: [[PseudoLGA:%[0-9]+]]:gpr = PseudoLGA @x :: (dereferenceable invariant load (p0) from got) + ; RV32-NOPIE-TAG-NEXT: $x10 = COPY [[PseudoLGA]] + ; RV32-NOPIE-TAG-NEXT: PseudoRET implicit $x10 + ; + ; RV32-SMALL-NOPIE-NOTAG-LABEL: name: global_addr + ; RV32-SMALL-NOPIE-NOTAG: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) @x + ; RV32-SMALL-NOPIE-NOTAG-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], target-flags(riscv-lo) @x + ; RV32-SMALL-NOPIE-NOTAG-NEXT: $x10 = COPY [[ADDI]] + ; RV32-SMALL-NOPIE-NOTAG-NEXT: PseudoRET implicit $x10 + ; + ; RV32-MED-LABEL: name: global_addr + ; RV32-MED: [[PseudoLLA:%[0-9]+]]:gpr = PseudoLLA @x + ; RV32-MED-NEXT: $x10 = COPY [[PseudoLLA]] + ; RV32-MED-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = G_GLOBAL_VALUE @x + $x10 = COPY %0(p0) + PseudoRET implicit $x10 +... +--- +name: extern_weak_global_addr +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gprb, preferred-register: '' } +body: | + bb.1.entry: + ; RV32-PIE-LABEL: name: extern_weak_global_addr + ; RV32-PIE: [[PseudoLGA:%[0-9]+]]:gpr = PseudoLGA @y :: (dereferenceable invariant load (p0) from got) + ; RV32-PIE-NEXT: $x10 = COPY [[PseudoLGA]] + ; RV32-PIE-NEXT: PseudoRET implicit $x10 + ; + ; RV32-NOPIE-TAG-LABEL: name: extern_weak_global_addr + ; RV32-NOPIE-TAG: [[PseudoLGA:%[0-9]+]]:gpr = PseudoLGA @y :: (dereferenceable invariant load (p0) from got) + ; RV32-NOPIE-TAG-NEXT: $x10 = COPY [[PseudoLGA]] + ; RV32-NOPIE-TAG-NEXT: PseudoRET implicit $x10 + ; + ; RV32-SMALL-NOPIE-NOTAG-LABEL: name: extern_weak_global_addr + ; RV32-SMALL-NOPIE-NOTAG: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) @y + ; RV32-SMALL-NOPIE-NOTAG-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], target-flags(riscv-lo) @y + ; RV32-SMALL-NOPIE-NOTAG-NEXT: $x10 = COPY [[ADDI]] + ; RV32-SMALL-NOPIE-NOTAG-NEXT: PseudoRET implicit $x10 + ; + ; RV32-MED-LABEL: name: extern_weak_global_addr + ; RV32-MED: [[PseudoLGA:%[0-9]+]]:gpr = PseudoLGA @y :: (dereferenceable invariant load (p0) from got) + ; RV32-MED-NEXT: $x10 = COPY [[PseudoLGA]] + ; RV32-MED-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = G_GLOBAL_VALUE @y + $x10 = COPY %0(p0) + PseudoRET implicit $x10 +... +--- +name: local_global_addr +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gprb, preferred-register: '' } +body: | + bb.1.entry: + ; RV32-PIE-LABEL: name: local_global_addr + ; RV32-PIE: [[PseudoLLA:%[0-9]+]]:gpr = PseudoLLA @z + ; RV32-PIE-NEXT: $x10 = COPY [[PseudoLLA]] + ; RV32-PIE-NEXT: PseudoRET implicit $x10 + ; + ; RV32-NOPIE-TAG-LABEL: name: local_global_addr + ; RV32-NOPIE-TAG: [[PseudoLGA:%[0-9]+]]:gpr = PseudoLGA @z :: (dereferenceable invariant load (p0) from got) + ; RV32-NOPIE-TAG-NEXT: $x10 = COPY [[PseudoLGA]] + ; RV32-NOPIE-TAG-NEXT: PseudoRET implicit $x10 + ; + ; RV32-SMALL-NOPIE-NOTAG-LABEL: name: local_global_addr + ; RV32-SMALL-NOPIE-NOTAG: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) @z + ; RV32-SMALL-NOPIE-NOTAG-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], target-flags(riscv-lo) @z + ; RV32-SMALL-NOPIE-NOTAG-NEXT: $x10 = COPY [[ADDI]] + ; RV32-SMALL-NOPIE-NOTAG-NEXT: PseudoRET implicit $x10 + ; + ; RV32-MED-LABEL: name: local_global_addr + ; RV32-MED: [[PseudoLLA:%[0-9]+]]:gpr = PseudoLLA @z + ; RV32-MED-NEXT: $x10 = COPY [[PseudoLLA]] + ; RV32-MED-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = G_GLOBAL_VALUE @z + $x10 = COPY %0(p0) + PseudoRET implicit $x10 +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value64.mir new file mode 100644 index 0000000..8151749 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/global-value64.mir @@ -0,0 +1,128 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -relocation-model=pic \ +# RUN: %s -o - | FileCheck --check-prefix=RV64-PIE %s +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select \ +# RUN: -mattr=+tagged-globals %s -o - | FileCheck \ +# RUN: --check-prefix=RV64-NOPIE-TAG %s +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -code-model=small \ +# RUN: %s -o - | FileCheck --check-prefix=RV64-SMALL-NOPIE-NOTAG %s +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -code-model=medium \ +# RUN: %s -o - | FileCheck --check-prefix=RV64-MED %s + +--- | + @x = global i32 0, align 4 + define ptr @global_addr() { + entry: + ret ptr @x + } + @y = extern_weak global i32, align 4 + define ptr @extern_weak_global_addr() { + entry: + ret ptr @y + } + @z = dso_local global i32 0, align 4 + define ptr @local_global_addr() { + entry: + ret ptr @z + } +... +--- +name: global_addr +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gprb, preferred-register: '' } +body: | + bb.1.entry: + ; RV64-PIE-LABEL: name: global_addr + ; RV64-PIE: [[PseudoLGA:%[0-9]+]]:gpr = PseudoLGA @x :: (dereferenceable invariant load (p0) from got) + ; RV64-PIE-NEXT: $x10 = COPY [[PseudoLGA]] + ; RV64-PIE-NEXT: PseudoRET implicit $x10 + ; + ; RV64-NOPIE-TAG-LABEL: name: global_addr + ; RV64-NOPIE-TAG: [[PseudoLGA:%[0-9]+]]:gpr = PseudoLGA @x :: (dereferenceable invariant load (p0) from got) + ; RV64-NOPIE-TAG-NEXT: $x10 = COPY [[PseudoLGA]] + ; RV64-NOPIE-TAG-NEXT: PseudoRET implicit $x10 + ; + ; RV64-SMALL-NOPIE-NOTAG-LABEL: name: global_addr + ; RV64-SMALL-NOPIE-NOTAG: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) @x + ; RV64-SMALL-NOPIE-NOTAG-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], target-flags(riscv-lo) @x + ; RV64-SMALL-NOPIE-NOTAG-NEXT: $x10 = COPY [[ADDI]] + ; RV64-SMALL-NOPIE-NOTAG-NEXT: PseudoRET implicit $x10 + ; + ; RV64-MED-LABEL: name: global_addr + ; RV64-MED: [[PseudoLLA:%[0-9]+]]:gpr = PseudoLLA @x + ; RV64-MED-NEXT: $x10 = COPY [[PseudoLLA]] + ; RV64-MED-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = G_GLOBAL_VALUE @x + $x10 = COPY %0(p0) + PseudoRET implicit $x10 +... +--- +name: extern_weak_global_addr +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gprb, preferred-register: '' } +body: | + bb.1.entry: + ; RV64-PIE-LABEL: name: extern_weak_global_addr + ; RV64-PIE: [[PseudoLGA:%[0-9]+]]:gpr = PseudoLGA @y :: (dereferenceable invariant load (p0) from got) + ; RV64-PIE-NEXT: $x10 = COPY [[PseudoLGA]] + ; RV64-PIE-NEXT: PseudoRET implicit $x10 + ; + ; RV64-NOPIE-TAG-LABEL: name: extern_weak_global_addr + ; RV64-NOPIE-TAG: [[PseudoLGA:%[0-9]+]]:gpr = PseudoLGA @y :: (dereferenceable invariant load (p0) from got) + ; RV64-NOPIE-TAG-NEXT: $x10 = COPY [[PseudoLGA]] + ; RV64-NOPIE-TAG-NEXT: PseudoRET implicit $x10 + ; + ; RV64-SMALL-NOPIE-NOTAG-LABEL: name: extern_weak_global_addr + ; RV64-SMALL-NOPIE-NOTAG: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) @y + ; RV64-SMALL-NOPIE-NOTAG-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], target-flags(riscv-lo) @y + ; RV64-SMALL-NOPIE-NOTAG-NEXT: $x10 = COPY [[ADDI]] + ; RV64-SMALL-NOPIE-NOTAG-NEXT: PseudoRET implicit $x10 + ; + ; RV64-MED-LABEL: name: extern_weak_global_addr + ; RV64-MED: [[PseudoLGA:%[0-9]+]]:gpr = PseudoLGA @y :: (dereferenceable invariant load (p0) from got) + ; RV64-MED-NEXT: $x10 = COPY [[PseudoLGA]] + ; RV64-MED-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = G_GLOBAL_VALUE @y + $x10 = COPY %0(p0) + PseudoRET implicit $x10 +... +--- +name: local_global_addr +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gprb, preferred-register: '' } +body: | + bb.1.entry: + ; RV64-PIE-LABEL: name: local_global_addr + ; RV64-PIE: [[PseudoLLA:%[0-9]+]]:gpr = PseudoLLA @z + ; RV64-PIE-NEXT: $x10 = COPY [[PseudoLLA]] + ; RV64-PIE-NEXT: PseudoRET implicit $x10 + ; + ; RV64-NOPIE-TAG-LABEL: name: local_global_addr + ; RV64-NOPIE-TAG: [[PseudoLGA:%[0-9]+]]:gpr = PseudoLGA @z :: (dereferenceable invariant load (p0) from got) + ; RV64-NOPIE-TAG-NEXT: $x10 = COPY [[PseudoLGA]] + ; RV64-NOPIE-TAG-NEXT: PseudoRET implicit $x10 + ; + ; RV64-SMALL-NOPIE-NOTAG-LABEL: name: local_global_addr + ; RV64-SMALL-NOPIE-NOTAG: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) @z + ; RV64-SMALL-NOPIE-NOTAG-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], target-flags(riscv-lo) @z + ; RV64-SMALL-NOPIE-NOTAG-NEXT: $x10 = COPY [[ADDI]] + ; RV64-SMALL-NOPIE-NOTAG-NEXT: PseudoRET implicit $x10 + ; + ; RV64-MED-LABEL: name: local_global_addr + ; RV64-MED: [[PseudoLLA:%[0-9]+]]:gpr = PseudoLLA @z + ; RV64-MED-NEXT: $x10 = COPY [[PseudoLLA]] + ; RV64-MED-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = G_GLOBAL_VALUE @z + $x10 = COPY %0(p0) + PseudoRET implicit $x10 +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv32.mir new file mode 100644 index 0000000..cf0baeb --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv32.mir @@ -0,0 +1,1117 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s +--- +name: cmp_ult_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ult_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_slt_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ugt_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_sgt_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_eq_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[XOR]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ne_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ule_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_sle_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_uge_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_sge_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ult_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_slt_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ugt_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_sgt_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_eq_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[XOR]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ne_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ule_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_sle_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_uge_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_sge_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulti_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ulti_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 10 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slti_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_slti_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], -10 + ; CHECK-NEXT: $x10 = COPY [[SLTI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 -10 + %2:gprb(s32) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugti_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ugti_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 11 + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTIU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgti_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_sgti_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], -9 + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTI]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 -10 + %2:gprb(s32) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eqi_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_eqi_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], -10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[ADDI]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_nei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_nei_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 -10 + %2:gprb(s32) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ulei_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 11 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_slei_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], -9 + ; CHECK-NEXT: $x10 = COPY [[SLTI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 -10 + %2:gprb(s32) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ugei_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 10 + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTIU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_sgei_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], -10 + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTI]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 -10 + %2:gprb(s32) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulti_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ulti_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slti_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_slti_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -10 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[SLT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 -10 + %2:gprb(s32) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugti_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ugti_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgti_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_sgti_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -10 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[ADDI]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 -10 + %2:gprb(s32) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eqi_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_eqi_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[ADDI]] + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[XOR]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_nei_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_nei_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -10 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[ADDI]] + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 -10 + %2:gprb(s32) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulei_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ulei_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slei_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_slei_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -10 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[ADDI]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 -10 + %2:gprb(s32) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugei_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ugei_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[ADDI]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgei_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_sgei_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -10 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[ADDI]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 -10 + %2:gprb(s32) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq0_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_eq0_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 0 + %2:gprb(s32) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq0_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_eq0_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 0 + %2:gprb(s32) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne0_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ne0_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 0 + %2:gprb(s32) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne0_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ne0_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 0 + %2:gprb(s32) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_neg1_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ugt_neg1_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 -1 + %2:gprb(s32) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_neg1_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ugt_neg1_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i32 -1 + %2:gprb(s32) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv64.mir new file mode 100644 index 0000000..7b6506e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv64.mir @@ -0,0 +1,1117 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s +--- +name: cmp_ult_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ult_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_slt_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ugt_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_sgt_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_eq_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[XOR]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ne_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ule_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_sle_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_uge_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_sge_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ult_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_slt_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ugt_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_sgt_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_eq_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[XOR]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ne_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_ule_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_sle_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_uge_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_sge_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulti_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ulti_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 10 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slti_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_slti_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], -10 + ; CHECK-NEXT: $x10 = COPY [[SLTI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 -10 + %2:gprb(s64) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugti_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ugti_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 11 + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTIU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgti_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_sgti_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], -9 + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTI]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 -10 + %2:gprb(s64) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eqi_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_eqi_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], -10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[ADDI]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_nei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_nei_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 -10 + %2:gprb(s64) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ulei_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 11 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_slei_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], -9 + ; CHECK-NEXT: $x10 = COPY [[SLTI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 -10 + %2:gprb(s64) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ugei_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 10 + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTIU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_sgei_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], -10 + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTI]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 -10 + %2:gprb(s64) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulti_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ulti_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slti_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_slti_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -10 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[SLT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 -10 + %2:gprb(s64) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugti_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ugti_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgti_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_sgti_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -10 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[ADDI]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 -10 + %2:gprb(s64) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eqi_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_eqi_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[ADDI]] + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[XOR]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_nei_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_nei_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -10 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[ADDI]] + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 -10 + %2:gprb(s64) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulei_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ulei_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slei_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_slei_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -10 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[ADDI]], [[COPY]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 -10 + %2:gprb(s64) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugei_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ugei_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[ADDI]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgei_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_sgei_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -10 + ; CHECK-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[ADDI]] + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; CHECK-NEXT: $x10 = COPY [[XORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 -10 + %2:gprb(s64) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq0_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_eq0_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 0 + %2:gprb(s64) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq0_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_eq0_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLTIU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 0 + %2:gprb(s64) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne0_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ne0_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 0 + %2:gprb(s64) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne0_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ne0_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 0 + %2:gprb(s64) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_neg1_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ugt_neg1_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 -1 + %2:gprb(s64) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_neg1_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: cmp_ugt_neg1_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_CONSTANT i64 -1 + %2:gprb(s64) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv32.mir new file mode 100644 index 0000000..5450ac7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv32.mir @@ -0,0 +1,59 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+f -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32F %s + +--- +name: implicit_def_gpr +legalized: true +regBankSelected: true +body: | + bb.0: + ; RV32F-LABEL: name: implicit_def_gpr + ; RV32F: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF + ; RV32F-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[DEF]], [[DEF]] + ; RV32F-NEXT: $x10 = COPY [[ADD]] + %0:gprb(s32) = G_IMPLICIT_DEF + %1:gprb(s32) = G_ADD %0, %0 + $x10 = COPY %1(s32) +... +--- +name: implicit_def_copy_gpr +legalized: true +regBankSelected: true +body: | + bb.0: + ; RV32F-LABEL: name: implicit_def_copy_gpr + ; RV32F: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF + ; RV32F-NEXT: $x10 = COPY [[DEF]] + %0:gprb(s32) = G_IMPLICIT_DEF + %1:gprb(s32) = COPY %0(s32) + $x10 = COPY %1(s32) +... + +--- +name: implicit_def_fpr +legalized: true +regBankSelected: true +body: | + bb.0: + ; RV32F-LABEL: name: implicit_def_fpr + ; RV32F: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF + ; RV32F-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[DEF]], [[DEF]], 7 + ; RV32F-NEXT: $f10_f = COPY [[FADD_S]] + %0:fprb(s32) = G_IMPLICIT_DEF + %1:fprb(s32) = G_FADD %0, %0 + $f10_f = COPY %1(s32) +... +--- +name: implicit_def_copy_fpr +legalized: true +regBankSelected: true +body: | + bb.0: + ; RV32F-LABEL: name: implicit_def_copy_fpr + ; RV32F: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF + ; RV32F-NEXT: $f10_f = COPY [[DEF]] + %0:fprb(s32) = G_IMPLICIT_DEF + %1:fprb(s32) = COPY %0(s32) + $f10_f = COPY %1(s32) +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv64.mir new file mode 100644 index 0000000..e0fc237 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv64.mir @@ -0,0 +1,59 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV64D %s + +--- +name: implicit_def_gpr +legalized: true +regBankSelected: true +body: | + bb.0: + ; RV64D-LABEL: name: implicit_def_gpr + ; RV64D: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF + ; RV64D-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[DEF]], [[DEF]] + ; RV64D-NEXT: $x10 = COPY [[ADD]] + %0:gprb(s64) = G_IMPLICIT_DEF + %1:gprb(s64) = G_ADD %0, %0 + $x10 = COPY %1(s64) +... +--- +name: implicit_def_copy_gpr +legalized: true +regBankSelected: true +body: | + bb.0: + ; RV64D-LABEL: name: implicit_def_copy_gpr + ; RV64D: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF + ; RV64D-NEXT: $x10 = COPY [[DEF]] + %0:gprb(s64) = G_IMPLICIT_DEF + %1:gprb(s64) = COPY %0(s64) + $x10 = COPY %1(s64) +... + +--- +name: implicit_def_fpr +legalized: true +regBankSelected: true +body: | + bb.0: + ; RV64D-LABEL: name: implicit_def_fpr + ; RV64D: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF + ; RV64D-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[DEF]], [[DEF]], 7 + ; RV64D-NEXT: $f10_d = COPY [[FADD_D]] + %0:fprb(s64) = G_IMPLICIT_DEF + %1:fprb(s64) = G_FADD %0, %0 + $f10_d = COPY %1(s64) +... +--- +name: implicit_def_copy_fpr +legalized: true +regBankSelected: true +body: | + bb.0: + ; RV64D-LABEL: name: implicit_def_copy_fpr + ; RV64D: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF + ; RV64D-NEXT: $f10_d = COPY [[DEF]] + %0:fprb(s64) = G_IMPLICIT_DEF + %1:fprb(s64) = COPY %0(s64) + $f10_d = COPY %1(s64) +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir new file mode 100644 index 0000000..a8ec01e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir @@ -0,0 +1,46 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: ptrtoint_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ptrtoint_s32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_PTRTOINT %0(p0) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: inttoptr_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: inttoptr_s32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(p0) = G_INTTOPTR %0(s32) + $x10 = COPY %1(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv64.mir new file mode 100644 index 0000000..7cf6b9a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv64.mir @@ -0,0 +1,46 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: ptrtoint_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ptrtoint_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_PTRTOINT %0(p0) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: inttoptr_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: inttoptr_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = G_INTTOPTR %0(s64) + $x10 = COPY %1(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv32.mir new file mode 100644 index 0000000..b8ff04a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv32.mir @@ -0,0 +1,82 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select -verify-machineinstrs %s -o - | \ +# RUN: FileCheck %s + +--- +name: is_fpclass_f16 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: is_fpclass_f16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCLASS_H:%[0-9]+]]:gpr = FCLASS_H [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_H]], 152 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %3:gprb(s32) = G_CONSTANT i32 152 + %4:gprb(s32) = G_CONSTANT i32 0 + %5:gprb(s32) = G_FCLASS %0(s16) + %6:gprb(s32) = G_AND %5, %3 + %7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f16_onehot +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: is_fpclass_f16_onehot + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCLASS_H:%[0-9]+]]:gpr = FCLASS_H [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_H]], 256 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %3:gprb(s32) = G_CONSTANT i32 256 + %4:gprb(s32) = G_CONSTANT i32 0 + %5:gprb(s32) = G_FCLASS %0(s16) + %6:gprb(s32) = G_AND %5, %3 + %7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f16_one +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: is_fpclass_f16_one + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCLASS_H:%[0-9]+]]:gpr = FCLASS_H [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_H]], 1 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %3:gprb(s32) = G_CONSTANT i32 1 + %4:gprb(s32) = G_CONSTANT i32 0 + %5:gprb(s32) = G_FCLASS %0(s16) + %6:gprb(s32) = G_AND %5, %3 + %7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv64.mir new file mode 100644 index 0000000..3860657 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv64.mir @@ -0,0 +1,82 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select -verify-machineinstrs %s -o - | \ +# RUN: FileCheck %s + +--- +name: is_fpclass_f16 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: is_fpclass_f16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCLASS_H:%[0-9]+]]:gpr = FCLASS_H [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_H]], 152 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %3:gprb(s64) = G_CONSTANT i64 152 + %4:gprb(s64) = G_CONSTANT i64 0 + %5:gprb(s64) = G_FCLASS %0(s16) + %6:gprb(s64) = G_AND %5, %3 + %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f16_onehot +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: is_fpclass_f16_onehot + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCLASS_H:%[0-9]+]]:gpr = FCLASS_H [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_H]], 256 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %3:gprb(s64) = G_CONSTANT i64 256 + %4:gprb(s64) = G_CONSTANT i64 0 + %5:gprb(s64) = G_FCLASS %0(s16) + %6:gprb(s64) = G_AND %5, %3 + %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f16_one +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: is_fpclass_f16_one + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h + ; CHECK-NEXT: [[FCLASS_H:%[0-9]+]]:gpr = FCLASS_H [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_H]], 1 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s16) = COPY $f10_h + %3:gprb(s64) = G_CONSTANT i64 1 + %4:gprb(s64) = G_CONSTANT i64 0 + %5:gprb(s64) = G_FCLASS %0(s16) + %6:gprb(s64) = G_AND %5, %3 + %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-rv32.mir new file mode 100644 index 0000000..8c8c780 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-rv32.mir @@ -0,0 +1,160 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select -verify-machineinstrs %s -o - | \ +# RUN: FileCheck %s + +--- +name: is_fpclass_f32 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: is_fpclass_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCLASS_S:%[0-9]+]]:gpr = FCLASS_S [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_S]], 152 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %3:gprb(s32) = G_CONSTANT i32 152 + %4:gprb(s32) = G_CONSTANT i32 0 + %5:gprb(s32) = G_FCLASS %0(s32) + %6:gprb(s32) = G_AND %5, %3 + %7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f32_onehot +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: is_fpclass_f32_onehot + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCLASS_S:%[0-9]+]]:gpr = FCLASS_S [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_S]], 256 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %3:gprb(s32) = G_CONSTANT i32 256 + %4:gprb(s32) = G_CONSTANT i32 0 + %5:gprb(s32) = G_FCLASS %0(s32) + %6:gprb(s32) = G_AND %5, %3 + %7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f32_one +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: is_fpclass_f32_one + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCLASS_S:%[0-9]+]]:gpr = FCLASS_S [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_S]], 1 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %3:gprb(s32) = G_CONSTANT i32 1 + %4:gprb(s32) = G_CONSTANT i32 0 + %5:gprb(s32) = G_FCLASS %0(s32) + %6:gprb(s32) = G_AND %5, %3 + %7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f64 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: is_fpclass_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCLASS_D:%[0-9]+]]:gpr = FCLASS_D [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_D]], 152 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %3:gprb(s32) = G_CONSTANT i32 152 + %4:gprb(s32) = G_CONSTANT i32 0 + %5:gprb(s32) = G_FCLASS %0(s64) + %6:gprb(s32) = G_AND %5, %3 + %7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f64_onehot +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: is_fpclass_f64_onehot + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCLASS_D:%[0-9]+]]:gpr = FCLASS_D [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_D]], 256 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %3:gprb(s32) = G_CONSTANT i32 256 + %4:gprb(s32) = G_CONSTANT i32 0 + %5:gprb(s32) = G_FCLASS %0(s64) + %6:gprb(s32) = G_AND %5, %3 + %7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f64_one +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: is_fpclass_f64_one + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCLASS_D:%[0-9]+]]:gpr = FCLASS_D [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_D]], 1 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %3:gprb(s32) = G_CONSTANT i32 1 + %4:gprb(s32) = G_CONSTANT i32 0 + %5:gprb(s32) = G_FCLASS %0(s64) + %6:gprb(s32) = G_AND %5, %3 + %7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-rv64.mir new file mode 100644 index 0000000..3e5a8a8 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-rv64.mir @@ -0,0 +1,160 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select -verify-machineinstrs %s -o - | \ +# RUN: FileCheck %s + +--- +name: is_fpclass_f32 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: is_fpclass_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCLASS_S:%[0-9]+]]:gpr = FCLASS_S [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_S]], 152 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %3:gprb(s64) = G_CONSTANT i64 152 + %4:gprb(s64) = G_CONSTANT i64 0 + %5:gprb(s64) = G_FCLASS %0(s32) + %6:gprb(s64) = G_AND %5, %3 + %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f32_onehot +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: is_fpclass_f32_onehot + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCLASS_S:%[0-9]+]]:gpr = FCLASS_S [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_S]], 256 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %3:gprb(s64) = G_CONSTANT i64 256 + %4:gprb(s64) = G_CONSTANT i64 0 + %5:gprb(s64) = G_FCLASS %0(s32) + %6:gprb(s64) = G_AND %5, %3 + %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f32_one +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: is_fpclass_f32_one + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[FCLASS_S:%[0-9]+]]:gpr = FCLASS_S [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_S]], 1 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s32) = COPY $f10_f + %3:gprb(s64) = G_CONSTANT i64 1 + %4:gprb(s64) = G_CONSTANT i64 0 + %5:gprb(s64) = G_FCLASS %0(s32) + %6:gprb(s64) = G_AND %5, %3 + %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f64 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: is_fpclass_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCLASS_D:%[0-9]+]]:gpr = FCLASS_D [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_D]], 152 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %3:gprb(s64) = G_CONSTANT i64 152 + %4:gprb(s64) = G_CONSTANT i64 0 + %5:gprb(s64) = G_FCLASS %0(s64) + %6:gprb(s64) = G_AND %5, %3 + %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f64_onehot +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: is_fpclass_f64_onehot + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCLASS_D:%[0-9]+]]:gpr = FCLASS_D [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_D]], 256 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %3:gprb(s64) = G_CONSTANT i64 256 + %4:gprb(s64) = G_CONSTANT i64 0 + %5:gprb(s64) = G_FCLASS %0(s64) + %6:gprb(s64) = G_AND %5, %3 + %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f64_one +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: is_fpclass_f64_one + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[FCLASS_D:%[0-9]+]]:gpr = FCLASS_D [[COPY]] + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_D]], 1 + ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLTU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %3:gprb(s64) = G_CONSTANT i64 1 + %4:gprb(s64) = G_CONSTANT i64 0 + %5:gprb(s64) = G_FCLASS %0(s64) + %6:gprb(s64) = G_AND %5, %3 + %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv32.mir new file mode 100644 index 0000000..fbcf124 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv32.mir @@ -0,0 +1,48 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: sitofp_s16_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s16_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FCVT_H_W:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_W [[COPY]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_W]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:gprb(s32) = COPY $x10 + %1:fprb(s16) = G_SITOFP %0(s32) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s16_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s16_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FCVT_H_WU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_WU [[COPY]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_WU]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:gprb(s32) = COPY $x10 + %1:fprb(s16) = G_UITOFP %0(s32) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir new file mode 100644 index 0000000..b813a79 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir @@ -0,0 +1,48 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: sitofp_s64_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FCVT_H_L:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_L [[COPY]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_L]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:gprb(s64) = COPY $x10 + %1:fprb(s16) = G_SITOFP %0(s64) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s64_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FCVT_H_LU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_LU [[COPY]], 7 + ; CHECK-NEXT: $f10_h = COPY [[FCVT_H_LU]] + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:gprb(s64) = COPY $x10 + %1:fprb(s16) = G_UITOFP %0(s64) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv32.mir new file mode 100644 index 0000000..7200fe1 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv32.mir @@ -0,0 +1,92 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: sitofp_s32_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FCVT_S_W:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_W [[COPY]], 7 + ; CHECK-NEXT: $f10_f = COPY [[FCVT_S_W]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:gprb(s32) = COPY $x10 + %1:fprb(s32) = G_SITOFP %0(s32) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FCVT_S_WU:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_WU [[COPY]], 7 + ; CHECK-NEXT: $f10_f = COPY [[FCVT_S_WU]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:gprb(s32) = COPY $x10 + %1:fprb(s32) = G_UITOFP %0(s32) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s64_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W [[COPY]], 0 + ; CHECK-NEXT: $f10_d = COPY [[FCVT_D_W]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:gprb(s32) = COPY $x10 + %1:fprb(s64) = G_SITOFP %0(s32) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FCVT_D_WU:%[0-9]+]]:fpr64 = FCVT_D_WU [[COPY]], 0 + ; CHECK-NEXT: $f10_d = COPY [[FCVT_D_WU]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:gprb(s32) = COPY $x10 + %1:fprb(s64) = G_UITOFP %0(s32) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir new file mode 100644 index 0000000..f99a15a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir @@ -0,0 +1,92 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: sitofp_s32_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FCVT_S_L:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_L [[COPY]], 7 + ; CHECK-NEXT: $f10_f = COPY [[FCVT_S_L]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:gprb(s64) = COPY $x10 + %1:fprb(s32) = G_SITOFP %0(s64) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FCVT_S_LU:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_LU [[COPY]], 7 + ; CHECK-NEXT: $f10_f = COPY [[FCVT_S_LU]] + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:gprb(s64) = COPY $x10 + %1:fprb(s32) = G_UITOFP %0(s64) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s64_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FCVT_D_L:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_L [[COPY]], 7 + ; CHECK-NEXT: $f10_d = COPY [[FCVT_D_L]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:gprb(s64) = COPY $x10 + %1:fprb(s64) = G_SITOFP %0(s64) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FCVT_D_LU:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_LU [[COPY]], 7 + ; CHECK-NEXT: $f10_d = COPY [[FCVT_D_LU]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:gprb(s64) = COPY $x10 + %1:fprb(s64) = G_UITOFP %0(s64) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir new file mode 100644 index 0000000..be4416e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir @@ -0,0 +1,294 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \ +# RUN: -disable-gisel-legality-check | FileCheck %s + +--- +name: load_i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[LBU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_LOAD %0(p0) :: (load (s8)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: load_i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[LH]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_LOAD %0(p0) :: (load (s16)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: load_i8_i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_i8_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[LBU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s16) = G_LOAD %0(p0) :: (load (s8)) + %2:gprb(s32) = G_ANYEXT %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: load_i16_i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_i16_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[LH]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s16) = G_LOAD %0(p0) :: (load (s16)) + %2:gprb(s32) = G_ANYEXT %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: load_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: $x10 = COPY [[LW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_LOAD %0(p0) :: (load (s32)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: zextload_i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[LBU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s8)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: zextload_i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LHU:%[0-9]+]]:gpr = LHU [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[LHU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s16)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: sextload_i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LB:%[0-9]+]]:gpr = LB [[COPY]], 0 :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[LB]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s8)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: sextload_i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[LH]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s16)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: load_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (p0)) + ; CHECK-NEXT: $x10 = COPY [[LW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_LOAD %0(p0) :: (load (p0)) + $x10 = COPY %1(p0) + PseudoRET implicit $x10 + +... +--- +name: load_fi_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +stack: + - { id: 0, offset: 0, size: 4, alignment: 4 } + +body: | + bb.0: + ; CHECK-LABEL: name: load_fi_i32 + ; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0, 0 :: (load (s32)) + ; CHECK-NEXT: $x10 = COPY [[LW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = G_FRAME_INDEX %stack.0 + %1:gprb(s32) = G_LOAD %0(p0) :: (load (s32)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: load_fi_gep_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +stack: + - { id: 0, offset: 0, size: 8, alignment: 4 } + +body: | + bb.0: + ; CHECK-LABEL: name: load_fi_gep_i32 + ; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0, 4 :: (load (s32)) + ; CHECK-NEXT: $x10 = COPY [[LW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = G_FRAME_INDEX %stack.0 + %1:gprb(s32) = G_CONSTANT i32 4 + %2:gprb(p0) = G_PTR_ADD %0(p0), %1(s32) + %3:gprb(s32) = G_LOAD %2(p0) :: (load (s32)) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: load_gep_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_gep_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: $x10 = COPY [[LW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 4 + %2:gprb(p0) = G_PTR_ADD %0(p0), %1(s32) + %3:gprb(s32) = G_LOAD %2(p0) :: (load (s32)) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir new file mode 100644 index 0000000..b78f78f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir @@ -0,0 +1,426 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \ +# RUN: -disable-gisel-legality-check | FileCheck %s + +--- +name: load_i8_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_i8_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[LBU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_LOAD %0(p0) :: (load (s8)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i16_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_i16_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[LH]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_LOAD %0(p0) :: (load (s16)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i8_i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_i8_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[LBU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s16) = G_LOAD %0(p0) :: (load (s8)) + %2:gprb(s64) = G_ANYEXT %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i16_i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_i16_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[LH]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s16) = G_LOAD %0(p0) :: (load (s16)) + %2:gprb(s64) = G_ANYEXT %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i32_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_i32_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: $x10 = COPY [[LW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_LOAD %0(p0) :: (load (s32)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i64_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_i64_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LD:%[0-9]+]]:gpr = LD [[COPY]], 0 :: (load (s64)) + ; CHECK-NEXT: $x10 = COPY [[LD]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_LOAD %0(p0) :: (load (s64)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: load_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_p0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LD:%[0-9]+]]:gpr = LD [[COPY]], 0 :: (load (p0)) + ; CHECK-NEXT: $x10 = COPY [[LD]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = G_LOAD %0(p0) :: (load (p0)) + $x10 = COPY %1(p0) + PseudoRET implicit $x10 + +... +--- +name: zextload_i8_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i8_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[LBU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_ZEXTLOAD %0(p0) :: (load (s8)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: zextload_i16_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i16_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LHU:%[0-9]+]]:gpr = LHU [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[LHU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_ZEXTLOAD %0(p0) :: (load (s16)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: zextload_i32_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i32_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LWU:%[0-9]+]]:gpr = LWU [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: $x10 = COPY [[LWU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_ZEXTLOAD %0(p0) :: (load (s32)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i8_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i8_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LB:%[0-9]+]]:gpr = LB [[COPY]], 0 :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[LB]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_SEXTLOAD %0(p0) :: (load (s8)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i16_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i16_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[LH]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_SEXTLOAD %0(p0) :: (load (s16)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i32_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i32_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: $x10 = COPY [[LW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_SEXTLOAD %0(p0) :: (load (s32)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i8_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: load_i8_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[LBU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %9:gprb(s32) = G_LOAD %0(p0) :: (load (s8)) + %5:gprb(s64) = G_ANYEXT %9(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i16_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: load_i16_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[LH]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %9:gprb(s32) = G_LOAD %0(p0) :: (load (s16)) + %5:gprb(s64) = G_ANYEXT %9(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i32_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: load_i32_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: $x10 = COPY [[LW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %9:gprb(s32) = G_LOAD %0(p0) :: (load (s32)) + %5:gprb(s64) = G_ANYEXT %9(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: load_fi_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +stack: + - { id: 0, offset: 0, size: 8, alignment: 8 } + +body: | + bb.0: + ; CHECK-LABEL: name: load_fi_i64 + ; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0, 0 :: (load (s64)) + ; CHECK-NEXT: $x10 = COPY [[LD]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = G_FRAME_INDEX %stack.0 + %1:gprb(s64) = G_LOAD %0(p0) :: (load (s64)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: load_fi_gep_i64_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +stack: + - { id: 0, offset: 0, size: 16, alignment: 8 } + +body: | + bb.0: + ; CHECK-LABEL: name: load_fi_gep_i64_i64 + ; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0, 8 :: (load (s64)) + ; CHECK-NEXT: $x10 = COPY [[LD]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = G_FRAME_INDEX %stack.0 + %1:gprb(s64) = G_CONSTANT i64 8 + %2:gprb(p0) = G_PTR_ADD %0(p0), %1(s64) + %3:gprb(s64) = G_LOAD %2(p0) :: (load (s64)) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: load_gep_i64_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: load_gep_i64_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LD:%[0-9]+]]:gpr = LD [[COPY]], 8 :: (load (s64)) + ; CHECK-NEXT: $x10 = COPY [[LD]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 8 + %2:gprb(p0) = G_PTR_ADD %0(p0), %1(s64) + %3:gprb(s64) = G_LOAD %2(p0) :: (load (s64)) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/merge-unmerge-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/merge-unmerge-rv32.mir new file mode 100644 index 0000000..11d3bf6 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/merge-unmerge-rv32.mir @@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: merge_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: merge_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY]], [[COPY]] + ; CHECK-NEXT: $f10_d = COPY [[BuildPairF64Pseudo]] + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:gprb(s32) = COPY $x10 + %1:fprb(s64) = G_MERGE_VALUES %0(s32), %0(s32) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d +... +--- +name: unmerge_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $f10_d + ; CHECK-LABEL: name: unmerge_i32 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d + ; CHECK-NEXT: [[SplitF64Pseudo:%[0-9]+]]:gpr, [[SplitF64Pseudo1:%[0-9]+]]:gpr = SplitF64Pseudo [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[SplitF64Pseudo]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:fprb(s64) = COPY $f10_d + %1:gprb(s32), %2:gprb(s32) = G_UNMERGE_VALUES %0(s64) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv32.mir new file mode 100644 index 0000000..891a34f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv32.mir @@ -0,0 +1,81 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s + +--- +name: smax_i32 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: smax_i32 + ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[MAX:%[0-9]+]]:gpr = MAX [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[MAX]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_SMAX %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: smin_i32 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: smin_i32 + ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[MIN:%[0-9]+]]:gpr = MIN [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[MIN]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_SMIN %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: umax_i32 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: umax_i32 + ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[MAXU:%[0-9]+]]:gpr = MAXU [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[MAXU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_UMAX %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: umin_i32 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: umin_i32 + ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[MINU:%[0-9]+]]:gpr = MINU [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[MINU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_UMIN %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv64.mir new file mode 100644 index 0000000..16f8f11 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv64.mir @@ -0,0 +1,81 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV64I %s + +--- +name: smax_i64 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: smax_i64 + ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[MAX:%[0-9]+]]:gpr = MAX [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[MAX]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SMAX %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: smin_i64 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: smin_i64 + ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[MIN:%[0-9]+]]:gpr = MIN [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[MIN]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SMIN %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: umax_i64 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: umax_i64 + ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[MAXU:%[0-9]+]]:gpr = MAXU [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[MAXU]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_UMAX %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: umin_i64 +legalized: true +regBankSelected: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: umin_i64 + ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[MINU:%[0-9]+]]:gpr = MINU [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[MINU]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_UMIN %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir new file mode 100644 index 0000000..459511e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir @@ -0,0 +1,88 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s + +--- +name: phi_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + ; RV32I-LABEL: name: phi_i32 + ; RV32I: bb.0: + ; RV32I-NEXT: liveins: $x10, $x11, $x12 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1 + ; RV32I-NEXT: BNE [[ANDI]], $x0, %bb.2 + ; RV32I-NEXT: PseudoBR %bb.1 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.1: + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.2: + ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.1, [[COPY1]], %bb.0 + ; RV32I-NEXT: $x10 = COPY [[PHI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x12 + + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = COPY $x12 + %3:gprb(s32) = G_CONSTANT i32 1 + %4:gprb(s32) = G_AND %0, %3 + G_BRCOND %4(s32), %bb.2 + G_BR %bb.1 + + bb.1: + + bb.2: + %5:gprb(s32) = G_PHI %2(s32), %bb.1, %1(s32), %bb.0 + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: phi_ptr +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + ; RV32I-LABEL: name: phi_ptr + ; RV32I: bb.0.entry: + ; RV32I-NEXT: liveins: $x10, $x11, $x12 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1 + ; RV32I-NEXT: BNE [[ANDI]], $x0, %bb.2 + ; RV32I-NEXT: PseudoBR %bb.1 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.1: + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.2: + ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.1, [[COPY1]], %bb.0 + ; RV32I-NEXT: $x10 = COPY [[PHI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + bb.0.entry: + liveins: $x10, $x11, $x12 + + %0:gprb(s32) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(p0) = COPY $x12 + %3:gprb(s32) = G_CONSTANT i32 1 + %4:gprb(s32) = G_AND %0, %3 + G_BRCOND %4(s32), %bb.2 + G_BR %bb.1 + + bb.1: + + bb.2: + %5:gprb(p0) = G_PHI %2(p0), %bb.1, %1(p0), %bb.0 + $x10 = COPY %5(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir new file mode 100644 index 0000000..8512af3 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir @@ -0,0 +1,88 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV64I %s + +--- +name: phi_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + ; RV64I-LABEL: name: phi_i64 + ; RV64I: bb.0: + ; RV64I-NEXT: liveins: $x10, $x11, $x12 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1 + ; RV64I-NEXT: BNE [[ANDI]], $x0, %bb.2 + ; RV64I-NEXT: PseudoBR %bb.1 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.1: + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.2: + ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.1, [[COPY1]], %bb.0 + ; RV64I-NEXT: $x10 = COPY [[PHI]] + ; RV64I-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x12 + + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = COPY $x12 + %3:gprb(s64) = G_CONSTANT i64 1 + %4:gprb(s64) = G_AND %0, %3 + G_BRCOND %4(s64), %bb.2 + G_BR %bb.1 + + bb.1: + + bb.2: + %5:gprb(s64) = G_PHI %2(s64), %bb.1, %1(s64), %bb.0 + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: phi_ptr +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + ; RV64I-LABEL: name: phi_ptr + ; RV64I: bb.0: + ; RV64I-NEXT: liveins: $x10, $x11, $x12 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1 + ; RV64I-NEXT: BNE [[ANDI]], $x0, %bb.2 + ; RV64I-NEXT: PseudoBR %bb.1 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.1: + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.2: + ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.1, [[COPY1]], %bb.0 + ; RV64I-NEXT: $x10 = COPY [[PHI]] + ; RV64I-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x12 + + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(p0) = COPY $x12 + %3:gprb(s64) = G_CONSTANT i64 1 + %4:gprb(s64) = G_AND %0, %3 + G_BRCOND %4(s64), %bb.2 + G_BR %bb.1 + + bb.1: + + bb.2: + %5:gprb(p0) = G_PHI %2(p0), %bb.1, %1(p0), %bb.0 + $x10 = COPY %5(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir new file mode 100644 index 0000000..a96f55f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s +--- +name: add_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: add_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(p0) = G_PTR_ADD %0, %1 + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... +--- +name: addi_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: addi_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 20 + ; CHECK-NEXT: $x10 = COPY [[ADDI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 20 + %2:gprb(p0) = G_PTR_ADD %0, %1 + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv64.mir new file mode 100644 index 0000000..6346d91 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv64.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s +--- +name: add_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: add_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(p0) = G_PTR_ADD %0, %1 + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... +--- +name: addi_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: addi_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 20 + ; CHECK-NEXT: $x10 = COPY [[ADDI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 20 + %2:gprb(p0) = G_PTR_ADD %0, %1 + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv32.mir new file mode 100644 index 0000000..f92b689 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv32.mir @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: ptrmask_p0_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; CHECK-LABEL: name: ptrmask_p0_s32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[AND]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(p0) = G_PTRMASK %0(p0), %1(s32) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 +... + +--- +name: ptrmask_p0_const_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: ptrmask_p0_const_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 10 + ; CHECK-NEXT: $x10 = COPY [[ANDI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(p0) = G_PTRMASK %0(p0), %1(s32) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv64.mir new file mode 100644 index 0000000..5dd943d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptrmask-rv64.mir @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: ptrmask_p0_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; CHECK-LABEL: name: ptrmask_p0_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[AND]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(p0) = G_PTRMASK %0(p0), %1(s64) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 +... + +--- +name: ptrmask_p0_const_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: ptrmask_p0_const_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 10 + ; CHECK-NEXT: $x10 = COPY [[ANDI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(p0) = G_PTRMASK %0(p0), %1(s64) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv32.mir new file mode 100644 index 0000000..5b0e52d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv32.mir @@ -0,0 +1,96 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: rotl_i32 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotl_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ROL:%[0-9]+]]:gpr = ROL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ROL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ROTL %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: rotr_i32 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotr_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ROR:%[0-9]+]]:gpr = ROR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ROR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ROTR %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: rotl_imm_i32 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: rotl_imm_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 27 + ; CHECK-NEXT: $x10 = COPY [[RORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 5 + %2:gprb(s32) = G_ROTL %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: rotr_imm_i32 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: rotr_imm_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 5 + ; CHECK-NEXT: $x10 = COPY [[RORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 5 + %2:gprb(s32) = G_ROTR %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir new file mode 100644 index 0000000..edf7ef2 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir @@ -0,0 +1,192 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: rotl_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotl_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ROLW:%[0-9]+]]:gpr = ROLW [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ROLW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ROLW %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: rotl_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotl_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ROL:%[0-9]+]]:gpr = ROL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ROL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ROTL %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: rotr_i32 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotr_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[RORW:%[0-9]+]]:gpr = RORW [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[RORW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_RORW %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: rotr_i64 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotr_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ROR:%[0-9]+]]:gpr = ROR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ROR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ROTR %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: rotl_imm_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: rotl_imm_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[RORIW:%[0-9]+]]:gpr = RORIW [[COPY]], 17 + ; CHECK-NEXT: $x10 = COPY [[RORIW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 15 + %2:gprb(s64) = G_ROLW %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: rotl_imm_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: rotl_imm_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 31 + ; CHECK-NEXT: $x10 = COPY [[RORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 33 + %2:gprb(s64) = G_ROTL %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: rotr_imm_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: rotr_imm_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[RORIW:%[0-9]+]]:gpr = RORIW [[COPY]], 15 + ; CHECK-NEXT: $x10 = COPY [[RORIW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 15 + %2:gprb(s64) = G_RORW %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: rotr_imm_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: rotr_imm_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 33 + ; CHECK-NEXT: $x10 = COPY [[RORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 33 + %2:gprb(s64) = G_ROTR %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/add.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/add.mir new file mode 100644 index 0000000..e8af68f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/add.mir @@ -0,0 +1,774 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s +--- +name: test_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv1i8 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_MF8_:%[0-9]+]]:vr = PseudoVADD_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF8_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv1i8 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_MF8_:%[0-9]+]]:vr = PseudoVADD_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF8_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv2i8 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_MF4_:%[0-9]+]]:vr = PseudoVADD_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF4_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv2i8 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_MF4_:%[0-9]+]]:vr = PseudoVADD_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF4_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv4i8 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv4i8 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv8i8 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv8i8 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; RV32I-LABEL: name: test_nxv16i8 + ; RV32I: liveins: $v8m2, $v10m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: test_nxv16i8 + ; RV64I: liveins: $v8m2, $v10m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8m2 + %1:vrb() = COPY $v10m2 + %2:vrb() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; RV32I-LABEL: name: test_nxv32i8 + ; RV32I: liveins: $v8m4, $v12m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: test_nxv32i8 + ; RV64I: liveins: $v8m4, $v12m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m4 + %1:vrb() = COPY $v12m4 + %2:vrb() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; RV32I-LABEL: name: test_nxv64i8 + ; RV32I: liveins: $v8m8, $v16m8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: test_nxv64i8 + ; RV64I: liveins: $v8m8, $v16m8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m8 + %1:vrb() = COPY $v16m8 + %2:vrb() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv1i16 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_MF4_:%[0-9]+]]:vr = PseudoVADD_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF4_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv1i16 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_MF4_:%[0-9]+]]:vr = PseudoVADD_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF4_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv2i16 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv2i16 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv4i16 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv4i16 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; RV32I-LABEL: name: test_nxv8i16 + ; RV32I: liveins: $v8m2, $v10m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: test_nxv8i16 + ; RV64I: liveins: $v8m2, $v10m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8m2 + %1:vrb() = COPY $v10m2 + %2:vrb() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; RV32I-LABEL: name: test_nxv16i16 + ; RV32I: liveins: $v8m4, $v12m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: test_nxv16i16 + ; RV64I: liveins: $v8m4, $v12m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m4 + %1:vrb() = COPY $v12m4 + %2:vrb() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; RV32I-LABEL: name: test_nxv32i16 + ; RV32I: liveins: $v8m8, $v16m8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: test_nxv32i16 + ; RV64I: liveins: $v8m8, $v16m8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m8 + %1:vrb() = COPY $v16m8 + %2:vrb() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv1i32 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv1i32 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv2i32 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv2i32 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; RV32I-LABEL: name: test_nxv4i32 + ; RV32I: liveins: $v8m2, $v10m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: test_nxv4i32 + ; RV64I: liveins: $v8m2, $v10m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8m2 + %1:vrb() = COPY $v10m2 + %2:vrb() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; RV32I-LABEL: name: test_nxv8i32 + ; RV32I: liveins: $v8m4, $v12m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: test_nxv8i32 + ; RV64I: liveins: $v8m4, $v12m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m4 + %1:vrb() = COPY $v12m4 + %2:vrb() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; RV32I-LABEL: name: test_nxv16i32 + ; RV32I: liveins: $v8m8, $v16m8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: test_nxv16i32 + ; RV64I: liveins: $v8m8, $v16m8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m8 + %1:vrb() = COPY $v16m8 + %2:vrb() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv1i64 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv1i64 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; RV32I-LABEL: name: test_nxv2i64 + ; RV32I: liveins: $v8m2, $v10m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: test_nxv2i64 + ; RV64I: liveins: $v8m2, $v10m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8m2 + %1:vrb() = COPY $v10m2 + %2:vrb() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv4i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; RV32I-LABEL: name: test_nxv4i64 + ; RV32I: liveins: $v8m4, $v12m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: test_nxv4i64 + ; RV64I: liveins: $v8m4, $v12m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m4 + %1:vrb() = COPY $v12m4 + %2:vrb() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv8i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; RV32I-LABEL: name: test_nxv8i64 + ; RV32I: liveins: $v8m8, $v16m8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: test_nxv8i64 + ; RV64I: liveins: $v8m8, $v16m8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m8 + %1:vrb() = COPY $v16m8 + %2:vrb() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir new file mode 100644 index 0000000..c1adfec --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir @@ -0,0 +1,902 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s + +--- +name: anyext_nxv1i16_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i16_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i16_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv1i32_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i32_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i32_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv1i64_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i64_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i64_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i16_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i16_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv2i16_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i32_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i32_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv2i32_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i64_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i64_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv2i64_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i16_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i16_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv4i16_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv4i32_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i32_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv4i32_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i64_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i64_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv4i64_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i16_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i16_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv8i16_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv8i32_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i32_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv8i32_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i64_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i64_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv8i64_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv16i16_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: anyext_nxv16i16_nxv16i8 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv16i16_nxv16i8 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_ANYEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv16i32_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: anyext_nxv16i32_nxv16i8 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv16i32_nxv16i8 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_ANYEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv32i16_nxv32i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4 + + ; RV32I-LABEL: name: anyext_nxv32i16_nxv32i8 + ; RV32I: liveins: $v8m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv32i16_nxv32i8 + ; RV64I: liveins: $v8m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m4 + %1:vrb() = G_ANYEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv1i32_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i32_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i32_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv1i64_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i64_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i64_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i32_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i32_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv2i32_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i64_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i64_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv2i64_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i32_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i32_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv4i32_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i64_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i64_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv4i64_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i32_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: anyext_nxv8i32_nxv8i16 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv8i32_nxv8i16 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_ANYEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i64_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: anyext_nxv8i64_nxv8i16 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv8i64_nxv8i16 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_ANYEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv16i32_nxv16i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4 + + ; RV32I-LABEL: name: anyext_nxv16i32_nxv16i16 + ; RV32I: liveins: $v8m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv16i32_nxv16i16 + ; RV64I: liveins: $v8m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m4 + %1:vrb() = G_ANYEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv1i64_nxv1i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i64_nxv1i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i64_nxv1i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i64_nxv2i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i64_nxv2i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv2i64_nxv2i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_ANYEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i64_nxv4i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: anyext_nxv4i64_nxv4i32 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv4i64_nxv4i32 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_ANYEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i64_nxv8i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4 + + ; RV32I-LABEL: name: anyext_nxv8i64_nxv8i32 + ; RV32I: liveins: $v8m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv8i64_nxv8i32 + ; RV64I: liveins: $v8m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m4 + %1:vrb() = G_ANYEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir new file mode 100644 index 0000000..b6d8361 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir @@ -0,0 +1,534 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s + +# Don't test i1 element types here since they have been widened to i8 in legalization + +--- +name: icmp_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i8 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLTU_VV_MF8_:%[0-9]+]]:vr = PseudoVMSLTU_VV_MF8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_MF8_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i8 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLTU_VV_MF8_:%[0-9]+]]:vr = PseudoVMSLTU_VV_MF8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_MF8_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(ult), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i8 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLT_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLT_VV_MF4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLT_VV_MF4_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i8 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLT_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLT_VV_MF4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLT_VV_MF4_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(slt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i8 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLEU_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLEU_VV_MF2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLEU_VV_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i8 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLEU_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLEU_VV_MF2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLEU_VV_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(uge), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i8 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLE_VV_M1_:%[0-9]+]]:vr = PseudoVMSLE_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i8 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLE_VV_M1_:%[0-9]+]]:vr = PseudoVMSLE_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(sge), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv16i8 + ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv16i8 + ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(ugt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv32i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv32i8 + ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv32i8 + ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv64i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv64i8 + ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv64i8 + ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(ule), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i16 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLE_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF4_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i16 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLE_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF4_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(sle), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i16 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSNE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSNE_VV_MF2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSNE_VV_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i16 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSNE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSNE_VV_MF2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSNE_VV_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(ne), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i16 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i16 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(eq), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i16 + ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i16 + ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(ult), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv16i16 + ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv16i16 + ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(slt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv32i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv32i16 + ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv32i16 + ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(uge), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i32 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i32 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(sge), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i32 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLTU_VV_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i32 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLTU_VV_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(ugt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i32 + ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i32 + ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i32 + ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i32 + ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(ule), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv16i32 + ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLE_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv16i32 + ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLE_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(sle), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i64 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i64 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(eq), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i64 + ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSNE_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i64 + ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSNE_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(ne), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i64 + ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i64 + ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(ult), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i64 + ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i64 + ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_ICMP intpred(ult), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir new file mode 100644 index 0000000..95c56c3 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir @@ -0,0 +1,76 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: negative_vl +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: negative_vl + ; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2 + ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[ADDI]] /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s32) = G_CONSTANT i32 -2 + %1:vrb() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 +... +--- +name: nonconst_vl +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: nonconst_vl + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[COPY]] /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s32) = COPY $x10 + %1:vrb() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 +... + +--- +name: nonzero_vl +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: nonzero_vl + ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s32) = G_CONSTANT i32 1 + %1:vrb() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 +... + +--- +name: zero_vl +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: zero_vl + ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 0 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s32) = G_CONSTANT i32 0 + %1:vrb() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir new file mode 100644 index 0000000..78b7439 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir @@ -0,0 +1,76 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: negative_vl +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: negative_vl + ; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2 + ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[ADDI]] /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s64) = G_CONSTANT i64 -2 + %1:vrb() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 +... +--- +name: nonconst_vl +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: nonconst_vl + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[COPY]] /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s64) = COPY $x10 + %1:vrb() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 +... + +--- +name: nonzero_vl +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: nonzero_vl + ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s64) = G_CONSTANT i64 1 + %1:vrb() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 +... + +--- +name: zero_vl +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: zero_vl + ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 0 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s64) = G_CONSTANT i64 0 + %1:vrb() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir new file mode 100644 index 0000000..35e8962 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir @@ -0,0 +1,323 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s + +--- +name: select_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: select_nxv1i8 + ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: select_nxv1i8 + ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_IMPLICIT_DEF + %2:vrb() = G_SELECT %0(), %1, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: select_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: select_nxv4i8 + ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: select_nxv4i8 + ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_IMPLICIT_DEF + %2:vrb() = G_SELECT %0(), %1, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: select_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: select_nxv16i8 + ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]] + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: select_nxv16i8 + ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ + ; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]] + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_IMPLICIT_DEF + %2:vrb() = G_SELECT %0(), %1, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: select_nxv64i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: select_nxv64i8 + ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: select_nxv64i8 + ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_IMPLICIT_DEF + %2:vrb() = G_SELECT %0(), %1, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: select_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: select_nxv2i16 + ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: select_nxv2i16 + ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_IMPLICIT_DEF + %2:vrb() = G_SELECT %0(), %1, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: select_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: select_nxv8i16 + ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]] + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: select_nxv8i16 + ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ + ; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]] + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_IMPLICIT_DEF + %2:vrb() = G_SELECT %0(), %1, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: select_nxv32i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: select_nxv32i16 + ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: select_nxv32i16 + ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_IMPLICIT_DEF + %2:vrb() = G_SELECT %0(), %1, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: select_nxv2i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: select_nxv2i32 + ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]] + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: select_nxv2i32 + ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]] + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_IMPLICIT_DEF + %2:vrb() = G_SELECT %0(), %1, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: select_nxv8i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: select_nxv8i32 + ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]] + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: select_nxv8i32 + ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ + ; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]] + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_IMPLICIT_DEF + %2:vrb() = G_SELECT %0(), %1, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: select_nxv1i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: select_nxv1i64 + ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]] + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: select_nxv1i64 + ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]] + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_IMPLICIT_DEF + %2:vrb() = G_SELECT %0(), %1, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: select_nxv4i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: select_nxv4i64 + ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]] + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: select_nxv4i64 + ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]] + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = G_IMPLICIT_DEF + %1:vrb() = G_IMPLICIT_DEF + %2:vrb() = G_SELECT %0(), %1, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir new file mode 100644 index 0000000..b5b22ec --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir @@ -0,0 +1,900 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s + +--- +name: sext_nxv1i16_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i16_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i16_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv1i32_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i32_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i32_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv1i64_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i64_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF8_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i64_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF8_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i16_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i16_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv2i16_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i32_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i32_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv2i32_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i64_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i64_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF8_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv2i64_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF8_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i16_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i16_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv4i16_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv4i32_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i32_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv4i32_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i64_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i64_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF8_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv4i64_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF8_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i16_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i16_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv8i16_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv8i32_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i32_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv8i32_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i64_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i64_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF8_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv8i64_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF8_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv16i16_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: sext_nxv16i16_nxv16i8 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv16i16_nxv16i8 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_SEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv16i32_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: sext_nxv16i32_nxv16i8 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv16i32_nxv16i8 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_SEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv32i16_nxv32i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4 + + ; RV32I-LABEL: name: sext_nxv32i16_nxv32i8 + ; RV32I: liveins: $v8m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv32i16_nxv32i8 + ; RV64I: liveins: $v8m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m4 + %1:vrb() = G_SEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv1i32_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i32_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i32_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv1i64_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i64_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i64_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i32_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i32_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv2i32_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i64_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i64_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv2i64_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i32_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i32_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv4i32_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i64_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i64_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv4i64_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i32_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: sext_nxv8i32_nxv8i16 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv8i32_nxv8i16 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_SEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i64_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: sext_nxv8i64_nxv8i16 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv8i64_nxv8i16 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_SEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv16i32_nxv16i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4 + + ; RV32I-LABEL: name: sext_nxv16i32_nxv16i16 + ; RV32I: liveins: $v8m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv16i32_nxv16i16 + ; RV64I: liveins: $v8m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m4 + %1:vrb() = G_SEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv1i64_nxv1i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i64_nxv1i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i64_nxv1i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i64_nxv2i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i64_nxv2i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv2i64_nxv2i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_SEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i64_nxv4i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: sext_nxv4i64_nxv4i32 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv4i64_nxv4i32 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_SEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i64_nxv8i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4 + + ; RV32I-LABEL: name: sext_nxv8i64_nxv8i32 + ; RV32I: liveins: $v8m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv8i64_nxv8i32 + ; RV64I: liveins: $v8m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m4 + %1:vrb() = G_SEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sub.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sub.mir new file mode 100644 index 0000000..5aa0654 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sub.mir @@ -0,0 +1,774 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s +--- +name: test_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv1i8 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_MF8_:%[0-9]+]]:vr = PseudoVSUB_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF8_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv1i8 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_MF8_:%[0-9]+]]:vr = PseudoVSUB_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF8_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv2i8 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF4_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv2i8 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF4_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv4i8 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv4i8 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv8i8 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv8i8 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; RV32I-LABEL: name: test_nxv16i8 + ; RV32I: liveins: $v8m2, $v10m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: test_nxv16i8 + ; RV64I: liveins: $v8m2, $v10m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8m2 + %1:vrb() = COPY $v10m2 + %2:vrb() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; RV32I-LABEL: name: test_nxv32i8 + ; RV32I: liveins: $v8m4, $v12m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: test_nxv32i8 + ; RV64I: liveins: $v8m4, $v12m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m4 + %1:vrb() = COPY $v12m4 + %2:vrb() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; RV32I-LABEL: name: test_nxv64i8 + ; RV32I: liveins: $v8m8, $v16m8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: test_nxv64i8 + ; RV64I: liveins: $v8m8, $v16m8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m8 + %1:vrb() = COPY $v16m8 + %2:vrb() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv1i16 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF4_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv1i16 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF4_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv2i16 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv2i16 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv4i16 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv4i16 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; RV32I-LABEL: name: test_nxv8i16 + ; RV32I: liveins: $v8m2, $v10m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: test_nxv8i16 + ; RV64I: liveins: $v8m2, $v10m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8m2 + %1:vrb() = COPY $v10m2 + %2:vrb() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; RV32I-LABEL: name: test_nxv16i16 + ; RV32I: liveins: $v8m4, $v12m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: test_nxv16i16 + ; RV64I: liveins: $v8m4, $v12m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m4 + %1:vrb() = COPY $v12m4 + %2:vrb() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; RV32I-LABEL: name: test_nxv32i16 + ; RV32I: liveins: $v8m8, $v16m8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: test_nxv32i16 + ; RV64I: liveins: $v8m8, $v16m8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m8 + %1:vrb() = COPY $v16m8 + %2:vrb() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv1i32 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv1i32 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv2i32 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv2i32 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; RV32I-LABEL: name: test_nxv4i32 + ; RV32I: liveins: $v8m2, $v10m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: test_nxv4i32 + ; RV64I: liveins: $v8m2, $v10m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8m2 + %1:vrb() = COPY $v10m2 + %2:vrb() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; RV32I-LABEL: name: test_nxv8i32 + ; RV32I: liveins: $v8m4, $v12m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: test_nxv8i32 + ; RV64I: liveins: $v8m4, $v12m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m4 + %1:vrb() = COPY $v12m4 + %2:vrb() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; RV32I-LABEL: name: test_nxv16i32 + ; RV32I: liveins: $v8m8, $v16m8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: test_nxv16i32 + ; RV64I: liveins: $v8m8, $v16m8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m8 + %1:vrb() = COPY $v16m8 + %2:vrb() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; RV32I-LABEL: name: test_nxv1i64 + ; RV32I: liveins: $v8, $v9 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: test_nxv1i64 + ; RV64I: liveins: $v8, $v9 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = COPY $v9 + %2:vrb() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; RV32I-LABEL: name: test_nxv2i64 + ; RV32I: liveins: $v8m2, $v10m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: test_nxv2i64 + ; RV64I: liveins: $v8m2, $v10m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8m2 + %1:vrb() = COPY $v10m2 + %2:vrb() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv4i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; RV32I-LABEL: name: test_nxv4i64 + ; RV32I: liveins: $v8m4, $v12m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: test_nxv4i64 + ; RV64I: liveins: $v8m4, $v12m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m4 + %1:vrb() = COPY $v12m4 + %2:vrb() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv8i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; RV32I-LABEL: name: test_nxv8i64 + ; RV32I: liveins: $v8m8, $v16m8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: test_nxv8i64 + ; RV64I: liveins: $v8m8, $v16m8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m8 + %1:vrb() = COPY $v16m8 + %2:vrb() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir new file mode 100644 index 0000000..9e91d22 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir @@ -0,0 +1,124 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: splat_zero_nxv1i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1i1 + ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s32) = G_CONSTANT i32 -1 + %1:vrb() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv2i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2i1 + ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s32) = G_CONSTANT i32 -1 + %1:vrb() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv4i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4i1 + ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s32) = G_CONSTANT i32 -1 + %1:vrb() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv8i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8i1 + ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s32) = G_CONSTANT i32 -1 + %1:vrb() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv16i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv16i1 + ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s32) = G_CONSTANT i32 -1 + %1:vrb() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv32i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv32i1 + ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s32) = G_CONSTANT i32 -1 + %1:vrb() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv64i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv64i1 + ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s32) = G_CONSTANT i32 -1 + %1:vrb() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir new file mode 100644 index 0000000..80da9e6 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir @@ -0,0 +1,124 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: splat_zero_nxv1i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1i1 + ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s64) = G_CONSTANT i64 -1 + %1:vrb() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv2i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2i1 + ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s64) = G_CONSTANT i64 -1 + %1:vrb() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv4i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4i1 + ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s64) = G_CONSTANT i64 -1 + %1:vrb() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv8i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8i1 + ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s64) = G_CONSTANT i64 -1 + %1:vrb() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv16i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv16i1 + ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s64) = G_CONSTANT i64 -1 + %1:vrb() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv32i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv32i1 + ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s64) = G_CONSTANT i64 -1 + %1:vrb() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv64i1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv64i1 + ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:gprb(s64) = G_CONSTANT i64 -1 + %1:vrb() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir new file mode 100644 index 0000000..27dfb3f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir @@ -0,0 +1,300 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: test_1_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_1_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:gprb(s32) = G_READ_VLENB + %2:gprb(s32) = G_CONSTANT i32 3 + %0:gprb(s32) = G_LSHR %1, %2(s32) + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_2_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_2_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:gprb(s32) = G_READ_VLENB + %2:gprb(s32) = G_CONSTANT i32 2 + %0:gprb(s32) = G_LSHR %1, %2(s32) + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_3_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_3_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:gprb(s32) = G_READ_VLENB + %2:gprb(s32) = G_CONSTANT i32 3 + %3:gprb(s32) = G_LSHR %1, %2(s32) + %4:gprb(s32) = G_CONSTANT i32 3 + %0:gprb(s32) = G_MUL %3, %4 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_4_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_4_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:gprb(s32) = G_READ_VLENB + %2:gprb(s32) = G_CONSTANT i32 1 + %0:gprb(s32) = G_LSHR %1, %2(s32) + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_8_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_8_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = G_READ_VLENB + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_16_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_16_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:gprb(s32) = G_READ_VLENB + %2:gprb(s32) = G_CONSTANT i32 1 + %0:gprb(s32) = G_SHL %1, %2(s32) + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_40_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_40_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PseudoReadVLENB]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:gprb(s32) = G_READ_VLENB + %2:gprb(s32) = G_CONSTANT i32 5 + %0:gprb(s32) = G_MUL %1, %2 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_1_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_1_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 1 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... +--- +name: test_2_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_2_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 2 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 2 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... +--- +name: test_3_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_3_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 3 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... +--- +name: test_4_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_4_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 4 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 4 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... +--- +name: test_8_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_8_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 8 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... +--- +name: test_16_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_16_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 16 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 16 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... +--- +name: test_40_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_40_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 40 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 40 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir new file mode 100644 index 0000000..4a96be2 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir @@ -0,0 +1,139 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: test_1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_1 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + %1:gprb(s64) = G_CONSTANT i64 3 + %2:gprb(s64) = G_LSHR %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: test_2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_2 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + %1:gprb(s64) = G_CONSTANT i64 2 + %2:gprb(s64) = G_LSHR %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: test_3 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_3 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + %1:gprb(s64) = G_CONSTANT i64 3 + %2:gprb(s64) = G_LSHR %0, %1(s64) + %3:gprb(s64) = G_CONSTANT i64 3 + %4:gprb(s64) = G_MUL %2, %3 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: test_4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_4 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + %1:gprb(s64) = G_CONSTANT i64 1 + %2:gprb(s64) = G_LSHR %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: test_8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_8 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: test_16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_16 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + %1:gprb(s64) = G_CONSTANT i64 1 + %2:gprb(s64) = G_SHL %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: test_40 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_40 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PseudoReadVLENB]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + %1:gprb(s64) = G_CONSTANT i64 5 + %2:gprb(s64) = G_MUL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir new file mode 100644 index 0000000..5e4218d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir @@ -0,0 +1,900 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s + +--- +name: zext_nxv1i16_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i16_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i16_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv1i32_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i32_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i32_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv1i64_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i64_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i64_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i16_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i16_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv2i16_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i32_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i32_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv2i32_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i64_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i64_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv2i64_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i16_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i16_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv4i16_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv4i32_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i32_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv4i32_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i64_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i64_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv4i64_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i16_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i16_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv8i16_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv8i32_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i32_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv8i32_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i64_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i64_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv8i64_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv16i16_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: zext_nxv16i16_nxv16i8 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv16i16_nxv16i8 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_ZEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv16i32_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: zext_nxv16i32_nxv16i8 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv16i32_nxv16i8 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_ZEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv32i16_nxv32i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4 + + ; RV32I-LABEL: name: zext_nxv32i16_nxv32i8 + ; RV32I: liveins: $v8m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv32i16_nxv32i8 + ; RV64I: liveins: $v8m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m4 + %1:vrb() = G_ZEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv1i32_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i32_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i32_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv1i64_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i64_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i64_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i32_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i32_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv2i32_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i64_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i64_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv2i64_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i32_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i32_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv4i32_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i64_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i64_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv4i64_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i32_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: zext_nxv8i32_nxv8i16 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv8i32_nxv8i16 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_ZEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i64_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: zext_nxv8i64_nxv8i16 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv8i64_nxv8i16 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_ZEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv16i32_nxv16i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4 + + ; RV32I-LABEL: name: zext_nxv16i32_nxv16i16 + ; RV32I: liveins: $v8m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv16i32_nxv16i16 + ; RV64I: liveins: $v8m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m4 + %1:vrb() = G_ZEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv1i64_nxv1i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i64_nxv1i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i64_nxv1i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i64_nxv2i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i64_nxv2i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv2i64_nxv2i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb() = COPY $v8 + %1:vrb() = G_ZEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i64_nxv4i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2 + + ; RV32I-LABEL: name: zext_nxv4i64_nxv4i32 + ; RV32I: liveins: $v8m2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv4i64_nxv4i32 + ; RV64I: liveins: $v8m2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb() = COPY $v8m2 + %1:vrb() = G_ZEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i64_nxv8i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4 + + ; RV32I-LABEL: name: zext_nxv8i64_nxv8i32 + ; RV32I: liveins: $v8m4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv8i64_nxv8i32 + ; RV64I: liveins: $v8m4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb() = COPY $v8m4 + %1:vrb() = G_ZEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir new file mode 100644 index 0000000..552a270 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir @@ -0,0 +1,175 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select --simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s +--- +name: select_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: select_s32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = COPY $x12 + %3:gprb(s32) = G_SELECT %0, %1, %2 + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: select_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: select_p0 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(p0) = COPY $x12 + %3:gprb(p0) = G_SELECT %0, %1, %2 + $x10 = COPY %3(p0) + PseudoRET implicit $x10 + +... +--- +name: select_icmp_ult +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: select_icmp_ult + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY2]], [[COPY3]], 4, [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = COPY $x12 + %3:gprb(s32) = COPY $x13 + %4:gprb(s32) = COPY $x14 + %5:gprb(s32) = G_ICMP intpred(ult), %2, %3 + %6:gprb(s32) = G_SELECT %5, %0, %1 + $x10 = COPY %6(s32) + PseudoRET implicit $x10 + +... +--- +name: select_icmp_ugt +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: select_icmp_ugt + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY3]], [[COPY2]], 4, [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = COPY $x12 + %3:gprb(s32) = COPY $x13 + %4:gprb(s32) = COPY $x14 + %5:gprb(s32) = G_ICMP intpred(ugt), %2, %3 + %6:gprb(s32) = G_SELECT %5, %0, %1 + $x10 = COPY %6(s32) + PseudoRET implicit $x10 + +... +--- +name: select_icmp_sgtneg1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: select_icmp_sgtneg1 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY2]], $x0, 3, [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = COPY $x12 + %3:gprb(s32) = COPY $x13 + %4:gprb(s32) = COPY $x14 + %5:gprb(s32) = G_CONSTANT i32 -1 + %6:gprb(s32) = G_ICMP intpred(sgt), %2, %5 + %7:gprb(s32) = G_SELECT %6, %0, %1 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 + +... +--- +name: select_icmp_slt1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: select_icmp_slt1 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR $x0, [[COPY2]], 3, [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = COPY $x12 + %3:gprb(s32) = COPY $x13 + %4:gprb(s32) = COPY $x14 + %5:gprb(s32) = G_CONSTANT i32 1 + %6:gprb(s32) = G_ICMP intpred(slt), %2, %5 + %7:gprb(s32) = G_SELECT %6, %0, %1 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir new file mode 100644 index 0000000..fc5d54a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir @@ -0,0 +1,205 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \ +# RUN: | FileCheck %s + +--- +name: select_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: select_s32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = COPY $x12 + %3:gprb(s32) = G_TRUNC %1 + %4:gprb(s32) = G_TRUNC %2 + %5:gprb(s32) = G_SELECT %0, %3, %4 + %6:gprb(s64) = G_ANYEXT %5 + $x10 = COPY %6(s64) + PseudoRET implicit $x10 + +... +--- +name: select_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: select_s64 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = COPY $x12 + %3:gprb(s64) = G_SELECT %0, %1, %2 + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: select_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: select_p0 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(p0) = COPY $x12 + %3:gprb(p0) = G_SELECT %0, %1, %2 + $x10 = COPY %3(p0) + PseudoRET implicit $x10 + +... +--- +name: select_icmp_ult +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: select_icmp_ult + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY2]], [[COPY3]], 4, [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = COPY $x12 + %3:gprb(s64) = COPY $x13 + %4:gprb(s64) = COPY $x14 + %5:gprb(s64) = G_ICMP intpred(ult), %2, %3 + %6:gprb(s64) = G_SELECT %5, %0, %1 + $x10 = COPY %6(s64) + PseudoRET implicit $x10 + +... +--- +name: select_icmp_ugt +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: select_icmp_ugt + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY3]], [[COPY2]], 4, [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = COPY $x12 + %3:gprb(s64) = COPY $x13 + %4:gprb(s64) = COPY $x14 + %5:gprb(s64) = G_ICMP intpred(ugt), %2, %3 + %6:gprb(s64) = G_SELECT %5, %0, %1 + $x10 = COPY %6(s64) + PseudoRET implicit $x10 + +... +--- +name: select_icmp_sgtneg1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: select_icmp_sgtneg1 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY2]], $x0, 3, [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = COPY $x12 + %3:gprb(s64) = COPY $x13 + %4:gprb(s64) = COPY $x14 + %5:gprb(s64) = G_CONSTANT i64 -1 + %6:gprb(s64) = G_ICMP intpred(sgt), %2, %5 + %7:gprb(s64) = G_SELECT %6, %0, %1 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: select_icmp_slt1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: select_icmp_slt1 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR $x0, [[COPY2]], 3, [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = COPY $x12 + %3:gprb(s64) = COPY $x13 + %4:gprb(s64) = COPY $x14 + %5:gprb(s64) = G_CONSTANT i64 1 + %6:gprb(s64) = G_ICMP intpred(slt), %2, %5 + %7:gprb(s64) = G_SELECT %6, %0, %1 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/sext-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/sext-rv64.mir new file mode 100644 index 0000000..36f33f4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/sext-rv64.mir @@ -0,0 +1,37 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s +--- +name: sext_32_64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sext_32_64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0 + ; CHECK-NEXT: $x8 = COPY [[ADDIW]] + %0:gprb(s64) = COPY $x10 + %1:gprb(s32) = G_TRUNC %0 + %2:gprb(s64) = G_SEXT %1 + $x8 = COPY %2(s64) +... +--- +name: sext_inreg_64_32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: name: sext_inreg_64_32 + ; CHECK: [[LUI:%[0-9]+]]:gpr = LUI 524288 + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 0 + ; CHECK-NEXT: $x8 = COPY [[ADDIW]] + %0:gprb(s64) = G_CONSTANT i64 -2147483648 + %1:gprb(s64) = G_SEXT_INREG %0, 32 + $x8 = COPY %1(s64) +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv32.mir new file mode 100644 index 0000000..4d0b5c2 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv32.mir @@ -0,0 +1,246 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +# This 32-bit version doesn't have tests for zext, because there is no legal type to zext from. +--- +name: shl +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %3:gprb(s32) = G_SHL %0, %1 + $x10 = COPY %3(s32) + PseudoRET implicit $x10 +... + +--- +name: shl_and +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_and + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 31 + %3:gprb(s32) = G_AND %1, %2 + %4:gprb(s32) = G_SHL %0, %3(s32) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... + +--- +name: shl_and_with_simplified_mask +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_and_with_simplified_mask + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY1]], 31 + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 31 + %3:gprb(s32) = G_AND %1, %2 + %4:gprb(s32) = G_CONSTANT i32 31 + %5:gprb(s32) = G_AND %3, %4 + %6:gprb(s32) = G_SHL %0, %5(s32) + $x10 = COPY %6(s32) + PseudoRET implicit $x10 +... + +--- +name: shl_add +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_add + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 32 + %3:gprb(s32) = G_ADD %1, %2 + %4:gprb(s32) = G_SHL %0, %3(s32) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... + +--- +name: shl_sub +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_sub + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB $x0, [[COPY1]] + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[SUB]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 32 + %3:gprb(s32) = G_SUB %2, %1 + %4:gprb(s32) = G_SHL %0, %3(s32) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... + +--- +name: shl_bitwise_not +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_bitwise_not + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1 + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[XORI]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 -1 + %3:gprb(s32) = G_SUB %2, %1 + %4:gprb(s32) = G_SHL %0, %3(s32) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... + +--- +name: shl_bitwise_not_2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_bitwise_not_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1 + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[XORI]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 31 + %3:gprb(s32) = G_SUB %2, %1 + %4:gprb(s32) = G_SHL %0, %3(s32) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... + +--- +name: srl_and_needed +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: srl_and_needed + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 15 + ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SRL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 15 + %3:gprb(s32) = G_AND %0, %2 + %4:gprb(s32) = G_LSHR %1, %3(s32) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... + +--- +name: srl_and_eliminated +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: srl_and_eliminated + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 47 + ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SRL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 15 + %3:gprb(s32) = G_CONSTANT i32 47 + %4:gprb(s32) = G_AND %0, %3 + %5:gprb(s32) = G_AND %4, %2 + %6:gprb(s32) = G_LSHR %1, %5(s32) + $x10 = COPY %6(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv64.mir new file mode 100644 index 0000000..1a8d155 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv64.mir @@ -0,0 +1,273 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: shl +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %3:gprb(s64) = G_SHL %0, %1 + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... + +--- +name: shl_and +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_and + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 63 + %3:gprb(s64) = G_AND %1, %2 + %4:gprb(s64) = G_SHL %0, %3(s64) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... + +--- +name: shl_and_with_simplified_mask +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_and_with_simplified_mask + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY1]], 62 + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 62 + %3:gprb(s64) = G_AND %1, %2 + %4:gprb(s64) = G_CONSTANT i64 62 + %5:gprb(s64) = G_AND %3, %4 + %6:gprb(s64) = G_SHL %0, %5(s64) + $x10 = COPY %6(s64) + PseudoRET implicit $x10 +... + +--- +name: shl_add +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_add + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 64 + %3:gprb(s64) = G_ADD %1, %2 + %4:gprb(s64) = G_SHL %0, %3(s64) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... + +--- +name: shl_sub +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_sub + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SUBW:%[0-9]+]]:gpr = SUBW $x0, [[COPY1]] + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[SUBW]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 64 + %3:gprb(s64) = G_SUB %2, %1 + %4:gprb(s64) = G_SHL %0, %3(s64) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... + +--- +name: shl_bitwise_not +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_bitwise_not + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1 + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[XORI]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 -1 + %3:gprb(s64) = G_SUB %2, %1 + %4:gprb(s64) = G_SHL %0, %3(s64) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... + +--- +name: shl_bitwise_not_2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_bitwise_not_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1 + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[XORI]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 63 + %3:gprb(s64) = G_SUB %2, %1 + %4:gprb(s64) = G_SHL %0, %3(s64) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... + +--- +name: shl_and_zext +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_and_zext + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (load (s32)) + ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[LW]] + ; CHECK-NEXT: $x10 = COPY [[SLL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s64) = G_LOAD %1(p0) :: (load (s32)) + %3:gprb(s64) = G_CONSTANT i64 63 + %4:gprb(s64) = G_AND %2, %3 + %5:gprb(s64) = G_SHL %0, %4(s64) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: srl_and_needed +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: srl_and_needed + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 15 + ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SRL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 15 + %3:gprb(s64) = G_AND %0, %2 + %4:gprb(s64) = G_LSHR %1, %3(s64) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... + +--- +name: srl_and_eliminated +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: srl_and_eliminated + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 79 + ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]] + ; CHECK-NEXT: $x10 = COPY [[SRL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 15 + %6:gprb(s64) = G_CONSTANT i64 79 + %7:gprb(s64) = G_AND %0, %6 + %3:gprb(s64) = G_AND %7, %2 + %5:gprb(s64) = G_LSHR %1, %3(s64) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir new file mode 100644 index 0000000..227eaae --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir @@ -0,0 +1,214 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \ +# RUN: -disable-gisel-legality-check | FileCheck %s +# +--- +name: store_i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x11 + + ; CHECK-LABEL: name: store_i8 + ; CHECK: liveins: $x10, $x11, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SB [[COPY]], [[COPY1]], 0 :: (store (s8)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s32) = COPY $x10 + %1:gprb(p0) = COPY $x11 + G_STORE %0(s32), %1(p0) :: (store (s8)) + PseudoRET + +... +--- +name: store_i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SH [[COPY]], [[COPY1]], 0 :: (store (s16)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s32) = COPY $x10 + %1:gprb(p0) = COPY $x11 + G_STORE %0(s32), %1(p0) :: (store (s16)) + PseudoRET + +... +--- +name: store_i8_i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i8_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SB [[COPY]], [[COPY1]], 0 :: (store (s8)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s32) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s16) = G_TRUNC %0 + G_STORE %2(s16), %1(p0) :: (store (s8)) + PseudoRET + +... +--- +name: store_i16_i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i16_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SH [[COPY]], [[COPY1]], 0 :: (store (s16)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s32) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s16) = G_TRUNC %0 + G_STORE %2(s16), %1(p0) :: (store (s16)) + PseudoRET + +... +--- +name: store_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SW [[COPY]], [[COPY1]], 0 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s32) = COPY $x10 + %1:gprb(p0) = COPY $x11 + G_STORE %0(s32), %1(p0) :: (store (s32)) + PseudoRET + +... +--- +name: store_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SW [[COPY]], [[COPY1]], 0 :: (store (p0)) + ; CHECK-NEXT: PseudoRET + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + G_STORE %0(p0), %1(p0) :: (store (p0)) + PseudoRET + +... +--- +name: store_fi_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +stack: + - { id: 0, offset: 0, size: 4, alignment: 4 } + +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: store_fi_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: SW [[COPY]], %stack.0, 0 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s32) = COPY $x10 + %1:gprb(p0) = G_FRAME_INDEX %stack.0 + G_STORE %0(s32), %1(p0) :: (store (s32)) + PseudoRET + +... +--- +name: store_fi_gep_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +stack: + - { id: 0, offset: 0, size: 8, alignment: 4 } + +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: store_fi_gep_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: SW [[COPY]], %stack.0, 4 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s32) = COPY $x10 + %1:gprb(p0) = G_FRAME_INDEX %stack.0 + %2:gprb(s32) = G_CONSTANT i32 4 + %3:gprb(p0) = G_PTR_ADD %1(p0), %2(s32) + G_STORE %0(s32), %3(p0) :: (store (s32)) + PseudoRET + +... +--- +name: store_gep_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_gep_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SW [[COPY]], [[COPY1]], 4 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s32) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 4 + %3:gprb(p0) = G_PTR_ADD %1(p0), %2(s32) + G_STORE %0(s32), %3(p0) :: (store (s32)) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir new file mode 100644 index 0000000..c177637 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir @@ -0,0 +1,317 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \ +# RUN: -disable-gisel-legality-check | FileCheck %s + +--- +name: store_i8_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i8_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SB [[COPY]], [[COPY1]], 0 :: (store (s8)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = COPY $x11 + G_STORE %0(s64), %1(p0) :: (store (s8)) + PseudoRET + +... +--- +name: store_i16_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i16_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SH [[COPY]], [[COPY1]], 0 :: (store (s16)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = COPY $x11 + G_STORE %0(s64), %1(p0) :: (store (s16)) + PseudoRET + +... +--- +name: store_i8_i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i8_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SB [[COPY]], [[COPY1]], 0 :: (store (s8)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s16) = G_TRUNC %0 + G_STORE %2(s16), %1(p0) :: (store (s8)) + PseudoRET + +... +--- +name: store_i16_i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i16_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SH [[COPY]], [[COPY1]], 0 :: (store (s16)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s16) = G_TRUNC %0 + G_STORE %2(s16), %1(p0) :: (store (s16)) + PseudoRET + +... +--- +name: store_i32_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i32_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SW [[COPY]], [[COPY1]], 0 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = COPY $x11 + G_STORE %0(s64), %1(p0) :: (store (s32)) + PseudoRET + +... +--- +name: store_i64_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i64_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SD [[COPY]], [[COPY1]], 0 :: (store (s64)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = COPY $x11 + G_STORE %0(s64), %1(p0) :: (store (s64)) + PseudoRET + +... +--- +name: store_p0 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_p0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SD [[COPY]], [[COPY1]], 0 :: (store (p0)) + ; CHECK-NEXT: PseudoRET + %0:gprb(p0) = COPY $x10 + %1:gprb(p0) = COPY $x11 + G_STORE %0(p0), %1(p0) :: (store (p0)) + PseudoRET + +... +--- +name: truncstore_i8_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: truncstore_i8_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SB [[COPY1]], [[COPY]], 0 :: (store (s8)) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY2]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %3:gprb(s64) = COPY $x11 + %9:gprb(s32) = G_TRUNC %3(s64) + G_STORE %9(s32), %0(p0) :: (store (s8)) + %7:gprb(s64) = G_CONSTANT i64 0 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: truncstore_i16_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: truncstore_i16_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SH [[COPY1]], [[COPY]], 0 :: (store (s16)) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY2]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %3:gprb(s64) = COPY $x11 + %9:gprb(s32) = G_TRUNC %3(s64) + G_STORE %9(s32), %0(p0) :: (store (s16)) + %7:gprb(s64) = G_CONSTANT i64 0 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: store_i32_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i32_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SW [[COPY1]], [[COPY]], 0 :: (store (s32)) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY2]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(p0) = COPY $x10 + %3:gprb(s64) = COPY $x11 + %9:gprb(s32) = G_TRUNC %3(s64) + G_STORE %9(s32), %0(p0) :: (store (s32)) + %7:gprb(s64) = G_CONSTANT i64 0 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: store_fi_i64_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +stack: + - { id: 0, offset: 0, size: 8, alignment: 8 } + +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: store_fi_i64_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: SD [[COPY]], %stack.0, 0 :: (store (s64)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = G_FRAME_INDEX %stack.0 + G_STORE %0(s64), %1(p0) :: (store (s64)) + PseudoRET + +... +--- +name: store_fi_gep_i64_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +stack: + - { id: 0, offset: 0, size: 16, alignment: 8 } + +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: store_fi_gep_i64_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: SD [[COPY]], %stack.0, 8 :: (store (s64)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = G_FRAME_INDEX %stack.0 + %2:gprb(s64) = G_CONSTANT i64 8 + %3:gprb(p0) = G_PTR_ADD %1(p0), %2(s64) + G_STORE %0(s64), %3(p0) :: (store (s64)) + PseudoRET + +... +--- +name: store_gep_i64_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_gep_i64_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SD [[COPY]], [[COPY1]], 8 :: (store (s64)) + ; CHECK-NEXT: PseudoRET + %0:gprb(s64) = COPY $x10 + %1:gprb(p0) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 8 + %3:gprb(p0) = G_PTR_ADD %1(p0), %2(s64) + G_STORE %0(s64), %3(p0) :: (store (s64)) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir new file mode 100644 index 0000000..5f52030 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir @@ -0,0 +1,34 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: test_trap +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: test_trap + ; CHECK: UNIMP + ; CHECK-NEXT: PseudoRET + G_TRAP + PseudoRET + +... +--- +name: test_debugtrap +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: test_debugtrap + ; CHECK: EBREAK + ; CHECK-NEXT: PseudoRET + G_DEBUGTRAP + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv32.mir new file mode 100644 index 0000000..f90de3e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv32.mir @@ -0,0 +1,152 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -mattr='+zba' -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck %s + +--- +name: sh1add +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: sh1add + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SH1ADD:%[0-9]+]]:gpr = SH1ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SH1ADD]] + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 1 + %3:gprb(s32) = G_SHL %0, %2 + %4:gprb(s32) = G_ADD %3, %1 + $x10 = COPY %4(s32) +... +--- +name: sh2add +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: sh2add + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SH2ADD:%[0-9]+]]:gpr = SH2ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SH2ADD]] + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 2 + %3:gprb(s32) = G_SHL %0, %2 + %4:gprb(s32) = G_ADD %3, %1 + $x10 = COPY %4(s32) +... +--- +name: sh3add +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: sh3add + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SH3ADD:%[0-9]+]]:gpr = SH3ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SH3ADD]] + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_CONSTANT i32 3 + %3:gprb(s32) = G_SHL %0, %2 + %4:gprb(s32) = G_ADD %3, %1 + $x10 = COPY %4(s32) +... +--- +name: no_sh1add +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: no_sh1add + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 1 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[SLLI]], 37 + ; CHECK-NEXT: $x10 = COPY [[ADDI]] + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 37 + %2:gprb(s32) = G_CONSTANT i32 1 + %3:gprb(s32) = G_SHL %0, %2 + %4:gprb(s32) = G_ADD %3, %1 + $x10 = COPY %4(s32) +... +--- +name: shXadd_complex_shl_and +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shXadd_complex_shl_and + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 1 + ; CHECK-NEXT: [[SH2ADD:%[0-9]+]]:gpr = SH2ADD [[SRLI]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SH2ADD]] + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + + %2:gprb(s32) = G_CONSTANT i32 1 + %3:gprb(s32) = G_SHL %0, %2 + %4:gprb(s32) = G_CONSTANT i32 4294967292 + %5:gprb(s32) = G_AND %3, %4 + + %6:gprb(s32) = G_ADD %5, %1 + $x10 = COPY %6(s32) +... +--- +name: shXadd_complex_lshr_and +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shXadd_complex_lshr_and + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 29 + ; CHECK-NEXT: [[SH2ADD:%[0-9]+]]:gpr = SH2ADD [[SRLI]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SH2ADD]] + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + + %2:gprb(s32) = G_CONSTANT i32 27 + %3:gprb(s32) = G_LSHR %0, %2 + %4:gprb(s32) = G_CONSTANT i32 60 + %5:gprb(s32) = G_AND %3, %4 + + %6:gprb(s32) = G_ADD %5, %1 + $x10 = COPY %6(s32) +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir new file mode 100644 index 0000000..345dc48 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir @@ -0,0 +1,250 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr='+zba' -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck %s + +--- +name: sh1add +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: sh1add + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SH1ADD:%[0-9]+]]:gpr = SH1ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SH1ADD]] + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 1 + %3:gprb(s64) = G_SHL %0, %2 + %4:gprb(s64) = G_ADD %3, %1 + $x10 = COPY %4(s64) +... +--- +name: sh2add +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: sh2add + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SH2ADD:%[0-9]+]]:gpr = SH2ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SH2ADD]] + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 2 + %3:gprb(s64) = G_SHL %0, %2 + %4:gprb(s64) = G_ADD %3, %1 + $x10 = COPY %4(s64) +... +--- +name: sh3add +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: sh3add + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SH3ADD:%[0-9]+]]:gpr = SH3ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SH3ADD]] + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 3 + %3:gprb(s64) = G_SHL %0, %2 + %4:gprb(s64) = G_ADD %3, %1 + $x10 = COPY %4(s64) +... +--- +name: no_sh1add +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: no_sh1add + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 1 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[SLLI]], 37 + ; CHECK-NEXT: $x10 = COPY [[ADDI]] + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 37 + %2:gprb(s64) = G_CONSTANT i64 1 + %3:gprb(s64) = G_SHL %0, %2 + %4:gprb(s64) = G_ADD %3, %1 + $x10 = COPY %4(s64) +... +--- +name: shXadd_complex_and_shl +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shXadd_complex_and_shl + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SRLIW:%[0-9]+]]:gpr = SRLIW [[COPY]], 1 + ; CHECK-NEXT: [[SH3ADD:%[0-9]+]]:gpr = SH3ADD [[SRLIW]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SH3ADD]] + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + + %2:gprb(s64) = G_CONSTANT i64 4294967294 + %3:gprb(s64) = G_AND %0, %2 + %4:gprb(s64) = G_CONSTANT i64 2 + %5:gprb(s64) = G_SHL %3, %4 + + %6:gprb(s64) = G_ADD %5, %1 + $x10 = COPY %6(s64) +... +--- +name: shXadd_complex_and_lshr +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shXadd_complex_and_lshr + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SRLIW:%[0-9]+]]:gpr = SRLIW [[COPY]], 2 + ; CHECK-NEXT: [[SH1ADD:%[0-9]+]]:gpr = SH1ADD [[SRLIW]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SH1ADD]] + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + + %2:gprb(s64) = G_CONSTANT i64 4294967292 + %3:gprb(s64) = G_AND %0, %2 + %4:gprb(s64) = G_CONSTANT i64 1 + %5:gprb(s64) = G_LSHR %3, %4 + + %6:gprb(s64) = G_ADD %5, %1 + $x10 = COPY %6(s64) +... +--- +name: shXadd_uw_complex_shl_and +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shXadd_uw_complex_shl_and + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 1 + ; CHECK-NEXT: [[SH2ADD_UW:%[0-9]+]]:gpr = SH2ADD_UW [[SLLI]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SH2ADD_UW]] + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + + %2:gprb(s64) = G_CONSTANT i64 3 + %3:gprb(s64) = G_SHL %0, %2 + %4:gprb(s64) = G_CONSTANT i64 17179869183 + %5:gprb(s64) = G_AND %3, %4 + + %6:gprb(s64) = G_ADD %5, %1 + $x10 = COPY %6(s64) +... +--- +name: slli_uw +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: slli_uw + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLLI_UW:%[0-9]+]]:gpr = SLLI_UW [[COPY]], 7 + ; CHECK-NEXT: $x10 = COPY [[SLLI_UW]] + %0:gprb(s64) = COPY $x10 + + %1:gprb(s64) = G_CONSTANT i64 4294967295 + %2:gprb(s64) = G_AND %0, %1 + %3:gprb(s64) = G_CONSTANT i64 7 + %4:gprb(s64) = G_SHL %2, %3 + + $x10 = COPY %4(s64) +... +--- +name: slli_uw_complex +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: slli_uw_complex + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 2 + ; CHECK-NEXT: [[SLLI_UW:%[0-9]+]]:gpr = SLLI_UW [[SRLI]], 2 + ; CHECK-NEXT: $x10 = COPY [[SLLI_UW]] + %0:gprb(s64) = COPY $x10 + + %1:gprb(s64) = G_CONSTANT i64 17179869180 + %2:gprb(s64) = G_AND %0, %1 + + $x10 = COPY %2(s64) +... +--- +name: adduw +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: adduw + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ADD_UW:%[0-9]+]]:gpr = ADD_UW [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ADD_UW]] + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_CONSTANT i64 4294967295 + %3:gprb(s64) = G_AND %0, %2 + %4:gprb(s64) = G_ADD %3, %1 + $x10 = COPY %4(s64) +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zext-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zext-rv64.mir new file mode 100644 index 0000000..12c2fd0 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zext-rv64.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -verify-machineinstrs -mattr='+zba' %s -o - | FileCheck %s --check-prefix=ZBA +--- +name: zext_32_64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zext_32_64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 32 + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[SLLI]], 32 + ; CHECK-NEXT: $x8 = COPY [[SRLI]] + ; + ; ZBA-LABEL: name: zext_32_64 + ; ZBA: liveins: $x10 + ; ZBA-NEXT: {{ $}} + ; ZBA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; ZBA-NEXT: [[ADD_UW:%[0-9]+]]:gpr = ADD_UW [[COPY]], $x0 + ; ZBA-NEXT: $x8 = COPY [[ADD_UW]] + %0:gprb(s64) = COPY $x10 + %1:gprb(s32) = G_TRUNC %0 + %2:gprb(s64) = G_ZEXT %1 + $x8 = COPY %2(s64) +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/knownbits-copy-crash.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/knownbits-copy-crash.mir new file mode 100644 index 0000000..99be88b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/knownbits-copy-crash.mir @@ -0,0 +1,36 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -mattr=+zbb,+f -run-pass=instruction-select %s -o - | FileCheck %s + +--- +name: foo +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: foo + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, %6, %bb.1 + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[PHI]], 0 + ; CHECK-NEXT: [[FCVT_S_W:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_W [[ADDIW]], 7 + ; CHECK-NEXT: [[FCVT_W_S:%[0-9]+]]:gpr = nofpexcept FCVT_W_S [[FCVT_S_W]], 1 + ; CHECK-NEXT: PseudoBR %bb.1 + bb.1: + %7:gprb(s64) = G_CONSTANT i64 0 + %3:gprb(s32) = G_TRUNC %7(s64) + + bb.2: + %0:gprb(s32) = G_PHI %3(s32), %bb.1, %2(s32), %bb.2 + %6:gprb(s64) = G_SEXT %0(s32) + %1:fprb(s32) = G_SITOFP %6(s64) + %5:gprb(s64) = G_FCVT_W_RV64 %1(s32), 1 + %2:gprb(s32) = G_TRUNC %5(s64) + G_BR %bb.2 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir new file mode 100644 index 0000000..2aa2f2e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir @@ -0,0 +1,977 @@ +# RUN: llc -mtriple=riscv32-- -run-pass=legalizer %s \ +# RUN: -mattr=+m,+zbb,+zfh,+v -o - 2>&1 | FileCheck %s --check-prefixes=CHECK +# RUN: llc -mtriple=riscv64-- -run-pass=legalizer %s \ +# RUN: -mattr=+m,+zbb,+zfh,+v -o - 2>&1 | FileCheck %s --check-prefixes=CHECK + +# RUN: llc -mtriple=riscv32-- -run-pass=legalizer %s -debug-only=legalizer-info -verbose-gisel-verify-legalizer-info \ +# RUN: -mattr=+m,+zbb,+zfh,+v -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,DEBUG,DEBUG-RV32 +# RUN: llc -mtriple=riscv64-- -run-pass=legalizer %s -debug-only=legalizer-info -verbose-gisel-verify-legalizer-info \ +# RUN: -mattr=+m,+zbb,+zfh,+v -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,DEBUG,DEBUG-RV64 + +# REQUIRES: asserts + +# The main purpose of this test is to make sure we don't over-relax +# LegalizerInfo validation and lose its ability to catch bugs. +# +# Watch out for every "SKIPPED: user-defined predicate detected" in the +# check-lines below and keep each and every one of them justified. + + +# DEBUG: G_ADD (opcode [[ADD_OPC:[0-9]+]]): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_SUB (opcode [[SUB_OPC:[0-9]+]]): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_MUL (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_SDIV (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_UDIV (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_SREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_UREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_SDIVREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_UDIVREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_AND (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_OR (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_XOR (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_ABDS (opcode [[G_ABDS:[0-9]+]]): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_ABDU (opcode [[G_ABDU:[0-9]+]]): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode [[G_ABDU]] is aliased to [[G_ABDS]] +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_UAVGFLOOR (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# +# DEBUG-NEXT: G_UAVGCEIL (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# +# DEBUG-NEXT: G_SAVGFLOOR (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# +# DEBUG-NEXT: G_SAVGCEIL (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# +# DEBUG-NEXT: G_IMPLICIT_DEF (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_PHI (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_FRAME_INDEX (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_GLOBAL_VALUE (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_PTRAUTH_GLOBAL_VALUE (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# +# DEBUG-NEXT: G_CONSTANT_POOL (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_EXTRACT (opcode {{[0-9]+}}): 2 type indices, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# +# DEBUG-NEXT: G_UNMERGE_VALUES (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-RV32-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-RV32-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-RV64-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-RV64-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_INSERT (opcode {{[0-9]+}}): 2 type indices, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# +# DEBUG-NEXT: G_MERGE_VALUES (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-RV32-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-RV32-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-RV64-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-RV64-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_BUILD_VECTOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# +# DEBUG-NEXT: G_BUILD_VECTOR_TRUNC (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# +# DEBUG-NEXT: G_CONCAT_VECTORS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# +# DEBUG-NEXT: G_PTRTOINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_INTTOPTR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# +# DEBUG-NEXT: G_BITCAST (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# +# DEBUG-NEXT: G_FREEZE (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected + +# DEBUG-NEXT: G_CONSTANT_FOLD_BARRIER (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected + +# DEBUG-NEXT: G_INTRINSIC_FPTRUNC_ROUND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined + +# DEBUG-NEXT: G_INTRINSIC_TRUNC (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_INTRINSIC_ROUND (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_INTRINSIC_LRINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_INTRINSIC_LLRINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_INTRINSIC_ROUNDEVEN (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_READCYCLECOUNTER (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_READSTEADYCOUNTER (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined + +# DEBUG-NEXT: G_LOAD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SEXTLOAD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_ZEXTLOAD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_FPEXTLOAD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_INDEXED_LOAD (opcode {{[0-9]+}}): 3 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_INDEXED_SEXTLOAD (opcode {{[0-9]+}}): 3 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_INDEXED_ZEXTLOAD (opcode {{[0-9]+}}): 3 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_STORE (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_FPTRUNCSTORE (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_INDEXED_STORE (opcode {{[0-9]+}}): 3 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMIC_CMPXCHG_WITH_SUCCESS (opcode {{[0-9]+}}): 3 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_ATOMIC_CMPXCHG (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_ATOMICRMW_XCHG (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_ADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_ATOMICRMW_SUB (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_ATOMICRMW_AND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_NAND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_OR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_XOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_MAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_MIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_UMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_UMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_FADD (opcode {{[0-9]+}}): 2 type indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_FSUB (opcode {{[0-9]+}}): 2 type indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_FMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_FMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_FMAXIMUM (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_FMINIMUM (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_FMAXIMUMNUM (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_FMINIMUMNUM (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_UINC_WRAP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_UDEC_WRAP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_USUB_COND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ATOMICRMW_USUB_SAT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FENCE (opcode {{[0-9]+}}): 0 type indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_PREFETCH (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_BRCOND (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_BRINDIRECT (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_INVOKE_REGION_START (opcode {{[0-9]+}}): 0 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_INTRINSIC (opcode {{[0-9]+}}): 0 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_INTRINSIC_W_SIDE_EFFECTS (opcode {{[0-9]+}}): 0 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_INTRINSIC_CONVERGENT (opcode {{[0-9]+}}): 0 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS (opcode {{[0-9]+}}): 0 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_ANYEXT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_TRUNC (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_TRUNC_SSAT_S (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_TRUNC_SSAT_U (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_TRUNC_USAT_U (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_CONSTANT (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FCONSTANT (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_VASTART (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_VAARG (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_SEXT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SEXT_INREG (opcode {{[0-9]+}}): 1 type index, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_ZEXT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SHL (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_LSHR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_ASHR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FSHL (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_FSHR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_ROTR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_ROTL (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_ICMP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_FCMP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_SCMP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_UCMP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SELECT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_UADDO (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_UADDE (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_USUBO (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_USUBE (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SADDO (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SADDE (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SSUBO (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SSUBE (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_UMULO (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SMULO (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_UMULH (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SMULH (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_UADDSAT (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SADDSAT (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_USUBSAT (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SSUBSAT (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_USHLSAT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SSHLSAT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SMULFIX (opcode {{[0-9]+}}): 1 type index, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_UMULFIX (opcode {{[0-9]+}}): 1 type index, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_SMULFIXSAT (opcode {{[0-9]+}}): 1 type index, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_UMULFIXSAT (opcode {{[0-9]+}}): 1 type index, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_SDIVFIX (opcode {{[0-9]+}}): 1 type index, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_UDIVFIX (opcode {{[0-9]+}}): 1 type index, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_SDIVFIXSAT (opcode {{[0-9]+}}): 1 type index, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_UDIVFIXSAT (opcode {{[0-9]+}}): 1 type index, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FADD (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FSUB (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FMUL (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FMA (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FMAD (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FDIV (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FMODF (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FPOW (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FPOWI (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FEXP (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FEXP2 (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FEXP10 (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FLOG (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FLOG2 (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FLOG10 (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FLDEXP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FFREXP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FNEG (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FPEXT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FPTRUNC (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FPTOSI (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FPTOUI (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_SITOFP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_UITOFP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_FPTOSI_SAT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FPTOUI_SAT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FABS (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FCOPYSIGN (opcode {{[0-9]+}}): 2 type indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_IS_FPCLASS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_FCANONICALIZE (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FMINNUM (opcode {{[0-9]+}}): 1 type index +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FMAXNUM (opcode {{[0-9]+}}): 1 type index +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FMINNUM_IEEE (opcode {{[0-9]+}}): 1 type index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FMAXNUM_IEEE (opcode {{[0-9]+}}): 1 type index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FMINIMUM (opcode {{[0-9]+}}): 1 type index +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FMAXIMUM (opcode {{[0-9]+}}): 1 type index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FMINIMUMNUM (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FMAXIMUMNUM (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_GET_FPENV (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_SET_FPENV (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_RESET_FPENV (opcode {{[0-9]+}}): 0 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_GET_FPMODE (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_SET_FPMODE (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_RESET_FPMODE (opcode {{[0-9]+}}): 0 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_GET_ROUNDING (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_SET_ROUNDING (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_PTR_ADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_PTRMASK (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_SMIN (opcode {{[0-9]+}}): 1 type index +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_SMAX (opcode {{[0-9]+}}): 1 type index +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_UMIN (opcode {{[0-9]+}}): 1 type index +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_UMAX (opcode {{[0-9]+}}): 1 type index +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_ABS (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_LROUND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_LLROUND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_BR (opcode {{[0-9]+}}): 0 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_BRJT (opcode {{[0-9]+}}): 2 type indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_VSCALE (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_INSERT_SUBVECTOR (opcode {{[0-9]+}}): 2 type indices, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_EXTRACT_SUBVECTOR (opcode {{[0-9]+}}): 2 type indices, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_INSERT_VECTOR_ELT (opcode {{[0-9]+}}): 3 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_EXTRACT_VECTOR_ELT (opcode {{[0-9]+}}): 3 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_SHUFFLE_VECTOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_SPLAT_VECTOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_STEP_VECTOR (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECTOR_COMPRESS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_CTTZ (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_CTTZ_ZERO_POISON (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_CTLZ (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_CTLZ_ZERO_POISON (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_CTLS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_CTPOP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 2, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_BSWAP (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_BITREVERSE (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_CLMUL (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FCEIL (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FCOS (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FSIN (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FSINCOS (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_FTAN (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FACOS (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FASIN (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FATAN (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FATAN2 (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FCOSH (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FSINH (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FTANH (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FSQRT (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FFLOOR (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FRINT (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_FNEARBYINT (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_ADDRSPACE_CAST (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_BLOCK_ADDR (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_JUMP_TABLE (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. the first uncovered type index: 1, OK +# DEBUG-NEXT: .. the first uncovered imm index: 0, OK +# DEBUG-NEXT: G_DYN_STACKALLOC (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_STACKSAVE (opcode [[STACKSAVE:[0-9]+]]): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_STACKRESTORE (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_STRICT_FADD (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_STRICT_FSUB (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_STRICT_FMUL (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_STRICT_FDIV (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_STRICT_FREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_STRICT_FMA (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_STRICT_FSQRT (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_STRICT_FLDEXP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_STRICT_FCMP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_STRICT_FCMPS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_READ_REGISTER (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_WRITE_REGISTER (opcode {{[0-9]+}}): 1 type index, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_MEMCPY (opcode {{[0-9]+}}): 3 type indices, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_MEMCPY_INLINE (opcode {{[0-9]+}}): 3 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_MEMMOVE (opcode {{[0-9]+}}): 3 type indices, 1 imm index +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_MEMSET (opcode {{[0-9]+}}): 3 type indices, 1 imm index +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_BZERO (opcode {{[0-9]+}}): 2 type indices, 1 imm index +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_TRAP (opcode {{[0-9]+}}): 0 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_DEBUGTRAP (opcode {{[0-9]+}}): 0 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_UBSANTRAP (opcode {{[0-9]+}}): 0 type indices, 0 imm indices +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} +# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected +# DEBUG-NEXT: G_VECREDUCE_SEQ_FADD (opcode {{[0-9]+}}): 3 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_SEQ_FMUL (opcode {{[0-9]+}}): 3 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_FADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_FMUL (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_FMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_FMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_FMAXIMUM (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_FMINIMUM (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_ADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_MUL (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_AND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_OR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_XOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_SMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_SMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_UMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_VECREDUCE_UMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_SBFX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: G_UBFX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices +# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined +# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined +# CHECK-NOT: ill-defined + +--- +name: dummy +body: | + bb.0: +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir new file mode 100644 index 0000000..d4a0c3b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir @@ -0,0 +1,316 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32I +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB + +--- +name: abds_i8 +body: | + bb.0.entry: + liveins: $x10, $x11 + ; RV32I-LABEL: name: abds_i8 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8 + ; RV32I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 8 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s32), [[ASSERT_SEXT1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: abds_i8 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8 + ; RV32ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 8 + ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]] + ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %3:_(s32) = G_ASSERT_SEXT %1, 8 + %4:_(s32) = G_ASSERT_SEXT %2, 8 + %5:_(s8) = G_TRUNC %3(s32) + %6:_(s8) = G_TRUNC %4(s32) + %7:_(s8) = G_ABDS %5, %6 + %8:_(s32) = G_ANYEXT %7(s8) + $x10 = COPY %8(s32) + PseudoRET implicit $x10 +... +--- +name: abds_i16 +body: | + bb.0.entry: + liveins: $x10, $x11 + ; RV32I-LABEL: name: abds_i16 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16 + ; RV32I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 16 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s32), [[ASSERT_SEXT1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: abds_i16 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16 + ; RV32ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 16 + ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]] + ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %3:_(s32) = G_ASSERT_SEXT %1, 16 + %4:_(s32) = G_ASSERT_SEXT %2, 16 + %5:_(s16) = G_TRUNC %3(s32) + %6:_(s16) = G_TRUNC %4(s32) + %7:_(s16) = G_ABDS %5, %6 + %8:_(s32) = G_ANYEXT %7(s16) + $x10 = COPY %8(s32) + PseudoRET implicit $x10 +... +--- +name: abds_i32 +body: | + bb.0.entry: + liveins: $x10, $x11 + ; RV32I-LABEL: name: abds_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: abds_i32 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[COPY1]] + ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[COPY1]] + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]] + ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %3:_(s32) = G_ABDS %1, %2 + $x10 = COPY %3(s32) + PseudoRET implicit $x10 +... +--- +name: abds_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: abds_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[COPY]] + ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]] + ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[ICMP1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[ICMP2]], [[ICMP3]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB]], [[SUB3]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB2]], [[SUB5]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $x10 + %4:_(s32) = COPY $x11 + %5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32) + %6:_(s64) = G_ABDS %2, %5 + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $x10 = COPY %7(s32) + $x11 = COPY %8(s32) + PseudoRET implicit $x10, implicit $x11 +... +--- +name: abdu_i8 +body: | + bb.0.entry: + liveins: $x10, $x11 + ; RV32I-LABEL: name: abdu_i8 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8 + ; RV32I-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 8 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s32), [[ASSERT_ZEXT1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: abdu_i8 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8 + ; RV32ZBB-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 8 + ; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UMIN]] + ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %3:_(s32) = G_ASSERT_ZEXT %1, 8 + %4:_(s32) = G_ASSERT_ZEXT %2, 8 + %5:_(s8) = G_TRUNC %3(s32) + %6:_(s8) = G_TRUNC %4(s32) + %7:_(s8) = G_ABDU %5, %6 + %8:_(s32) = G_ANYEXT %7(s8) + $x10 = COPY %8(s32) + PseudoRET implicit $x10 +... +--- +name: abdu_i16 +body: | + bb.0.entry: + liveins: $x10, $x11 + ; RV32I-LABEL: name: abdu_i16 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16 + ; RV32I-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 16 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s32), [[ASSERT_ZEXT1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: abdu_i16 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16 + ; RV32ZBB-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 16 + ; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UMIN]] + ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %3:_(s32) = G_ASSERT_ZEXT %1, 16 + %4:_(s32) = G_ASSERT_ZEXT %2, 16 + %5:_(s16) = G_TRUNC %3(s32) + %6:_(s16) = G_TRUNC %4(s32) + %7:_(s16) = G_ABDU %5, %6 + %8:_(s32) = G_ANYEXT %7(s16) + $x10 = COPY %8(s32) + PseudoRET implicit $x10 +... +--- +name: abdu_i32 +body: | + bb.0.entry: + liveins: $x10, $x11 + ; RV32I-LABEL: name: abdu_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: abdu_i32 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]] + ; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]] + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UMIN]] + ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %3:_(s32) = G_ABDU %1, %2 + $x10 = COPY %3(s32) + PseudoRET implicit $x10 +... +--- +name: abdu_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: abdu_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[COPY]] + ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]] + ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[ICMP1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[ICMP2]], [[ICMP3]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB]], [[SUB3]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB2]], [[SUB5]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $x10 + %4:_(s32) = COPY $x11 + %5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32) + %6:_(s64) = G_ABDU %2, %5 + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $x10 = COPY %7(s32) + $x11 = COPY %8(s32) + PseudoRET implicit $x10, implicit $x11 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv64.mir new file mode 100644 index 0000000..deb65d4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv64.mir @@ -0,0 +1,344 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=RV64I +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=RV64ZBB + +--- +name: abds_i8 +body: | + bb.0.entry: + liveins: $x10, $x11 + ; RV64I-LABEL: name: abds_i8 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 8 + ; RV64I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY1]], 8 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s64), [[ASSERT_SEXT1]] + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SUB1]](s64) + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: abds_i8 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 8 + ; RV64ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY1]], 8 + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SMAX]], [[SMIN]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = COPY $x11 + %3:_(s64) = G_ASSERT_SEXT %1, 8 + %4:_(s64) = G_ASSERT_SEXT %2, 8 + %5:_(s8) = G_TRUNC %3(s64) + %6:_(s8) = G_TRUNC %4(s64) + %7:_(s8) = G_ABDS %5, %6 + %8:_(s64) = G_ANYEXT %7(s8) + $x10 = COPY %8(s64) + PseudoRET implicit $x10 +... +--- +name: abds_i16 +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: abds_i16 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 16 + ; RV64I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY1]], 16 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s64), [[ASSERT_SEXT1]] + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SUB1]](s64) + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: abds_i16 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 16 + ; RV64ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY1]], 16 + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SMAX]], [[SMIN]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = COPY $x11 + %3:_(s64) = G_ASSERT_SEXT %1, 16 + %4:_(s64) = G_ASSERT_SEXT %2, 16 + %5:_(s16) = G_TRUNC %3(s64) + %6:_(s16) = G_TRUNC %4(s64) + %7:_(s16) = G_ABDS %5, %6 + %8:_(s64) = G_ANYEXT %7(s16) + $x10 = COPY %8(s64) + PseudoRET implicit $x10 +... +--- +name: abds_i32 +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: abds_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32 + ; RV64I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY1]], 32 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG]](s64) + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB1]], 32 + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG1]](s64) + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s64), [[ASSERT_SEXT1]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: abds_i32 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32 + ; RV64ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY1]], 32 + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[ASSERT_SEXT]], [[ASSERT_SEXT1]] + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SMAX]], [[SMIN]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = COPY $x11 + %3:_(s64) = G_ASSERT_SEXT %1, 32 + %4:_(s64) = G_ASSERT_SEXT %2, 32 + %5:_(s32) = G_TRUNC %3(s64) + %6:_(s32) = G_TRUNC %4(s64) + %7:_(s32) = G_ABDS %5, %6 + %8:_(s64) = G_ANYEXT %7(s32) + $x10 = COPY %8(s64) + PseudoRET implicit $x10 +... +--- +name: abds_i64 +body: | + bb.0.entry: + + ; RV64I-LABEL: name: abds_i64 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[COPY1]], [[COPY]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SUB]], [[SUB1]] + ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: abds_i64 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[COPY]], [[COPY1]] + ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[COPY]], [[COPY1]] + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SMAX]], [[SMIN]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = COPY $x11 + %3:_(s64) = G_ABDS %1, %2 + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... +--- +name: abdu_i8 +body: | + bb.0.entry: + liveins: $x10, $x11 + ; RV64I-LABEL: name: abdu_i8 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8 + ; RV64I-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY1]], 8 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s64), [[ASSERT_ZEXT1]] + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SUB1]](s64) + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: abdu_i8 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8 + ; RV64ZBB-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY1]], 8 + ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[UMAX]], [[UMIN]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = COPY $x11 + %3:_(s64) = G_ASSERT_ZEXT %1, 8 + %4:_(s64) = G_ASSERT_ZEXT %2, 8 + %5:_(s8) = G_TRUNC %3(s64) + %6:_(s8) = G_TRUNC %4(s64) + %7:_(s8) = G_ABDU %5, %6 + %8:_(s64) = G_ANYEXT %7(s8) + $x10 = COPY %8(s64) + PseudoRET implicit $x10 +... +--- +name: abdu_i16 +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: abdu_i16 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16 + ; RV64I-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY1]], 16 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s64), [[ASSERT_ZEXT1]] + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SUB1]](s64) + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: abdu_i16 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16 + ; RV64ZBB-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY1]], 16 + ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[UMAX]], [[UMIN]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = COPY $x11 + %3:_(s64) = G_ASSERT_ZEXT %1, 16 + %4:_(s64) = G_ASSERT_ZEXT %2, 16 + %5:_(s16) = G_TRUNC %3(s64) + %6:_(s16) = G_TRUNC %4(s64) + %7:_(s16) = G_ABDU %5, %6 + %8:_(s64) = G_ANYEXT %7(s16) + $x10 = COPY %8(s64) + PseudoRET implicit $x10 +... +--- +name: abdu_i32 +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: abdu_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32 + ; RV64I-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY1]], 32 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG]](s64) + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB1]], 32 + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG1]](s64) + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ASSERT_ZEXT]], 32 + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ASSERT_ZEXT1]], 32 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SEXT_INREG2]](s64), [[SEXT_INREG3]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: abdu_i32 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32 + ; RV64ZBB-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY1]], 32 + ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]] + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[UMAX]], [[UMIN]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = COPY $x11 + %3:_(s64) = G_ASSERT_ZEXT %1, 32 + %4:_(s64) = G_ASSERT_ZEXT %2, 32 + %5:_(s32) = G_TRUNC %3(s64) + %6:_(s32) = G_TRUNC %4(s64) + %7:_(s32) = G_ABDU %5, %6 + %8:_(s64) = G_ANYEXT %7(s32) + $x10 = COPY %8(s64) + PseudoRET implicit $x10 +... +--- +name: abdu_i64 +body: | + bb.0.entry: + + ; RV64I-LABEL: name: abdu_i64 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[COPY1]], [[COPY]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SUB]], [[SUB1]] + ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: abdu_i64 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[COPY]], [[COPY1]] + ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[COPY]], [[COPY1]] + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[UMAX]], [[UMIN]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = COPY $x11 + %3:_(s64) = G_ABDU %1, %2 + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv32.mir new file mode 100644 index 0000000..e64e786 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv32.mir @@ -0,0 +1,132 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32I +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o -\ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB + +--- +name: abs_i8 +body: | + bb.0.entry: + ; RV32I-LABEL: name: abs_i8 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C1]](s32) + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) + ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32) + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASSERT_ZEXT]], [[ASHR1]] + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR1]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C2]] + ; RV32I-NEXT: $x10 = COPY [[AND]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: abs_i8 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8 + ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ASSERT_ZEXT]], 8 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SEXT_INREG]] + ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SUB]] + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SMAX]], [[C1]] + ; RV32ZBB-NEXT: $x10 = COPY [[AND]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = G_ASSERT_ZEXT %1, 8 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s8) = G_ABS %0 + %4:_(s32) = G_ZEXT %3(s8) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: abs_i16 +body: | + bb.0.entry: + ; RV32I-LABEL: name: abs_i16 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ASSERT_SEXT]], [[C]](s32) + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASSERT_SEXT]], [[ASHR]] + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[XOR]], [[C1]](s32) + ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) + ; RV32I-NEXT: $x10 = COPY [[ASHR1]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: abs_i16 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[ASSERT_SEXT]] + ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASSERT_SEXT]], [[SUB]] + ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMAX]], 16 + ; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = G_ASSERT_SEXT %1, 16 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s16) = G_ABS %0 + %4:_(s32) = G_SEXT %3(s16) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: abs_i32 +body: | + bb.0.entry: + ; RV32I-LABEL: name: abs_i32 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]] + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]] + ; RV32I-NEXT: $x10 = COPY [[XOR]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: abs_i32 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY]] + ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[SUB]] + ; RV32ZBB-NEXT: $x10 = COPY [[SMAX]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_ABS %0 + $x10 = COPY %1(s32) + PseudoRET implicit $x10 +... +--- +name: abs_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: abs_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[ASHR]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[ASHR]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[ASHR]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[ASHR]] + ; CHECK-NEXT: $x10 = COPY [[XOR]](s32) + ; CHECK-NEXT: $x11 = COPY [[XOR1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %3:_(s64) = G_ABS %0 + %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) + $x10 = COPY %4(s32) + $x11 = COPY %5(s32) + PseudoRET implicit $x10, implicit $x11 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir new file mode 100644 index 0000000..a7c1c63 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir @@ -0,0 +1,135 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64I +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64ZBB + +--- +name: abs_i8 +body: | + bb.0.entry: + ; RV64I-LABEL: name: abs_i8 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[C1]](s64) + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64) + ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C]](s64) + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_ZEXT]], [[ASHR1]] + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR1]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C2]] + ; RV64I-NEXT: $x10 = COPY [[AND]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: abs_i8 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8 + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ASSERT_ZEXT]], 8 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[SEXT_INREG]] + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SUB]] + ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SMAX]], [[C1]] + ; RV64ZBB-NEXT: $x10 = COPY [[AND]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = G_ASSERT_ZEXT %1, 8 + %0:_(s8) = G_TRUNC %2(s64) + %3:_(s8) = G_ABS %0 + %4:_(s64) = G_ZEXT %3(s8) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: abs_i16 +body: | + bb.0.entry: + ; RV64I-LABEL: name: abs_i16 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 16 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[C]](s64) + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]] + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[XOR]], [[C1]](s64) + ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64) + ; RV64I-NEXT: $x10 = COPY [[ASHR1]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: abs_i16 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 16 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[ASSERT_SEXT]] + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASSERT_SEXT]], [[SUB]] + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 16 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = G_ASSERT_SEXT %1, 16 + %0:_(s16) = G_TRUNC %2(s64) + %3:_(s16) = G_ABS %0 + %4:_(s64) = G_SEXT %3(s16) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: abs_i32 +body: | + bb.0.entry: + ; RV64I-LABEL: name: abs_i32 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[C]](s64) + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[SEXT_INREG]], [[ASHR]] + ; RV64I-NEXT: $x10 = COPY [[XOR]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: abs_i32 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[ASSERT_SEXT]] + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASSERT_SEXT]], [[SUB]] + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = G_ASSERT_SEXT %1, 32 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s32) = G_ABS %0 + %4:_(s64) = G_SEXT %3(s32) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: abs_i64 +body: | + bb.0.entry: + ; RV64I-LABEL: name: abs_i64 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64) + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ASHR]] + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]] + ; RV64I-NEXT: $x10 = COPY [[XOR]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: abs_i64 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY]] + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[COPY]], [[SUB]] + ; RV64ZBB-NEXT: $x10 = COPY [[SMAX]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_ABS %0 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv32.mir new file mode 100644 index 0000000..b3c62df --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv32.mir @@ -0,0 +1,190 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: add_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_ADD %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: add_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_ADD %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: add_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_ADD %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: add_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_ADD %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: add_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i48 + ; CHECK: %xlo:_(s32) = COPY $x10 + ; CHECK-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD %xlo, %ylo + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), %ylo + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD %xhi, %yhi + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32) + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s48) = G_ADD %x, %y + %z0:_(s64) = G_ANYEXT %z(s48) + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: add_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i64 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD %lo1, %lo2 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), %lo2 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD %hi1, %hi2 + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32) + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_ADD %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: add_i96 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i96 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s32) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x13 + ; CHECK-NEXT: %mid2:_(s32) = COPY $x14 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x15 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD %lo1, %lo2 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), %lo2 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD %mid1, %mid2 + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), %mid1 + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD2]](s32), [[C]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32) + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD %hi1, %hi2 + ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[OR]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD4]](s32) + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: $x12 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s32) = COPY $x10 + %mid1:_(s32) = COPY $x11 + %hi1:_(s32) = COPY $x12 + %lo2:_(s32) = COPY $x13 + %mid2:_(s32) = COPY $x14 + %hi2:_(s32) = COPY $x15 + %x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32) + %x2:_(s96) = G_MERGE_VALUES %lo2(s32), %mid2(s32), %hi2(s32) + %y:_(s96) = G_ADD %x1, %x2 + %lo:_(s32), %mid:_(s32), %hi:_(s32) = G_UNMERGE_VALUES %y(s96) + $x10 = COPY %lo(s32) + $x11 = COPY %mid(s32) + $x12 = COPY %hi(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir new file mode 100644 index 0000000..8f2b9f3 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir @@ -0,0 +1,211 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: add_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_ADD %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: add_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_ADD %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: add_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_ADD %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: add_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_ADD %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: add_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_ADD %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: add_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i72 + ; CHECK: %x00:_(s64) = COPY $x10 + ; CHECK-NEXT: %x01:_(s64) = COPY $x11 + ; CHECK-NEXT: %y00:_(s64) = COPY $x12 + ; CHECK-NEXT: %y01:_(s64) = COPY $x13 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD %x00, %y00 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), %y00 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[ADD]](s64) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD %x01, %y01 + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ADD2]](s64) + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %x00:_(s64) = COPY $x10 + %x01:_(s64) = COPY $x11 + %y00:_(s64) = COPY $x12 + %y01:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %x00(s64), %x01 + %y0:_(s128) = G_MERGE_VALUES %y00(s64), %y01 + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s72) = G_ADD %x, %y + %z0:_(s128) = G_ANYEXT %z(s72) + %z00:_(s64), %z01:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %z00(s64) + $x11 = COPY %z01(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: add_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i128 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD %lo1, %lo2 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), %lo2 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[ADD]](s64) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD %hi1, %hi2 + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ADD2]](s64) + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_ADD %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: add_i192 +body: | + bb.0.entry: + ; CHECK-LABEL: name: add_i192 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s64) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x13 + ; CHECK-NEXT: %mid2:_(s64) = COPY $x14 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x15 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD %lo1, %lo2 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), %lo2 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[ADD]](s64) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD %mid1, %mid2 + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD1]](s64), %mid1 + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ADD2]](s64), [[C]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP2]], [[ICMP]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ICMP1]], [[AND]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ADD2]](s64) + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s64) = G_ADD %hi1, %hi2 + ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s64) = G_ADD [[ADD3]], [[OR]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ADD4]](s64) + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-NEXT: $x12 = COPY [[COPY2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s64) = COPY $x10 + %mid1:_(s64) = COPY $x11 + %hi1:_(s64) = COPY $x12 + %lo2:_(s64) = COPY $x13 + %mid2:_(s64) = COPY $x14 + %hi2:_(s64) = COPY $x15 + %x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64) + %x2:_(s192) = G_MERGE_VALUES %lo2(s64), %mid2(s64), %hi2(s64) + %y:_(s192) = G_ADD %x1, %x2 + %lo:_(s64), %mid:_(s64), %hi:_(s64) = G_UNMERGE_VALUES %y(s192) + $x10 = COPY %lo(s64) + $x11 = COPY %mid(s64) + $x12 = COPY %hi(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir new file mode 100644 index 0000000..35f2011 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir @@ -0,0 +1,553 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: saddo_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: saddo_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8), %5:_(s1) = G_SADDO %0, %1 + %6:_(s32) = G_ANYEXT %4(s8) + %7:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %6(s32) + $x11 = COPY %7(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: saddo_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: saddo_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16), %5:_(s1) = G_SADDO %0, %1 + %6:_(s32) = G_ANYEXT %4(s16) + %7:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %6(s32) + $x11 = COPY %7(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: saddo_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: saddo_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ADD]](s32), [[COPY]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[C]] + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP1]], [[ICMP]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: $x11 = COPY [[XOR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32), %3:_(s1) = G_SADDO %0, %1 + %4:_(s32) = G_ANYEXT %3(s1) + $x10 = COPY %2(s32) + $x11 = COPY %4(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: saddo_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13 + + ; CHECK-LABEL: name: saddo_i64 + ; CHECK: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY2]] + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32) + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[COPY]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY5]](s32), [[COPY1]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY5]](s32), [[COPY1]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY3]](s32), [[C]] + ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[ICMP4]], [[ICMP5]] + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[SELECT]] + ; CHECK-NEXT: $x10 = COPY [[COPY4]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY5]](s32) + ; CHECK-NEXT: $x12 = COPY [[XOR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64), %7:_(s1) = G_SADDO %0, %1 + %8:_(s32), %9:_(s32) = G_UNMERGE_VALUES %6(s64) + %10:_(s32) = G_ANYEXT %7(s1) + $x10 = COPY %8(s32) + $x11 = COPY %9(s32) + $x12 = COPY %10(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... +--- +name: ssubo_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ssubo_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8), %5:_(s1) = G_SSUBO %0, %1 + %6:_(s32) = G_ANYEXT %4(s8) + %7:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %6(s32) + $x11 = COPY %7(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssubo_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ssubo_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16), %5:_(s1) = G_SSUBO %0, %1 + %6:_(s32) = G_ANYEXT %4(s16) + %7:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %6(s32) + $x11 = COPY %7(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssubo_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ssubo_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB]](s32), [[C]] + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: $x11 = COPY [[XOR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32), %3:_(s1) = G_SSUBO %0, %1 + %4:_(s32) = G_ANYEXT %3(s1) + $x10 = COPY %2(s32) + $x11 = COPY %4(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssubo_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13 + + ; CHECK-LABEL: name: ssubo_i64 + ; CHECK: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB2]](s32), [[C]] + ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB2]](s32), [[C]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[ICMP4]], [[ICMP5]] + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SELECT]], [[SELECT1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: $x11 = COPY [[SUB2]](s32) + ; CHECK-NEXT: $x12 = COPY [[XOR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64), %7:_(s1) = G_SSUBO %0, %1 + %8:_(s32), %9:_(s32) = G_UNMERGE_VALUES %6(s64) + %10:_(s32) = G_ANYEXT %7(s1) + $x10 = COPY %8(s32) + $x11 = COPY %9(s32) + $x12 = COPY %10(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... +--- +name: uaddo_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: uaddo_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8), %5:_(s1) = G_UADDO %0, %1 + %6:_(s32) = G_ANYEXT %4(s8) + %7:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %6(s32) + $x11 = COPY %7(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uaddo_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: uaddo_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16), %5:_(s1) = G_UADDO %0, %1 + %6:_(s32) = G_ANYEXT %4(s16) + %7:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %6(s32) + $x11 = COPY %7(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uaddo_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: uaddo_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32), %3:_(s1) = G_UADDO %0, %1 + %4:_(s32) = G_ANYEXT %3(s1) + $x10 = COPY %2(s32) + $x11 = COPY %4(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uaddo_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13 + + ; CHECK-LABEL: name: uaddo_i64 + ; CHECK: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY2]] + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32) + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[COPY2]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY5]](s32), [[COPY3]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY5]](s32), [[COPY3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]] + ; CHECK-NEXT: $x10 = COPY [[COPY4]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY5]](s32) + ; CHECK-NEXT: $x12 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64), %7:_(s1) = G_UADDO %0, %1 + %8:_(s32), %9:_(s32) = G_UNMERGE_VALUES %6(s64) + %10:_(s32) = G_ANYEXT %7(s1) + $x10 = COPY %8(s32) + $x11 = COPY %9(s32) + $x12 = COPY %10(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... +--- +name: usubo_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: usubo_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8), %5:_(s1) = G_USUBO %0, %1 + %6:_(s32) = G_ANYEXT %4(s8) + %7:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %6(s32) + $x11 = COPY %7(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: usubo_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: usubo_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16), %5:_(s1) = G_USUBO %0, %1 + %6:_(s32) = G_ANYEXT %4(s16) + %7:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %6(s32) + $x11 = COPY %7(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: usubo_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: usubo_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32), %3:_(s1) = G_USUBO %0, %1 + %4:_(s32) = G_ANYEXT %3(s1) + $x10 = COPY %2(s32) + $x11 = COPY %4(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: usubo_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13 + + ; CHECK-LABEL: name: usubo_i64 + ; CHECK: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: $x11 = COPY [[SUB2]](s32) + ; CHECK-NEXT: $x12 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64), %7:_(s1) = G_USUBO %0, %1 + %8:_(s32), %9:_(s32) = G_UNMERGE_VALUES %6(s64) + %10:_(s32) = G_ANYEXT %7(s1) + $x10 = COPY %8(s32) + $x11 = COPY %9(s32) + $x12 = COPY %10(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir new file mode 100644 index 0000000..22fe335 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir @@ -0,0 +1,500 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: saddo_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: saddo_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ADD]], [[C]](s64) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[ADD]](s64), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s64) + %4:_(s8), %5:_(s1) = G_SADDO %0, %1 + %6:_(s64) = G_ANYEXT %4(s8) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: saddo_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: saddo_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ADD]], [[C]](s64) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[ADD]](s64), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s64) + %4:_(s16), %5:_(s1) = G_SADDO %0, %1 + %6:_(s64) = G_ANYEXT %4(s16) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: saddo_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: saddo_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]] + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[ADD]](s64), [[SEXT_INREG2]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32), %5:_(s1) = G_SADDO %0, %1 + %6:_(s64) = G_ANYEXT %4(s32) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: saddo_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: saddo_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[ADD]](s64), [[COPY]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[COPY1]](s64), [[C]] + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ICMP1]], [[ICMP]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ADD]](s64) + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-NEXT: $x11 = COPY [[XOR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64), %3:_(s1) = G_SADDO %0, %1 + %4:_(s64) = G_ANYEXT %3(s1) + $x10 = COPY %2(s64) + $x11 = COPY %4(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssubo_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ssubo_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SUB]], [[C]](s64) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[SUB]](s64), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s64) + %4:_(s8), %5:_(s1) = G_SSUBO %0, %1 + %6:_(s64) = G_ANYEXT %4(s8) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssubo_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ssubo_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SUB]], [[C]](s64) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[SUB]](s64), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s64) + %4:_(s16), %5:_(s1) = G_SSUBO %0, %1 + %6:_(s64) = G_ANYEXT %4(s16) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssubo_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ssubo_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]] + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[SUB]](s64), [[SEXT_INREG2]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32), %5:_(s1) = G_SSUBO %0, %1 + %6:_(s64) = G_ANYEXT %4(s32) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssubo_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ssubo_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SUB]](s64), [[C]] + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SUB]](s64) + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-NEXT: $x11 = COPY [[XOR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64), %3:_(s1) = G_SSUBO %0, %1 + %4:_(s64) = G_ANYEXT %3(s1) + $x10 = COPY %2(s64) + $x11 = COPY %4(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uaddo_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: uaddo_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s64) + %4:_(s8), %5:_(s1) = G_UADDO %0, %1 + %6:_(s64) = G_ANYEXT %4(s8) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uaddo_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: uaddo_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s64) + %4:_(s16), %5:_(s1) = G_UADDO %0, %1 + %6:_(s64) = G_ANYEXT %4(s16) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uaddo_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: uaddo_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32), %5:_(s1) = G_UADDO %0, %1 + %6:_(s64) = G_ANYEXT %4(s32) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uaddo_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: uaddo_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), [[COPY1]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ADD]](s64) + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64), %3:_(s1) = G_UADDO %0, %1 + %4:_(s64) = G_ANYEXT %3(s1) + $x10 = COPY %2(s64) + $x11 = COPY %4(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: usubo_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: usubo_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s64) + %4:_(s8), %5:_(s1) = G_USUBO %0, %1 + %6:_(s64) = G_ANYEXT %4(s8) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: usubo_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: usubo_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s64) + %4:_(s16), %5:_(s1) = G_USUBO %0, %1 + %6:_(s64) = G_ANYEXT %4(s16) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: usubo_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: usubo_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG1]](s64), [[SEXT_INREG2]] + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32), %5:_(s1) = G_USUBO %0, %1 + %6:_(s64) = G_ANYEXT %4(s32) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: usubo_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: usubo_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64), %3:_(s1) = G_USUBO %0, %1 + %4:_(s64) = G_ANYEXT %3(s1) + $x10 = COPY %2(s64) + $x11 = COPY %4(s64) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-and-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-and-rv32.mir new file mode 100644 index 0000000..d5c13f4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-and-rv32.mir @@ -0,0 +1,171 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: and_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_AND %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: and_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_AND %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: and_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_AND %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: and_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_AND %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: and_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i48 + ; CHECK: %xlo:_(s32) = COPY $x10 + ; CHECK-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %xlo, %ylo + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xhi, %yhi + ; CHECK-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s48) = G_AND %x, %y + %z0:_(s64) = G_ANYEXT %z(s48) + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: and_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i64 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %lo1, %lo2 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %hi1, %hi2 + ; CHECK-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_AND %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: and_i96 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i96 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s32) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x13 + ; CHECK-NEXT: %mid2:_(s32) = COPY $x14 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x15 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %lo1, %lo2 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %mid1, %mid2 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %hi1, %hi2 + ; CHECK-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-NEXT: $x12 = COPY [[AND2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s32) = COPY $x10 + %mid1:_(s32) = COPY $x11 + %hi1:_(s32) = COPY $x12 + %lo2:_(s32) = COPY $x13 + %mid2:_(s32) = COPY $x14 + %hi2:_(s32) = COPY $x15 + %x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32) + %x2:_(s96) = G_MERGE_VALUES %lo2(s32), %mid2(s32), %hi2(s32) + %y:_(s96) = G_AND %x1, %x2 + %lo:_(s32), %mid:_(s32), %hi:_(s32) = G_UNMERGE_VALUES %y(s96) + $x10 = COPY %lo(s32) + $x11 = COPY %mid(s32) + $x12 = COPY %hi(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-and-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-and-rv64.mir new file mode 100644 index 0000000..f7802eb --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-and-rv64.mir @@ -0,0 +1,191 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: and_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_AND %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: and_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_AND %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: and_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_AND %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: and_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_AND %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: and_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_AND %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: and_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i72 + ; CHECK: %x00:_(s64) = COPY $x10 + ; CHECK-NEXT: %x01:_(s64) = COPY $x11 + ; CHECK-NEXT: %y00:_(s64) = COPY $x12 + ; CHECK-NEXT: %y01:_(s64) = COPY $x13 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %x00, %y00 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %x01, %y01 + ; CHECK-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %x00:_(s64) = COPY $x10 + %x01:_(s64) = COPY $x11 + %y00:_(s64) = COPY $x12 + %y01:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %x00(s64), %x01 + %y0:_(s128) = G_MERGE_VALUES %y00(s64), %y01 + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s72) = G_AND %x, %y + %z0:_(s128) = G_ANYEXT %z(s72) + %z00:_(s64), %z01:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %z00(s64) + $x11 = COPY %z01(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: and_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i128 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %lo1, %lo2 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %hi1, %hi2 + ; CHECK-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_AND %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: and_i192 +body: | + bb.0.entry: + ; CHECK-LABEL: name: and_i192 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s64) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x13 + ; CHECK-NEXT: %mid2:_(s64) = COPY $x14 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x15 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %lo1, %lo2 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %mid1, %mid2 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %hi1, %hi2 + ; CHECK-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-NEXT: $x12 = COPY [[AND2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s64) = COPY $x10 + %mid1:_(s64) = COPY $x11 + %hi1:_(s64) = COPY $x12 + %lo2:_(s64) = COPY $x13 + %mid2:_(s64) = COPY $x14 + %hi2:_(s64) = COPY $x15 + %x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64) + %x2:_(s192) = G_MERGE_VALUES %lo2(s64), %mid2(s64), %hi2(s64) + %y:_(s192) = G_AND %x1, %x2 + %lo:_(s64), %mid:_(s64), %hi:_(s64) = G_UNMERGE_VALUES %y(s192) + $x10 = COPY %lo(s64) + $x11 = COPY %mid(s64) + $x12 = COPY %hi(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv32.mir new file mode 100644 index 0000000..e5ac59c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv32.mir @@ -0,0 +1,272 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: ashr_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32) + ; CHECK-NEXT: $x10 = COPY [[ASHR1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_ASHR %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: ashr_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32) + ; CHECK-NEXT: $x10 = COPY [[ASHR1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_ASHR %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: ashr_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32) + ; CHECK-NEXT: $x10 = COPY [[ASHR1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_ASHR %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: ashr_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: $x10 = COPY [[ASHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_ASHR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: ashr_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i48 + ; CHECK: %xlo:_(s32) = COPY $x10 + ; CHECK-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C1]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %ylo, [[C2]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], %ylo + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %ylo(s32), [[C2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %ylo(s32), [[C3]] + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], %ylo(s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %xlo, %ylo(s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ASHR]], [[SUB1]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]] + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32) + ; CHECK-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[SUB]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[ASHR3]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %xlo, [[SELECT]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ASHR1]], [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s48) = G_ASHR %x, %y + %z0:_(s64) = G_ANYEXT %z(s48) + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ashr_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i64 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], %lo2 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C1]] + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %hi1, %lo2(s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %lo1, %lo2(s32) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %hi1, [[SUB1]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR %hi1, [[C2]](s32) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR %hi1, [[SUB]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[ASHR2]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %lo1, [[SELECT]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_ASHR %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ashr_i96 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i96 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s32) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %hi1, [[C]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C2]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], %lo2 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C1]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C3]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], %lo2 + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C3]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %hi1, %lo2(s32) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASHR]], [[SUB3]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[SUB2]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR]], [[ASHR1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), %hi1, [[SELECT]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C3]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR %mid1, %lo2(s32) + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %lo1, %lo2(s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %mid1, [[SUB3]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR %mid1, [[SUB2]](s32) + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[OR1]], [[LSHR3]] + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), %lo1, [[SELECT2]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[LSHR1]], [[C1]] + ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]] + ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB1]] + ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB1]](s32), [[C3]] + ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL %hi1, [[SUB1]](s32) + ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR %hi1, [[SUB5]](s32) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ASHR]], [[SUB1]](s32) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[SHL3]] + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %hi1, [[SUB4]](s32) + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[SHL2]], [[C1]] + ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[OR2]], [[SHL4]] + ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s32), [[ASHR]], [[SELECT6]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SELECT3]], [[SELECT5]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[SELECT4]], [[SELECT7]] + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32) + ; CHECK-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C3]] + ; CHECK-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB]] + ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C3]] + ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]] + ; CHECK-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[SUB]](s32) + ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR %hi1, [[SUB]](s32) + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ASHR]], [[SUB7]](s32) + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL5]] + ; CHECK-NEXT: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32) + ; CHECK-NEXT: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[SUB6]](s32) + ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[ICMP8]](s32), [[OR5]], [[ASHR5]] + ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s32) = G_SELECT [[ICMP9]](s32), %hi1, [[SELECT8]] + ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s32) = G_SELECT [[ICMP8]](s32), [[ASHR3]], [[ASHR4]] + ; CHECK-NEXT: [[SELECT11:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR3]], [[SELECT9]] + ; CHECK-NEXT: [[SELECT12:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR4]], [[SELECT10]] + ; CHECK-NEXT: [[SELECT13:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %lo1, [[SELECT11]] + ; CHECK-NEXT: [[SELECT14:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %mid1, [[SELECT12]] + ; CHECK-NEXT: [[SELECT15:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SELECT1]], [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[SELECT13]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT14]](s32) + ; CHECK-NEXT: $x12 = COPY [[SELECT15]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s32) = COPY $x10 + %mid1:_(s32) = COPY $x11 + %hi1:_(s32) = COPY $x12 + %lo2:_(s32) = COPY $x13 + %mid2:_(s32) = COPY $x14 + %hi2:_(s32) = COPY $x15 + %x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32) + %x2:_(s96) = G_MERGE_VALUES %lo2(s32), %mid2(s32), %hi2(s32) + %y:_(s96) = G_ASHR %x1, %x2 + %lo:_(s32), %mid:_(s32), %hi:_(s32) = G_UNMERGE_VALUES %y(s96) + $x10 = COPY %lo(s32) + $x11 = COPY %mid(s32) + $x12 = COPY %hi(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir new file mode 100644 index 0000000..0d097a5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir @@ -0,0 +1,321 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: ashr_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C1]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[ASHR1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_ASHR %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: ashr_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 49 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C1]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[ASHR1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_ASHR %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: ashr_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C1]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[ASHR1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_ASHR %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: ashr_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SRAW:%[0-9]+]]:_(s64) = G_SRAW [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SRAW]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_ASHR %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: ashr_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: $x10 = COPY [[ASHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_ASHR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: ashr_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i72 + ; CHECK: %x00:_(s64) = COPY $x10 + ; CHECK-NEXT: %x01:_(s64) = COPY $x11 + ; CHECK-NEXT: %y00:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %x01, [[C1]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %y00, [[C2]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C2]], %y00 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %y00(s64), [[C2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %y00(s64), [[C3]] + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], %y00(s64) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR %x00, %y00(s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ASHR]], [[SUB1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]] + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C]](s64) + ; CHECK-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[SUB]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR]], [[ASHR3]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %x00, [[SELECT]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[ASHR1]], [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s64) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %x00:_(s64) = COPY $x10 + %x01:_(s64) = COPY $x11 + %y00:_(s64) = COPY $x12 + %y01:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %x00(s64), %x01 + %y0:_(s128) = G_MERGE_VALUES %y00(s64), %y01 + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s72) = G_ASHR %x, %y + %z0:_(s128) = G_ANYEXT %z(s72) + %z00:_(s64), %z01:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %z00(s64) + $x11 = COPY %z01(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ashr_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i128 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C]], %lo2 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C1]] + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR %hi1, %lo2(s64) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR %lo1, %lo2(s64) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %hi1, [[SUB1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR %hi1, [[C2]](s64) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR %hi1, [[SUB]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR]], [[ASHR2]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %lo1, [[SELECT]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s64) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_ASHR %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ashr_i192 +body: | + bb.0.entry: + ; CHECK-LABEL: name: ashr_i192 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s64) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR %hi1, [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 128 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C1]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C1]], %lo2 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C1]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C2]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C3]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s64) = G_SUB [[C3]], %lo2 + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C3]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR %hi1, %lo2(s64) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASHR]], [[SUB3]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[SUB2]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s64), [[OR]], [[ASHR1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s64), %hi1, [[SELECT]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C3]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C2]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR %mid1, %lo2(s64) + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR %lo1, %lo2(s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %mid1, [[SUB3]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[SHL1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR %mid1, [[SUB2]](s64) + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s64), [[OR1]], [[LSHR3]] + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s64), %lo1, [[SELECT2]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s64), [[LSHR1]], [[C2]] + ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C3]] + ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s64) = G_SUB [[C3]], [[SUB1]] + ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB1]](s64), [[C3]] + ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C2]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL %hi1, [[SUB1]](s64) + ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR %hi1, [[SUB5]](s64) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[ASHR]], [[SUB1]](s64) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL3]] + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL %hi1, [[SUB4]](s64) + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s64), [[SHL2]], [[C2]] + ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s64), [[OR2]], [[SHL4]] + ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s64), [[ASHR]], [[SELECT6]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT3]], [[SELECT5]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT7]] + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C]](s64) + ; CHECK-NEXT: [[SUB6:%[0-9]+]]:_(s64) = G_SUB [[SUB]], [[C3]] + ; CHECK-NEXT: [[SUB7:%[0-9]+]]:_(s64) = G_SUB [[C3]], [[SUB]] + ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB]](s64), [[C3]] + ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB]](s64), [[C2]] + ; CHECK-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[SUB]](s64) + ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR %hi1, [[SUB]](s64) + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[ASHR]], [[SUB7]](s64) + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR5]], [[SHL5]] + ; CHECK-NEXT: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C]](s64) + ; CHECK-NEXT: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[SUB6]](s64) + ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s64), [[OR5]], [[ASHR5]] + ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s64), %hi1, [[SELECT8]] + ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s64), [[ASHR3]], [[ASHR4]] + ; CHECK-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR3]], [[SELECT9]] + ; CHECK-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR4]], [[SELECT10]] + ; CHECK-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %lo1, [[SELECT11]] + ; CHECK-NEXT: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %mid1, [[SELECT12]] + ; CHECK-NEXT: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SELECT1]], [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[SELECT13]](s64) + ; CHECK-NEXT: $x11 = COPY [[SELECT14]](s64) + ; CHECK-NEXT: $x12 = COPY [[SELECT15]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s64) = COPY $x10 + %mid1:_(s64) = COPY $x11 + %hi1:_(s64) = COPY $x12 + %lo2:_(s64) = COPY $x13 + %mid2:_(s64) = COPY $x14 + %hi2:_(s64) = COPY $x15 + %x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64) + %x2:_(s192) = G_MERGE_VALUES %lo2(s64), %mid2(s64), %hi2(s64) + %y:_(s192) = G_ASHR %x1, %x2 + %lo:_(s64), %mid:_(s64), %hi:_(s64) = G_UNMERGE_VALUES %y(s192) + $x10 = COPY %lo(s64) + $x11 = COPY %mid(s64) + $x12 = COPY %hi(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... +--- +name: ashr_i48 +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ashr_i48 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[ASHR1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s48) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s48) = G_TRUNC %3(s64) + %4:_(s48) = G_ASHR %0, %1(s48) + %5:_(s64) = G_ANYEXT %4(s48) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomic-cmpxchg-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomic-cmpxchg-rv32.mir new file mode 100644 index 0000000..3f50bc7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomic-cmpxchg-rv32.mir @@ -0,0 +1,155 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+a,+zacas,+zabha -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=RV32IA-ZABHA +# RUN: llc -mtriple=riscv32 -mattr=+a -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=RV32IA + +--- +name: cmpxchg_i8 +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_i8 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-ZABHA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32IA-ZABHA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s8)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s32) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: cmpxchg_i8 + ; RV32IA: liveins: $x10 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32IA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s8)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s32) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s8) = G_CONSTANT i8 0 + %2:_(s8) = G_CONSTANT i8 1 + %3:_(s8) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s8)) + %4:_(s32) = G_ANYEXT %3 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_i16 +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_i16 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-ZABHA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32IA-ZABHA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s16)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s32) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: cmpxchg_i16 + ; RV32IA: liveins: $x10 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32IA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s16)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s32) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s16) = G_CONSTANT i16 0 + %2:_(s16) = G_CONSTANT i16 1 + %3:_(s16) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s16)) + %4:_(s32) = G_ANYEXT %3 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_i32 +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_i32 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-ZABHA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32IA-ZABHA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s32)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s32) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: cmpxchg_i32 + ; RV32IA: liveins: $x10 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32IA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s32)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s32) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s32) = G_CONSTANT i32 1 + %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s32)) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_with_success_i32 + +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_with_success_i32 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-ZABHA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32IA-ZABHA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s32)) + ; RV32IA-ZABHA-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ATOMIC_CMPXCHG]](s32), [[C]] + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ATOMIC_CMPXCHG]](s32) + ; RV32IA-ZABHA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32IA-ZABHA-NEXT: $x11 = COPY [[ICMP]](s32) + ; RV32IA-ZABHA-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV32IA-ZABHA-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-ZABHA-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[COPY2]](s32) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: cmpxchg_with_success_i32 + ; RV32IA: liveins: $x10 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32IA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s32)) + ; RV32IA-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ATOMIC_CMPXCHG]](s32), [[C]] + ; RV32IA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ATOMIC_CMPXCHG]](s32) + ; RV32IA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32IA-NEXT: $x11 = COPY [[ICMP]](s32) + ; RV32IA-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV32IA-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32IA-NEXT: $x10 = COPY [[COPY2]](s32) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s32) = G_CONSTANT i32 1 + %3:_(s32), %4:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS %0, %1, %2 :: (load store monotonic (s32)) + %5:_(s32) = G_ANYEXT %4 + %6:_(s32) = G_MUL %3, %5 + $x10 = COPY %6(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomic-cmpxchg-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomic-cmpxchg-rv64.mir new file mode 100644 index 0000000..6899982 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomic-cmpxchg-rv64.mir @@ -0,0 +1,240 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+a,+zacas,+zabha -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=RV32IA-ZABHA +# RUN: llc -mtriple=riscv64 -mattr=+a -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=RV32IA + +--- +name: cmpxchg_i8 +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_i8 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32IA-ZABHA-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32IA-ZABHA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s8)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s64) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: cmpxchg_i8 + ; RV32IA: liveins: $x10 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32IA-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32IA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s8)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s64) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s8) = G_CONSTANT i8 0 + %2:_(s8) = G_CONSTANT i8 1 + %3:_(s8) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s8)) + %4:_(s64) = G_ANYEXT %3 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_i16 +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_i16 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32IA-ZABHA-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32IA-ZABHA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s16)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s64) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: cmpxchg_i16 + ; RV32IA: liveins: $x10 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32IA-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32IA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s16)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s64) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s16) = G_CONSTANT i16 0 + %2:_(s16) = G_CONSTANT i16 1 + %3:_(s16) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s16)) + %4:_(s64) = G_ANYEXT %3 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_i32 +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_i32 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32IA-ZABHA-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32IA-ZABHA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s32)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s64) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: cmpxchg_i32 + ; RV32IA: liveins: $x10 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32IA-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32IA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s32)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s64) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s32) = G_CONSTANT i32 1 + %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s32)) + %4:_(s64) = G_ANYEXT %3 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_i64 +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_i64 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32IA-ZABHA-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32IA-ZABHA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s64)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s64) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: cmpxchg_i64 + ; RV32IA: liveins: $x10 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32IA-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32IA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s64)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s64) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_CONSTANT i64 0 + %2:_(s64) = G_CONSTANT i64 1 + %3:_(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s64)) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_with_success_i32 + +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_with_success_i32 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32IA-ZABHA-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32IA-ZABHA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s32)) + ; RV32IA-ZABHA-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ATOMIC_CMPXCHG]], 32 + ; RV32IA-ZABHA-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SEXT_INREG]](s64), [[C]] + ; RV32IA-ZABHA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s64) + ; RV32IA-ZABHA-NEXT: $x11 = COPY [[ICMP]](s64) + ; RV32IA-ZABHA-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV32IA-ZABHA-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[COPY1]](s64) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: cmpxchg_with_success_i32 + ; RV32IA: liveins: $x10 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32IA-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32IA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s32)) + ; RV32IA-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ATOMIC_CMPXCHG]], 32 + ; RV32IA-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SEXT_INREG]](s64), [[C]] + ; RV32IA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-NEXT: $x10 = COPY [[ATOMIC_CMPXCHG]](s64) + ; RV32IA-NEXT: $x11 = COPY [[ICMP]](s64) + ; RV32IA-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV32IA-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; RV32IA-NEXT: $x10 = COPY [[COPY1]](s64) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s32) = G_CONSTANT i32 1 + %3:_(s32), %4:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS %0, %1, %2 :: (load store monotonic (s32)) + %5:_(s32) = G_ANYEXT %4 + %6:_(s32) = G_MUL %3, %5 + %7:_(s64) = G_ANYEXT %6 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... +--- +name: cmpxchg_with_success_i64 + +body: | + bb.0: + liveins: $x10 + + ; RV32IA-ZABHA-LABEL: name: cmpxchg_with_success_i64 + ; RV32IA-ZABHA: liveins: $x10 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32IA-ZABHA-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32IA-ZABHA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s64)) + ; RV32IA-ZABHA-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ATOMIC_CMPXCHG]](s64), [[C]] + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ATOMIC_CMPXCHG]](s64) + ; RV32IA-ZABHA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[COPY1]](s64) + ; RV32IA-ZABHA-NEXT: $x11 = COPY [[ICMP]](s64) + ; RV32IA-ZABHA-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV32IA-ZABHA-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-ZABHA-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[COPY2]](s64) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: cmpxchg_with_success_i64 + ; RV32IA: liveins: $x10 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32IA-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32IA-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s64)) + ; RV32IA-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ATOMIC_CMPXCHG]](s64), [[C]] + ; RV32IA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ATOMIC_CMPXCHG]](s64) + ; RV32IA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-NEXT: $x10 = COPY [[COPY1]](s64) + ; RV32IA-NEXT: $x11 = COPY [[ICMP]](s64) + ; RV32IA-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV32IA-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32IA-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; RV32IA-NEXT: $x10 = COPY [[COPY2]](s64) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_CONSTANT i64 0 + %2:_(s64) = G_CONSTANT i64 1 + %3:_(s64), %4:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS %0, %1, %2 :: (load store monotonic (s64)) + %5:_(s64) = G_ANYEXT %4 + %6:_(s64) = G_MUL %3, %5 + $x10 = COPY %6(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv32.mir new file mode 100644 index 0000000..ecff2e6 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv32.mir @@ -0,0 +1,198 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+a,+zabha -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=RV32IA-ZABHA +# RUN: llc -mtriple=riscv32 -mattr=+a -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=RV32IA + +--- +name: atomicrmw_add_i8_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32IA-ZABHA-LABEL: name: atomicrmw_add_i8_monotonic + ; RV32IA-ZABHA: liveins: $x10, $x11 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s8)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s32) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: atomicrmw_add_i8_monotonic + ; RV32IA: liveins: $x10, $x11 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s8)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s32) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %1(s32) + %3:_(s8) = G_ATOMICRMW_ADD %0(p0), %2 :: (load store monotonic (s8)) + %4:_(s32) = G_ANYEXT %3(s8) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_add_i16_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32IA-ZABHA-LABEL: name: atomicrmw_add_i16_monotonic + ; RV32IA-ZABHA: liveins: $x10, $x11 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s16)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s32) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: atomicrmw_add_i16_monotonic + ; RV32IA: liveins: $x10, $x11 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s16)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s32) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %1(s32) + %3:_(s16) = G_ATOMICRMW_ADD %0(p0), %2 :: (load store monotonic (s16)) + %4:_(s32) = G_ANYEXT %3(s16) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_add_i32_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32IA-ZABHA-LABEL: name: atomicrmw_add_i32_monotonic + ; RV32IA-ZABHA: liveins: $x10, $x11 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s32)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s32) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: atomicrmw_add_i32_monotonic + ; RV32IA: liveins: $x10, $x11 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s32)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s32) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_ATOMICRMW_ADD %0(p0), %1 :: (load store monotonic (s32)) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i8_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32IA-ZABHA-LABEL: name: atomicrmw_sub_i8_monotonic + ; RV32IA-ZABHA: liveins: $x10, $x11 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-ZABHA-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; RV32IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s8)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s32) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: atomicrmw_sub_i8_monotonic + ; RV32IA: liveins: $x10, $x11 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; RV32IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s8)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s32) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %1(s32) + %3:_(s8) = G_ATOMICRMW_SUB %0(p0), %2 :: (load store monotonic (s8)) + %4:_(s32) = G_ANYEXT %3(s8) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i16_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32IA-ZABHA-LABEL: name: atomicrmw_sub_i16_monotonic + ; RV32IA-ZABHA: liveins: $x10, $x11 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-ZABHA-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; RV32IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s16)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s32) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: atomicrmw_sub_i16_monotonic + ; RV32IA: liveins: $x10, $x11 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; RV32IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s16)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s32) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %1(s32) + %3:_(s16) = G_ATOMICRMW_SUB %0(p0), %2 :: (load store monotonic (s16)) + %4:_(s32) = G_ANYEXT %3(s16) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i32_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32IA-ZABHA-LABEL: name: atomicrmw_sub_i32_monotonic + ; RV32IA-ZABHA: liveins: $x10, $x11 + ; RV32IA-ZABHA-NEXT: {{ $}} + ; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-ZABHA-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; RV32IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s32)) + ; RV32IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s32) + ; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV32IA-LABEL: name: atomicrmw_sub_i32_monotonic + ; RV32IA: liveins: $x10, $x11 + ; RV32IA-NEXT: {{ $}} + ; RV32IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32IA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32IA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32IA-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; RV32IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s32)) + ; RV32IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s32) + ; RV32IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_ATOMICRMW_SUB %0(p0), %1 :: (load store monotonic (s32)) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv64.mir new file mode 100644 index 0000000..0d7bd5f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv64.mir @@ -0,0 +1,264 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+a,+zabha -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=RV64IA-ZABHA +# RUN: llc -mtriple=riscv64 -mattr=+a -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=RV64IA + +--- +name: atomicrmw_add_i8_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64IA-ZABHA-LABEL: name: atomicrmw_add_i8_monotonic + ; RV64IA-ZABHA: liveins: $x10, $x11 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s8)) + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV64IA-LABEL: name: atomicrmw_add_i8_monotonic + ; RV64IA: liveins: $x10, $x11 + ; RV64IA-NEXT: {{ $}} + ; RV64IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s8)) + ; RV64IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %1(s64) + %3:_(s8) = G_ATOMICRMW_ADD %0(p0), %2 :: (load store monotonic (s8)) + %4:_(s64) = G_ANYEXT %3(s8) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_add_i16_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64IA-ZABHA-LABEL: name: atomicrmw_add_i16_monotonic + ; RV64IA-ZABHA: liveins: $x10, $x11 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s16)) + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV64IA-LABEL: name: atomicrmw_add_i16_monotonic + ; RV64IA: liveins: $x10, $x11 + ; RV64IA-NEXT: {{ $}} + ; RV64IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s16)) + ; RV64IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %1(s64) + %3:_(s16) = G_ATOMICRMW_ADD %0(p0), %2 :: (load store monotonic (s16)) + %4:_(s64) = G_ANYEXT %3(s16) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_add_i32_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64IA-ZABHA-LABEL: name: atomicrmw_add_i32_monotonic + ; RV64IA-ZABHA: liveins: $x10, $x11 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s32)) + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV64IA-LABEL: name: atomicrmw_add_i32_monotonic + ; RV64IA: liveins: $x10, $x11 + ; RV64IA-NEXT: {{ $}} + ; RV64IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s32)) + ; RV64IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %1(s64) + %3:_(s32) = G_ATOMICRMW_ADD %0(p0), %2 :: (load store monotonic (s32)) + %4:_(s64) = G_ANYEXT %3(s32) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_add_i64_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64IA-ZABHA-LABEL: name: atomicrmw_add_i64_monotonic + ; RV64IA-ZABHA: liveins: $x10, $x11 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s64)) + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV64IA-LABEL: name: atomicrmw_add_i64_monotonic + ; RV64IA: liveins: $x10, $x11 + ; RV64IA-NEXT: {{ $}} + ; RV64IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[COPY1]] :: (load store monotonic (s64)) + ; RV64IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_ATOMICRMW_ADD %0(p0), %1 :: (load store monotonic (s64)) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i8_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64IA-ZABHA-LABEL: name: atomicrmw_sub_i8_monotonic + ; RV64IA-ZABHA: liveins: $x10, $x11 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64IA-ZABHA-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s8)) + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV64IA-LABEL: name: atomicrmw_sub_i8_monotonic + ; RV64IA: liveins: $x10, $x11 + ; RV64IA-NEXT: {{ $}} + ; RV64IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64IA-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s8)) + ; RV64IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %1(s64) + %3:_(s8) = G_ATOMICRMW_SUB %0(p0), %2 :: (load store monotonic (s8)) + %4:_(s64) = G_ANYEXT %3(s8) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i16_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64IA-ZABHA-LABEL: name: atomicrmw_sub_i16_monotonic + ; RV64IA-ZABHA: liveins: $x10, $x11 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64IA-ZABHA-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s16)) + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV64IA-LABEL: name: atomicrmw_sub_i16_monotonic + ; RV64IA: liveins: $x10, $x11 + ; RV64IA-NEXT: {{ $}} + ; RV64IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64IA-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s16)) + ; RV64IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %1(s64) + %3:_(s16) = G_ATOMICRMW_SUB %0(p0), %2 :: (load store monotonic (s16)) + %4:_(s64) = G_ANYEXT %3(s16) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i32_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64IA-ZABHA-LABEL: name: atomicrmw_sub_i32_monotonic + ; RV64IA-ZABHA: liveins: $x10, $x11 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64IA-ZABHA-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s32)) + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV64IA-LABEL: name: atomicrmw_sub_i32_monotonic + ; RV64IA: liveins: $x10, $x11 + ; RV64IA-NEXT: {{ $}} + ; RV64IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64IA-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s32)) + ; RV64IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %1(s64) + %3:_(s32) = G_ATOMICRMW_SUB %0(p0), %2 :: (load store monotonic (s32)) + %4:_(s64) = G_ANYEXT %3(s32) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: atomicrmw_sub_i64_monotonic +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64IA-ZABHA-LABEL: name: atomicrmw_sub_i64_monotonic + ; RV64IA-ZABHA: liveins: $x10, $x11 + ; RV64IA-ZABHA-NEXT: {{ $}} + ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-ZABHA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64IA-ZABHA-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64IA-ZABHA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s64)) + ; RV64IA-ZABHA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10 + ; + ; RV64IA-LABEL: name: atomicrmw_sub_i64_monotonic + ; RV64IA: liveins: $x10, $x11 + ; RV64IA-NEXT: {{ $}} + ; RV64IA-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64IA-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64IA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64IA-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64IA-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[SUB]] :: (load store monotonic (s64)) + ; RV64IA-NEXT: $x10 = COPY [[ATOMICRMW_ADD]](s64) + ; RV64IA-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_ATOMICRMW_SUB %0(p0), %1 :: (load store monotonic (s64)) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv32.mir new file mode 100644 index 0000000..2f1ca52 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv32.mir @@ -0,0 +1,478 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -mattr=+v -global-isel-abort=0 -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: bitreverse_i8 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C2]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[AND3]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -52 + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]] + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[AND4]], [[C1]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C4]](s32) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C4]](s32) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND6]] + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 -86 + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C7]] + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[AND7]], [[C1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[C6]](s32) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C6]](s32) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C7]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND9]] + ; CHECK-NEXT: $x10 = COPY [[OR3]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s8) = G_BITREVERSE %0 + %3:_(s32) = G_ANYEXT %2(s8) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i16 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -3856 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C2]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[AND3]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -13108 + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]] + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[AND4]], [[C1]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C4]](s32) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C4]](s32) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND6]] + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 -21846 + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C7]] + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[AND7]], [[C1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[C6]](s32) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C6]](s32) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C7]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND9]] + ; CHECK-NEXT: $x10 = COPY [[OR3]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s16) = G_BITREVERSE %0 + %3:_(s32) = G_ANYEXT %2(s16) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i32 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C4]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C3]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C4]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND3]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460 + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C6]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C5]](s32) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C5]](s32) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C6]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766 + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] + ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C7]](s32) + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C8]] + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND7]] + ; CHECK-NEXT: $x10 = COPY [[OR5]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_BITREVERSE %0 + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: bitreverse_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C4]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C3]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C4]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND3]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460 + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C6]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C5]](s32) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C5]](s32) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C6]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]] + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766 + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]] + ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C7]](s32) + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32) + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C8]] + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND7]] + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL5]] + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C2]](s32) + ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL6]] + ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]] + ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[AND9]] + ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR8]], [[C4]] + ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C3]](s32) + ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[OR8]], [[C3]](s32) + ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[SHL7]], [[C4]] + ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[LSHR7]], [[AND11]] + ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[OR9]], [[C6]] + ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[C5]](s32) + ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[OR9]], [[C5]](s32) + ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[SHL8]], [[C6]] + ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[LSHR8]], [[AND13]] + ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[OR10]], [[C8]] + ; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[C7]](s32) + ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[OR10]], [[C7]](s32) + ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[SHL9]], [[C8]] + ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[LSHR9]], [[AND15]] + ; CHECK-NEXT: $x10 = COPY [[OR5]](s32) + ; CHECK-NEXT: $x11 = COPY [[OR11]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %3:_(s64) = G_BITREVERSE %0 + %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) + $x10 = COPY %4(s32) + $x11 = COPY %5(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: bitreverse_i2 +body: | + bb.1.entry: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C]](s32) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND2]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s2) = G_TRUNC %1(s32) + %2:_(s2) = G_BITREVERSE %0 + %3:_(s32) = G_ANYEXT %2(s2) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i3 +body: | + bb.1.entry: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i3 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND2]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C]](s32) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[AND3]] + ; CHECK-NEXT: $x10 = COPY [[OR1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s3) = G_TRUNC %1(s32) + %2:_(s3) = G_BITREVERSE %0 + %3:_(s32) = G_ANYEXT %2(s3) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i4 +body: | + bb.1.entry: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i4 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32) + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[AND3]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C]](s32) + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND4]] + ; CHECK-NEXT: $x10 = COPY [[OR2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s4) = G_TRUNC %1(s32) + %2:_(s4) = G_BITREVERSE %0 + %3:_(s32) = G_ANYEXT %2(s4) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i7 +body: | + bb.1.entry: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i7 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C4]](s32) + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[AND2]] + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C7]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C6]](s32) + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C8]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND4]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[AND5]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C2]](s32) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[AND6]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C]](s32) + ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C9]] + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[AND7]] + ; CHECK-NEXT: $x10 = COPY [[OR5]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s7) = G_TRUNC %1(s32) + %2:_(s7) = G_BITREVERSE %0 + %3:_(s32) = G_ANYEXT %2(s7) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i24 +body: | + bb.1.entry: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i24 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -986896 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C2]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[AND3]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -3355444 + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]] + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[AND4]], [[C1]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C4]](s32) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C4]](s32) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND6]] + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 -5592406 + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C7]] + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[AND7]], [[C1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[C6]](s32) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C6]](s32) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C7]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND9]] + ; CHECK-NEXT: $x10 = COPY [[OR3]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s24) = G_TRUNC %1(s32) + %2:_(s24) = G_BITREVERSE %0 + %3:_(s32) = G_ANYEXT %2(s24) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_v2i4 +body: | + bb.1.entry: + + ; CHECK-LABEL: name: bitreverse_v2i4 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $v8 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s4>) = G_TRUNC [[COPY]](<2 x s32>) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s4) = G_CONSTANT i4 3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s4>) = G_BUILD_VECTOR [[C]](s4), [[C]](s4) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<2 x s4>) = G_SHL [[TRUNC]], [[BUILD_VECTOR]](<2 x s4>) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s4) = G_CONSTANT i4 -8 + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s4>) = G_BUILD_VECTOR [[C1]](s4), [[C1]](s4) + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s4>) = G_AND [[SHL]], [[BUILD_VECTOR1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s4) = G_CONSTANT i4 1 + ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s4>) = G_BUILD_VECTOR [[C2]](s4), [[C2]](s4) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(<2 x s4>) = G_SHL [[TRUNC]], [[BUILD_VECTOR2]](<2 x s4>) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s4) = G_CONSTANT i4 4 + ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s4>) = G_BUILD_VECTOR [[C3]](s4), [[C3]](s4) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s4>) = G_AND [[SHL1]], [[BUILD_VECTOR3]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s4>) = G_OR [[AND]], [[AND1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<2 x s4>) = G_LSHR [[TRUNC]], [[BUILD_VECTOR2]](<2 x s4>) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s4) = G_CONSTANT i4 2 + ; CHECK-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s4>) = G_BUILD_VECTOR [[C4]](s4), [[C4]](s4) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s4>) = G_AND [[LSHR]], [[BUILD_VECTOR4]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s4>) = G_OR [[OR]], [[AND2]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(<2 x s4>) = G_LSHR [[TRUNC]], [[BUILD_VECTOR]](<2 x s4>) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s4>) = G_AND [[LSHR1]], [[BUILD_VECTOR2]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(<2 x s4>) = G_OR [[OR1]], [[AND3]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s4>) = COPY [[OR2]](<2 x s4>) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[COPY1]](<2 x s4>) + ; CHECK-NEXT: $v8 = COPY [[ANYEXT]](<2 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(<2 x s32>) = COPY $v8 + %0:_(<2 x s4>) = G_TRUNC %1(<2 x s32>) + %2:_(<2 x s4>) = G_BITREVERSE %0 + %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s4>) + $v8 = COPY %3(<2 x s32>) + PseudoRET implicit $v8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir new file mode 100644 index 0000000..31c9b2c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir @@ -0,0 +1,474 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr=+v -global-isel-abort=0 -global-isel-abort=0 -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: bitreverse_i8 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C3]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C2]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C2]](s64) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C3]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[AND3]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 -52 + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C5]] + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[C1]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C4]](s64) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C4]](s64) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SHL2]], [[C5]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[AND6]] + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 -86 + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C7]] + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND7]], [[C1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[C6]](s64) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[C6]](s64) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SHL3]], [[C7]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[AND9]] + ; CHECK-NEXT: $x10 = COPY [[OR3]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s8) = G_BITREVERSE %0 + %3:_(s64) = G_ANYEXT %2(s8) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i16 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -3856 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C3]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C2]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C2]](s64) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C3]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[AND3]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 -13108 + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C5]] + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[C1]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C4]](s64) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C4]](s64) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SHL2]], [[C5]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[AND6]] + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 -21846 + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C7]] + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND7]], [[C1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[C6]](s64) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[C6]](s64) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SHL3]], [[C7]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[AND9]] + ; CHECK-NEXT: $x10 = COPY [[OR3]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s16) = G_BITREVERSE %0 + %3:_(s64) = G_ANYEXT %2(s16) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i32 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65280 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[SHL1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C3]](s64) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C2]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND2]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 -252645136 + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C5]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[AND3]], [[C1]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[C4]](s64) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[C4]](s64) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SHL2]], [[C5]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[AND5]] + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 -858993460 + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C7]] + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[AND6]], [[C1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[C6]](s64) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[OR3]], [[C6]](s64) + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[SHL3]], [[C7]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[AND8]] + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1431655766 + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[OR4]], [[C9]] + ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[AND9]], [[C1]] + ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND10]], [[C8]](s64) + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[OR4]], [[C8]](s64) + ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[SHL4]], [[C9]] + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[AND11]] + ; CHECK-NEXT: $x10 = COPY [[OR5]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s32) = G_BITREVERSE %0 + %3:_(s64) = G_ANYEXT %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i64 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65280 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 40 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[C2]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[SHL1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C1]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND1]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16711680 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C3]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[AND2]], [[C4]](s64) + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[SHL2]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C4]](s64) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR2]], [[C3]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[AND3]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16777216 + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C5]] + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[AND4]], [[C6]](s64) + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[SHL3]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C6]](s64) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR3]], [[C5]] + ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[OR5]], [[AND5]] + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[CONSTANT_POOL:%[0-9]+]]:_(p0) = G_CONSTANT_POOL %const.2 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[CONSTANT_POOL]](p0) :: (load (s64) from constant-pool) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[OR6]], [[LOAD]] + ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[C7]](s64) + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[OR6]], [[C7]](s64) + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SHL4]], [[LOAD]] + ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[AND7]] + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[CONSTANT_POOL1:%[0-9]+]]:_(p0) = G_CONSTANT_POOL %const.1 + ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[CONSTANT_POOL1]](p0) :: (load (s64) from constant-pool) + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[OR7]], [[LOAD1]] + ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[C8]](s64) + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[OR7]], [[C8]](s64) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SHL5]], [[LOAD1]] + ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s64) = G_OR [[LSHR5]], [[AND9]] + ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[CONSTANT_POOL2:%[0-9]+]]:_(p0) = G_CONSTANT_POOL %const.0 + ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[CONSTANT_POOL2]](p0) :: (load (s64) from constant-pool) + ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[OR8]], [[LOAD2]] + ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND10]], [[C9]](s64) + ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[OR8]], [[C9]](s64) + ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[SHL6]], [[LOAD2]] + ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s64) = G_OR [[LSHR6]], [[AND11]] + ; CHECK-NEXT: $x10 = COPY [[OR9]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_BITREVERSE %0 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i2 +body: | + bb.1.entry: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C]](s64) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s2) = G_TRUNC %1(s64) + %2:_(s2) = G_BITREVERSE %0 + %3:_(s64) = G_ANYEXT %2(s2) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i3 +body: | + bb.1.entry: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i3 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C2]](s64) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C]](s64) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C4]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[AND3]] + ; CHECK-NEXT: $x10 = COPY [[OR1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s3) = G_TRUNC %1(s64) + %2:_(s3) = G_BITREVERSE %0 + %3:_(s64) = G_ANYEXT %2(s3) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i4 +body: | + bb.1.entry: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i4 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C3]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C4]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C2]](s64) + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C5]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[AND3]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C]](s64) + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C2]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND4]] + ; CHECK-NEXT: $x10 = COPY [[OR2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s4) = G_TRUNC %1(s64) + %2:_(s4) = G_BITREVERSE %0 + %3:_(s64) = G_ANYEXT %2(s4) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i7 +body: | + bb.1.entry: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i7 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 6 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C3]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C4]](s64) + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL2]], [[C5]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[AND2]] + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 127 + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C7]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C6]](s64) + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C8]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND4]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C2]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[AND5]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C2]](s64) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR2]], [[C4]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[AND6]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C]](s64) + ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[LSHR3]], [[C9]] + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[AND7]] + ; CHECK-NEXT: $x10 = COPY [[OR5]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s7) = G_TRUNC %1(s64) + %2:_(s7) = G_BITREVERSE %0 + %3:_(s64) = G_ANYEXT %2(s7) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_i24 +body: | + bb.1.entry: + liveins: $x10 + + ; CHECK-LABEL: name: bitreverse_i24 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -986896 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C3]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C2]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C2]](s64) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C3]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[AND3]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 -3355444 + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C5]] + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[C1]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C4]](s64) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C4]](s64) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SHL2]], [[C5]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[AND6]] + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 -5592406 + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C7]] + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND7]], [[C1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[C6]](s64) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[C6]](s64) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SHL3]], [[C7]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[AND9]] + ; CHECK-NEXT: $x10 = COPY [[OR3]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s24) = G_TRUNC %1(s64) + %2:_(s24) = G_BITREVERSE %0 + %3:_(s64) = G_ANYEXT %2(s24) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: bitreverse_v2i4 +body: | + bb.1.entry: + + ; CHECK-LABEL: name: bitreverse_v2i4 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $v8 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s4>) = G_TRUNC [[COPY]](<2 x s32>) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s4) = G_CONSTANT i4 3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s4>) = G_BUILD_VECTOR [[C]](s4), [[C]](s4) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<2 x s4>) = G_SHL [[TRUNC]], [[BUILD_VECTOR]](<2 x s4>) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s4) = G_CONSTANT i4 -8 + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s4>) = G_BUILD_VECTOR [[C1]](s4), [[C1]](s4) + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s4>) = G_AND [[SHL]], [[BUILD_VECTOR1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s4) = G_CONSTANT i4 1 + ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s4>) = G_BUILD_VECTOR [[C2]](s4), [[C2]](s4) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(<2 x s4>) = G_SHL [[TRUNC]], [[BUILD_VECTOR2]](<2 x s4>) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s4) = G_CONSTANT i4 4 + ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s4>) = G_BUILD_VECTOR [[C3]](s4), [[C3]](s4) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s4>) = G_AND [[SHL1]], [[BUILD_VECTOR3]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s4>) = G_OR [[AND]], [[AND1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<2 x s4>) = G_LSHR [[TRUNC]], [[BUILD_VECTOR2]](<2 x s4>) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s4) = G_CONSTANT i4 2 + ; CHECK-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s4>) = G_BUILD_VECTOR [[C4]](s4), [[C4]](s4) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s4>) = G_AND [[LSHR]], [[BUILD_VECTOR4]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s4>) = G_OR [[OR]], [[AND2]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(<2 x s4>) = G_LSHR [[TRUNC]], [[BUILD_VECTOR]](<2 x s4>) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s4>) = G_AND [[LSHR1]], [[BUILD_VECTOR2]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(<2 x s4>) = G_OR [[OR1]], [[AND3]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s4>) = COPY [[OR2]](<2 x s4>) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[COPY1]](<2 x s4>) + ; CHECK-NEXT: $v8 = COPY [[ANYEXT]](<2 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(<2 x s32>) = COPY $v8 + %0:_(<2 x s4>) = G_TRUNC %1(<2 x s32>) + %2:_(<2 x s4>) = G_BITREVERSE %0 + %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s4>) + $v8 = COPY %3(<2 x s32>) + PseudoRET implicit $v8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-brindirect-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-brindirect-rv32.mir new file mode 100644 index 0000000..271989e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-brindirect-rv32.mir @@ -0,0 +1,42 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: indirectbr +body: | + ; CHECK-LABEL: name: indirectbr + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: G_BRINDIRECT [[COPY]](p0) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: $x10 = COPY [[C1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: $x10 = COPY [[C]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1: + successors: %bb.2, %bb.3 + liveins: $x10 + + %0:_(p0) = COPY $x10 + %1:_(s32) = G_CONSTANT i32 1 + %2:_(s32) = G_CONSTANT i32 0 + G_BRINDIRECT %0(p0) + + bb.2: + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + + bb.3: + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-brindirect-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-brindirect-rv64.mir new file mode 100644 index 0000000..e997323 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-brindirect-rv64.mir @@ -0,0 +1,42 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: indirectbr +body: | + ; CHECK-LABEL: name: indirectbr + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: G_BRINDIRECT [[COPY]](p0) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: $x10 = COPY [[C]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: $x10 = COPY [[C1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1: + successors: %bb.2, %bb.3 + liveins: $x10 + + %0:_(p0) = COPY $x10 + G_BRINDIRECT %0(p0) + + bb.2: + %4:_(s64) = G_CONSTANT i64 0 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + + bb.3: + %2:_(s64) = G_CONSTANT i64 1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir new file mode 100644 index 0000000..d31a448 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir @@ -0,0 +1,135 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32I +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB +# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB + +--- +name: bswap_i16 +body: | + bb.0: + liveins: $x10 + ; RV32I-LABEL: name: bswap_i16 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C]](s32) + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ASSERT_ZEXT]], [[C]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C1]] + ; RV32I-NEXT: $x10 = COPY [[AND]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i16 + ; RV32ZBB_OR_RV32ZBKB: liveins: $x10 + ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}} + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]] + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[LSHR]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_ASSERT_ZEXT %0, 16 + %2:_(s16) = G_TRUNC %1(s32) + %3:_(s16) = G_BSWAP %2 + %4:_(s32) = G_ZEXT %3(s16) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: bswap_i32 +body: | + bb.0: + liveins: $x10 + ; RV32I-LABEL: name: bswap_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280 + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32) + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]] + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]] + ; RV32I-NEXT: $x10 = COPY [[OR2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i32 + ; RV32ZBB_OR_RV32ZBKB: liveins: $x10 + ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}} + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]] + ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_BSWAP %0 + $x10 = COPY %1(s32) + PseudoRET implicit $x10 +... +--- +name: bswap_i64 +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-LABEL: name: bswap_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280 + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] + ; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]] + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]] + ; RV32I-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; RV32I-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32) + ; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL3]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32) + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]] + ; RV32I-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[AND3]] + ; RV32I-NEXT: $x10 = COPY [[OR2]](s32) + ; RV32I-NEXT: $x11 = COPY [[OR5]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i64 + ; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11 + ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}} + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]] + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]] + ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: $x11 = COPY [[BSWAP1]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s64) = G_BSWAP %2 + %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) + $x10 = COPY %4(s32) + $x11 = COPY %5(s32) + PseudoRET implicit $x10, implicit $x11 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir new file mode 100644 index 0000000..b5d2876 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir @@ -0,0 +1,143 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64I +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64ZBB_OR_RV64ZBKB +# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64ZBB_OR_RV64ZBKB + +--- +name: bswap_i16 +body: | + bb.0: + liveins: $x10 + ; RV64I-LABEL: name: bswap_i16 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[C]](s64) + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ASSERT_ZEXT]], [[C]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: $x10 = COPY [[AND]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i16 + ; RV64ZBB_OR_RV64ZBKB: liveins: $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}} + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]] + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[LSHR]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_ASSERT_ZEXT %0, 16 + %2:_(s16) = G_TRUNC %1(s64) + %3:_(s16) = G_BSWAP %2 + %4:_(s64) = G_ZEXT %3(s16) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: bswap_i32 +body: | + bb.0: + liveins: $x10 + ; RV64I-LABEL: name: bswap_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[C]](s64) + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ASSERT_ZEXT]], [[C]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65280 + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ASSERT_ZEXT]], [[C1]] + ; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[C2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[SHL1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ASSERT_ZEXT]], [[C2]](s64) + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C1]] + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C3]] + ; RV64I-NEXT: $x10 = COPY [[AND2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i32 + ; RV64ZBB_OR_RV64ZBKB: liveins: $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}} + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]] + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[LSHR]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_ASSERT_ZEXT %0, 32 + %2:_(s32) = G_TRUNC %1(s64) + %3:_(s32) = G_BSWAP %2 + %4:_(s64) = G_ZEXT %3(s32) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: bswap_i64 +body: | + bb.0: + liveins: $x10 + ; RV64I-LABEL: name: bswap_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65280 + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 40 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[C2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[SHL1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C2]](s64) + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C1]] + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16711680 + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C3]] + ; RV64I-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[AND2]], [[C4]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[SHL2]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C4]](s64) + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR2]], [[C3]] + ; RV64I-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[AND3]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16777216 + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C5]] + ; RV64I-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[AND4]], [[C6]](s64) + ; RV64I-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[SHL3]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C6]](s64) + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR3]], [[C5]] + ; RV64I-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[OR5]], [[AND5]] + ; RV64I-NEXT: $x10 = COPY [[OR6]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i64 + ; RV64ZBB_OR_RV64ZBKB: liveins: $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}} + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[COPY]] + ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[BSWAP]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_BSWAP %0 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv32.mir new file mode 100644 index 0000000..e2903b2 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv32.mir @@ -0,0 +1,126 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: const_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i7 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; CHECK-NEXT: $x10 = COPY [[C]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s7) = G_CONSTANT i7 15 + %1:_(s32) = G_ANYEXT %0(s7) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: const_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -127 + ; CHECK-NEXT: $x10 = COPY [[C]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s8) = G_CONSTANT i8 129 + %1:_(s32) = G_ANYEXT %0(s8) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: const_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 + ; CHECK-NEXT: $x10 = COPY [[C]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = G_CONSTANT i16 -32769 + %1:_(s32) = G_ANYEXT %0(s16) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: const_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483647 + ; CHECK-NEXT: $x10 = COPY [[C]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_CONSTANT i32 2147483649 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: const_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i48 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: $x10 = COPY [[C]](s32) + ; CHECK-NEXT: $x11 = COPY [[C1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s48) = G_CONSTANT i48 2 + %1:_(s64) = G_ANYEXT %0(s48) + %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) + $x10 = COPY %2(s32) + $x11 = COPY %3(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: const_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i64 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483647 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: $x10 = COPY [[C]](s32) + ; CHECK-NEXT: $x11 = COPY [[C1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = G_CONSTANT i64 2147483649 + %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64) + $x10 = COPY %1(s32) + $x11 = COPY %2(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: const_i96 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i96 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -121 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -51 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: $x10 = COPY [[C]](s32) + ; CHECK-NEXT: $x11 = COPY [[C1]](s32) + ; CHECK-NEXT: $x12 = COPY [[C2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %0:_(s96) = G_CONSTANT i96 -214748364921 + %1:_(s32), %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %0(s96) + $x10 = COPY %1(s32) + $x11 = COPY %2(s32) + $x12 = COPY %3(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... +--- +name: const_null +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_null + ; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i32 0 + ; CHECK-NEXT: $x10 = COPY [[C]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = G_CONSTANT i32 0 + $x10 = COPY %0(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir new file mode 100644 index 0000000..e28572d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir @@ -0,0 +1,194 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: const_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i8 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -127 + ; CHECK-NEXT: $x10 = COPY [[C]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s8) = G_CONSTANT i8 129 + %1:_(s64) = G_ANYEXT %0(s8) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i15 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; CHECK-NEXT: $x10 = COPY [[C]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s15) = G_CONSTANT i15 15 + %1:_(s64) = G_ANYEXT %0(s15) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i16 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 767 + ; CHECK-NEXT: $x10 = COPY [[C]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = G_CONSTANT i16 -64769 + %1:_(s64) = G_ANYEXT %0(s16) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i32 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -64769 + ; CHECK-NEXT: $x10 = COPY [[C]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_CONSTANT i32 -64769 + %1:_(s64) = G_ANYEXT %0(s32) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i64 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2147483649 + ; CHECK-NEXT: $x10 = COPY [[C]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_CONSTANT i64 2147483649 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: const_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i72 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2147483649312 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: $x10 = COPY [[C]](s64) + ; CHECK-NEXT: $x11 = COPY [[C1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s72) = G_CONSTANT i72 -2147483649312 + %1:_(s128) = G_ANYEXT %0(s72) + %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %1(s128) + $x10 = COPY %2(s64) + $x11 = COPY %3(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: const_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i128 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 21474831289 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: $x10 = COPY [[C]](s64) + ; CHECK-NEXT: $x11 = COPY [[C1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s128) = G_CONSTANT i128 21474831289 + %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(s128) + $x10 = COPY %1(s64) + $x11 = COPY %2(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: const_i192 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_i192 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -214772364921 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: $x10 = COPY [[C]](s64) + ; CHECK-NEXT: $x11 = COPY [[C1]](s64) + ; CHECK-NEXT: $x12 = COPY [[C1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %0:_(s192) = G_CONSTANT i192 -214772364921 + %1:_(s64), %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %0(s192) + $x10 = COPY %1(s64) + $x11 = COPY %2(s64) + $x12 = COPY %3(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... +--- +name: const_null +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_null + ; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 + ; CHECK-NEXT: $x10 = COPY [[C]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = G_CONSTANT i64 0 + $x10 = COPY %0(p0) + PseudoRET implicit $x10 + +... +--- +name: const_add_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_add_i32 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -64769 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_CONSTANT i32 -64769 + %1:_(s64) = COPY $x10 + %2:_(s32) = G_TRUNC %1(s64) + %3:_(s32) = G_ADD %2, %0 + %4:_(s64) = G_ANYEXT %3(s32) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: const_add_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: const_add_i8 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] + ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s8) = G_CONSTANT i8 1 + %1:_(s64) = COPY $x10 + %2:_(s8) = G_TRUNC %1(s64) + %3:_(s8) = G_ADD %2, %0 + %4:_(s64) = G_ANYEXT %3(s8) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... + +... +--- +name: constant_pool_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constant_pool_i64 + ; CHECK: [[CONSTANT_POOL:%[0-9]+]]:_(p0) = G_CONSTANT_POOL %const.0 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[CONSTANT_POOL]](p0) :: (load (s64) from constant-pool) + ; CHECK-NEXT: $x10 = COPY [[LOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_CONSTANT i64 -1085102592571150096 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv32.mir new file mode 100644 index 0000000..b1630d9 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv32.mir @@ -0,0 +1,84 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: constbarrier_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constbarrier_i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16368 + ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s32) = G_CONSTANT_FOLD_BARRIER [[C]] + ; CHECK-NEXT: $x10 = COPY [[CONSTANT_FOLD_BARRIER]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = G_CONSTANT i32 16368 + %2:_(s32) = G_CONSTANT_FOLD_BARRIER %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: constbarrier_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constbarrier_i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2048 + ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s32) = G_CONSTANT_FOLD_BARRIER [[C]] + ; CHECK-NEXT: $x10 = COPY [[CONSTANT_FOLD_BARRIER]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s16) = G_CONSTANT i16 2048 + %2:_(s16) = G_CONSTANT_FOLD_BARRIER %1 + %3:_(s32) = G_ANYEXT %2(s16) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: constbarrier_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constbarrier_i128 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2048 + ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s32) = G_CONSTANT_FOLD_BARRIER [[C]] + ; CHECK-NEXT: $x10 = COPY [[CONSTANT_FOLD_BARRIER]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s128) = G_CONSTANT i128 2048 + %2:_(s128) = G_CONSTANT_FOLD_BARRIER %1 + %3:_(s32) = G_TRUNC %2(s128) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: constbarrier_nxv2i1 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constbarrier_nxv2i1 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_() = G_CONSTANT_FOLD_BARRIER [[VMCLR_VL]] + ; CHECK-NEXT: $v8 = COPY [[CONSTANT_FOLD_BARRIER]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s1) = G_CONSTANT i1 0 + %2:_() = G_SPLAT_VECTOR %1(s1) + %3:_() = G_CONSTANT_FOLD_BARRIER %2 + $v8 = COPY %3() + PseudoRET implicit $v8 + +... +--- +name: constbarrier_nxv2i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constbarrier_nxv2i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_() = G_CONSTANT_FOLD_BARRIER [[SPLAT_VECTOR]] + ; CHECK-NEXT: $v8 = COPY [[CONSTANT_FOLD_BARRIER]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_CONSTANT i32 0 + %2:_() = G_SPLAT_VECTOR %1(s32) + %3:_() = G_CONSTANT_FOLD_BARRIER %2 + $v8 = COPY %3() + PseudoRET implicit $v8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv64.mir new file mode 100644 index 0000000..dc5f062 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv64.mir @@ -0,0 +1,122 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: constbarrier_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constbarrier_i32 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16368 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s32) = G_CONSTANT_FOLD_BARRIER [[TRUNC]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CONSTANT_FOLD_BARRIER]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = G_CONSTANT i32 16368 + %2:_(s32) = G_CONSTANT_FOLD_BARRIER %1 + %3:_(s64) = G_ANYEXT %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: constbarrier_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constbarrier_i64 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16368 + ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s64) = G_CONSTANT_FOLD_BARRIER [[C]] + ; CHECK-NEXT: $x10 = COPY [[CONSTANT_FOLD_BARRIER]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = G_CONSTANT i64 16368 + %2:_(s64) = G_CONSTANT_FOLD_BARRIER %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: constbarrier_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constbarrier_i16 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2048 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s32) = G_CONSTANT_FOLD_BARRIER [[TRUNC]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CONSTANT_FOLD_BARRIER]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s16) = G_CONSTANT i16 2048 + %2:_(s16) = G_CONSTANT_FOLD_BARRIER %1 + %3:_(s64) = G_ANYEXT %2(s16) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: constbarrier_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constbarrier_i128 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2048 + ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s64) = G_CONSTANT_FOLD_BARRIER [[C]] + ; CHECK-NEXT: $x10 = COPY [[CONSTANT_FOLD_BARRIER]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s128) = G_CONSTANT i128 2048 + %2:_(s128) = G_CONSTANT_FOLD_BARRIER %1 + %3:_(s64) = G_TRUNC %2(s128) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: constbarrier_nxv2i1 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constbarrier_nxv2i1 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_() = G_CONSTANT_FOLD_BARRIER [[VMCLR_VL]] + ; CHECK-NEXT: $v8 = COPY [[CONSTANT_FOLD_BARRIER]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s1) = G_CONSTANT i1 0 + %2:_() = G_SPLAT_VECTOR %1(s1) + %3:_() = G_CONSTANT_FOLD_BARRIER %2 + $v8 = COPY %3() + PseudoRET implicit $v8 + +... +--- +name: constbarrier_nxv2i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constbarrier_nxv2i32 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_() = G_CONSTANT_FOLD_BARRIER [[SPLAT_VECTOR]] + ; CHECK-NEXT: $v8 = COPY [[CONSTANT_FOLD_BARRIER]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_CONSTANT i32 0 + %2:_() = G_SPLAT_VECTOR %1(s32) + %3:_() = G_CONSTANT_FOLD_BARRIER %2 + $v8 = COPY %3() + PseudoRET implicit $v8 + +... +--- +name: constbarrier_nxv2i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: constbarrier_nxv2i64 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_() = G_CONSTANT_FOLD_BARRIER [[SPLAT_VECTOR]] + ; CHECK-NEXT: $v8m2 = COPY [[CONSTANT_FOLD_BARRIER]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + %1:_(s64) = G_CONSTANT i64 0 + %2:_() = G_SPLAT_VECTOR %1(s64) + %3:_() = G_CONSTANT_FOLD_BARRIER %2() + $v8m2 = COPY %3() + PseudoRET implicit $v8m2 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv32.mir new file mode 100644 index 0000000..78cfaf1 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv32.mir @@ -0,0 +1,412 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32I +# RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32P +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32ZBB + +--- +name: cls_i8 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: cls_i8 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32) + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]](s32) + ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32) + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[ASHR1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C3]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[LSHR]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C4]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C3]] + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32) + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C3]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32) + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C6]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR2]], [[AND4]] + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]] + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C4]](s32) + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C7]] + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C7]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND6]], [[AND7]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C5]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR5]], [[ADD]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C8]] + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV32I-NEXT: $x10 = COPY [[AND8]](s32) + ; RV32I-NEXT: $x11 = COPY [[C1]](s32) + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C9]](s32) + ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[LSHR6]] + ; RV32I-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C1]] + ; RV32I-NEXT: $x10 = COPY [[SUB2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32P-LABEL: name: cls_i8 + ; RV32P: liveins: $x10 + ; RV32P-NEXT: {{ $}} + ; RV32P-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32P-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8 + ; RV32P-NEXT: [[CTLS:%[0-9]+]]:_(s32) = G_CTLS [[SEXT_INREG]](s32) + ; RV32P-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32P-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLS]], [[C]] + ; RV32P-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; RV32P-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32P-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: cls_i8 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8 + ; RV32ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32) + ; RV32ZBB-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[ASHR]] + ; RV32ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C2]] + ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) + ; RV32ZBB-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C3]] + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SUB1]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s8) = G_CTLS %0(s8) + %3:_(s32) = G_ANYEXT %2(s8) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 +... + +--- +name: cls_i16 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: cls_i16 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32) + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]](s32) + ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32) + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[ASHR1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C3]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[LSHR]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C4]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C3]] + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32) + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C3]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C6]](s32) + ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C3]] + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C1]](s32) + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C7]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR3]], [[AND5]] + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C4]](s32) + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C8]] + ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C8]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND7]], [[AND8]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C5]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD]] + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 + ; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C9]] + ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C6]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND9]], [[LSHR7]] + ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C10]] + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[AND10]] + ; RV32I-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C1]] + ; RV32I-NEXT: $x10 = COPY [[SUB2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32P-LABEL: name: cls_i16 + ; RV32P: liveins: $x10 + ; RV32P-NEXT: {{ $}} + ; RV32P-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32P-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16 + ; RV32P-NEXT: [[CTLS:%[0-9]+]]:_(s32) = G_CTLS [[SEXT_INREG]](s32) + ; RV32P-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32P-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLS]], [[C]] + ; RV32P-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; RV32P-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32P-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: cls_i16 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16 + ; RV32ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32) + ; RV32ZBB-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[ASHR]] + ; RV32ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C2]] + ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) + ; RV32ZBB-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C3]] + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SUB1]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s16) = G_CTLS %0(s16) + %3:_(s32) = G_ANYEXT %2(s16) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 +... + +--- +name: cls_i32 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: cls_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[ASHR]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[XOR]], [[C1]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[LSHR]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32) + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C4]](s32) + ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C5]](s32) + ; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[LSHR4]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[C1]](s32) + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C6]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR4]], [[AND]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32) + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C7]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C7]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] + ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C3]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[ADD]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C8]] + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND3]], [[SHL]] + ; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ADD2]], [[C5]](s32) + ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[SHL1]] + ; RV32I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[ADD3]], [[C9]](s32) + ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[LSHR8]] + ; RV32I-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C1]] + ; RV32I-NEXT: $x10 = COPY [[SUB2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32P-LABEL: name: cls_i32 + ; RV32P: liveins: $x10 + ; RV32P-NEXT: {{ $}} + ; RV32P-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32P-NEXT: [[CTLS:%[0-9]+]]:_(s32) = G_CTLS [[COPY]](s32) + ; RV32P-NEXT: $x10 = COPY [[CTLS]](s32) + ; RV32P-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: cls_i32 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32) + ; RV32ZBB-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[ASHR]] + ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[XOR]](s32) + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_CTLS %0(s32) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 +... + +--- +name: cls_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cls_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C]](s32) + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[ASHR]] + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[ASHR]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[XOR]], [[C1]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[LSHR]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32) + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C4]](s32) + ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C5]](s32) + ; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[LSHR4]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[C1]](s32) + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C6]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR4]], [[AND]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32) + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C7]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C7]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] + ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C3]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[ADD]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C8]] + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND3]], [[SHL]] + ; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ADD2]], [[C5]](s32) + ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[SHL1]] + ; RV32I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[ADD3]], [[C9]](s32) + ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[LSHR8]] + ; RV32I-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[SUB1]], [[C]] + ; RV32I-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[ASHR]] + ; RV32I-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[XOR1]], [[C1]](s32) + ; RV32I-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[XOR1]], [[LSHR9]] + ; RV32I-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[OR5]], [[C2]](s32) + ; RV32I-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[LSHR10]] + ; RV32I-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[OR6]], [[C3]](s32) + ; RV32I-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[LSHR11]] + ; RV32I-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[OR7]], [[C4]](s32) + ; RV32I-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[LSHR12]] + ; RV32I-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[OR8]], [[C5]](s32) + ; RV32I-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[LSHR13]] + ; RV32I-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[OR9]], [[C1]](s32) + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C6]] + ; RV32I-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[OR9]], [[AND4]] + ; RV32I-NEXT: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[SUB2]], [[C2]](s32) + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C7]] + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB2]], [[C7]] + ; RV32I-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]] + ; RV32I-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[ADD5]], [[C3]](s32) + ; RV32I-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[LSHR16]], [[ADD5]] + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD6]], [[C8]] + ; RV32I-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32) + ; RV32I-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[AND7]], [[SHL2]] + ; RV32I-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ADD7]], [[C5]](s32) + ; RV32I-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[SHL3]] + ; RV32I-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[ADD8]], [[C9]](s32) + ; RV32I-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[LSHR17]] + ; RV32I-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[C1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD4]], [[SUB4]] + ; RV32I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: $x11 = COPY [[C11]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; RV32P-LABEL: name: cls_i64 + ; RV32P: liveins: $x10, $x11 + ; RV32P-NEXT: {{ $}} + ; RV32P-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32P-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32P-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV32P-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C]](s32) + ; RV32P-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[ASHR]] + ; RV32P-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[ASHR]] + ; RV32P-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[XOR]](s32) + ; RV32P-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C]] + ; RV32P-NEXT: [[CTLS:%[0-9]+]]:_(s32) = G_CTLS [[COPY1]](s32) + ; RV32P-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[CTLS]] + ; RV32P-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32P-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32P-NEXT: $x11 = COPY [[C1]](s32) + ; RV32P-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; RV32ZBB-LABEL: name: cls_i64 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV32ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C]](s32) + ; RV32ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[ASHR]] + ; RV32ZBB-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[ASHR]] + ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[XOR]](s32) + ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C]] + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32ZBB-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[ASHR]] + ; RV32ZBB-NEXT: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[XOR1]](s32) + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ1]], [[C1]] + ; RV32ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[SUB]] + ; RV32ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32ZBB-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32ZBB-NEXT: $x11 = COPY [[C2]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %3:_(s64) = G_CTLS %0(s64) + %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) + $x10 = COPY %4(s32) + $x11 = COPY %5(s32) + PseudoRET implicit $x10, implicit $x11 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv64.mir new file mode 100644 index 0000000..c5a3fe1 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv64.mir @@ -0,0 +1,386 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64I +# RUN: llc -mtriple=riscv64 -mattr=+experimental-p -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64P +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64ZBB + +--- +name: cls_i8 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: cls_i8 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64) + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C2]](s64) + ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C]](s64) + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[ASHR1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C3]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C1]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[LSHR]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C3]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C4]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C3]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C5]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C3]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C1]](s64) + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 85 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR3]], [[C6]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR2]], [[AND4]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C3]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C4]](s64) + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 51 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR4]], [[C7]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C7]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[AND7]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C5]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR5]], [[ADD]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C8]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV64I-NEXT: $x10 = COPY [[AND8]](s64) + ; RV64I-NEXT: $x11 = COPY [[C1]](s64) + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C3]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND9]], [[C9]](s64) + ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C10]], [[LSHR6]] + ; RV64I-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C1]] + ; RV64I-NEXT: $x10 = COPY [[SUB2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64P-LABEL: name: cls_i8 + ; RV64P: liveins: $x10 + ; RV64P-NEXT: {{ $}} + ; RV64P-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64P-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8 + ; RV64P-NEXT: [[CLSW:%[0-9]+]]:_(s64) = G_CLSW [[SEXT_INREG]] + ; RV64P-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; RV64P-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CLSW]], [[C]] + ; RV64P-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64P-NEXT: $x10 = COPY [[SEXT_INREG1]](s64) + ; RV64P-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: cls_i8 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8 + ; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s64) + ; RV64ZBB-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[ASHR]] + ; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C2]] + ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] + ; RV64ZBB-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = nuw G_SUB [[CLZW]], [[C3]] + ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG1]], [[C1]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB1]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s8) = G_CTLS %0(s8) + %3:_(s64) = G_ANYEXT %2(s8) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... + +--- +name: cls_i16 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: cls_i16 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64) + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C2]](s64) + ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C]](s64) + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[ASHR1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C3]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C1]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[LSHR]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C3]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C4]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C3]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C5]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C3]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C6]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C3]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[C1]](s64) + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 21845 + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR4]], [[C7]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR3]], [[AND5]] + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C3]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[C4]](s64) + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 13107 + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[C8]] + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C8]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND7]], [[AND8]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C5]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR6]], [[ADD]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855 + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C9]] + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND9]], [[C6]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND9]], [[LSHR7]] + ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C10]] + ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C11]], [[AND10]] + ; RV64I-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C1]] + ; RV64I-NEXT: $x10 = COPY [[SUB2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64P-LABEL: name: cls_i16 + ; RV64P: liveins: $x10 + ; RV64P-NEXT: {{ $}} + ; RV64P-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64P-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 16 + ; RV64P-NEXT: [[CLSW:%[0-9]+]]:_(s64) = G_CLSW [[SEXT_INREG]] + ; RV64P-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64P-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CLSW]], [[C]] + ; RV64P-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64P-NEXT: $x10 = COPY [[SEXT_INREG1]](s64) + ; RV64P-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: cls_i16 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 16 + ; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s64) + ; RV64ZBB-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[ASHR]] + ; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C2]] + ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] + ; RV64ZBB-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = nuw G_SUB [[CLZW]], [[C3]] + ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG1]], [[C1]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB1]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s16) = G_CTLS %0(s16) + %3:_(s64) = G_ANYEXT %2(s16) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... + +--- +name: cls_i32 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: cls_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s64) + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[ASHR]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C2]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C1]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[LSHR]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C2]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C3]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C2]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C4]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C2]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C5]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C2]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[C6]](s64) + ; RV64I-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[LSHR4]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[OR4]], [[C2]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C1]](s64) + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[C7]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR4]], [[AND6]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C2]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[C3]](s64) + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[C8]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C8]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND8]], [[AND9]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG2]], [[C4]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[SEXT_INREG2]] + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG3]], [[C9]] + ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 + ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; RV64I-NEXT: $x10 = COPY [[AND10]](s64) + ; RV64I-NEXT: $x11 = COPY [[C10]](s64) + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C2]] + ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[AND11]], [[C11]](s64) + ; RV64I-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C12]], [[LSHR8]] + ; RV64I-NEXT: [[SEXT_INREG4:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB1]], 32 + ; RV64I-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG4]], [[C1]] + ; RV64I-NEXT: [[SEXT_INREG5:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB2]], 32 + ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG5]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64P-LABEL: name: cls_i32 + ; RV64P: liveins: $x10 + ; RV64P-NEXT: {{ $}} + ; RV64P-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64P-NEXT: [[CLSW:%[0-9]+]]:_(s64) = G_CLSW [[COPY]] + ; RV64P-NEXT: $x10 = COPY [[CLSW]](s64) + ; RV64P-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: cls_i32 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 + ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s64) + ; RV64ZBB-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[ASHR]] + ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[XOR]] + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CLZW]], [[C1]] + ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG1]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s32) = G_CTLS %0(s32) + %3:_(s64) = G_ANYEXT %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... + +--- +name: cls_i64 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: cls_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64) + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[ASHR]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[XOR]], [[C1]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[LSHR]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[OR]], [[C2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[OR1]], [[C3]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[OR2]], [[C4]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[OR3]], [[C5]](s64) + ; RV64I-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[LSHR4]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[OR4]], [[C6]](s64) + ; RV64I-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[LSHR5]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[OR5]], [[C1]](s64) + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 6148914691236517205 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[C7]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR5]], [[AND]] + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[SUB]], [[C2]](s64) + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 3689348814741910323 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR7]], [[C8]] + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C8]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND1]], [[AND2]] + ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C3]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR8]], [[ADD]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 1085102592571150095 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C9]] + ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND3]], [[C4]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND3]], [[SHL]] + ; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ADD2]], [[C5]](s64) + ; RV64I-NEXT: [[ADD3:%[0-9]+]]:_(s64) = G_ADD [[ADD2]], [[SHL1]] + ; RV64I-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ADD3]], [[C6]](s64) + ; RV64I-NEXT: [[ADD4:%[0-9]+]]:_(s64) = G_ADD [[ADD3]], [[SHL2]] + ; RV64I-NEXT: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[ADD4]], [[C10]](s64) + ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C11]], [[LSHR9]] + ; RV64I-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C1]] + ; RV64I-NEXT: $x10 = COPY [[SUB2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64P-LABEL: name: cls_i64 + ; RV64P: liveins: $x10 + ; RV64P-NEXT: {{ $}} + ; RV64P-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64P-NEXT: [[CTLS:%[0-9]+]]:_(s64) = G_CTLS [[COPY]](s64) + ; RV64P-NEXT: $x10 = COPY [[CTLS]](s64) + ; RV64P-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: cls_i64 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64) + ; RV64ZBB-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[ASHR]] + ; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[XOR]](s64) + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CTLZ]], [[C1]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_CTLS %0(s64) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir new file mode 100644 index 0000000..f2d8683 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv32.mir @@ -0,0 +1,602 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mattr=+m -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32I +# RUN: llc -mattr=+m -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32ZBB + +--- +name: ctlz_i8 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: ctlz_i8 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C1]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C1]] + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32) + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C1]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C]](s32) + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR2]], [[AND4]] + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C2]](s32) + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]] + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND6]], [[AND7]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C3]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR5]], [[ADD]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND8]], [[C]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32) + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[LSHR6]] + ; RV32I-NEXT: $x10 = COPY [[SUB1]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: ctlz_i8 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C1]] + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s8) = G_CTLZ %0(s8) + %3:_(s32) = G_ANYEXT %2(s8) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: ctlz_i16 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: ctlz_i16 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C1]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C1]] + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32) + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C1]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32) + ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C1]] + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C]](s32) + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR3]], [[AND5]] + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C2]](s32) + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C6]] + ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C6]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND7]], [[AND8]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C3]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 + ; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]] + ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C4]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND9]], [[LSHR7]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C8]] + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C9]], [[AND10]] + ; RV32I-NEXT: $x10 = COPY [[SUB1]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: ctlz_i16 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C1]] + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s16) = G_CTLZ %0(s16) + %3:_(s32) = G_ANYEXT %2(s16) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: ctlz_i32 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: ctlz_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C2]](s32) + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C3]](s32) + ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C4]](s32) + ; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[LSHR4]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[C]](s32) + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C5]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR4]], [[AND]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C1]](s32) + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C6]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C6]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] + ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C2]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[ADD]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C8]] + ; RV32I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C9]](s32) + ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[LSHR8]] + ; RV32I-NEXT: $x10 = COPY [[SUB1]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: ctlz_i32 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[CTLZ]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_CTLZ %0(s32) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: ctlz_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: ctlz_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32) + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C4]](s32) + ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C5]](s32) + ; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[LSHR4]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[C1]](s32) + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C6]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR4]], [[AND]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32) + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C7]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C7]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] + ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C3]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[ADD]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C8]] + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C9]] + ; RV32I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C10]](s32) + ; RV32I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C11]], [[LSHR8]] + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SUB1]], [[C11]] + ; RV32I-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32) + ; RV32I-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[LSHR9]] + ; RV32I-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[OR5]], [[C2]](s32) + ; RV32I-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[LSHR10]] + ; RV32I-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[OR6]], [[C3]](s32) + ; RV32I-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[LSHR11]] + ; RV32I-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[OR7]], [[C4]](s32) + ; RV32I-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[LSHR12]] + ; RV32I-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[OR8]], [[C5]](s32) + ; RV32I-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[LSHR13]] + ; RV32I-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[OR9]], [[C1]](s32) + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C6]] + ; RV32I-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[OR9]], [[AND4]] + ; RV32I-NEXT: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[SUB2]], [[C2]](s32) + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C7]] + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB2]], [[C7]] + ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]] + ; RV32I-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[ADD3]], [[C3]](s32) + ; RV32I-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR16]], [[ADD3]] + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD4]], [[C8]] + ; RV32I-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[C9]] + ; RV32I-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C10]](s32) + ; RV32I-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C11]], [[LSHR17]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD2]], [[SUB3]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: $x11 = COPY [[C]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; RV32ZBB-LABEL: name: ctlz_i64 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32) + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]] + ; RV32ZBB-NEXT: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32) + ; RV32ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[CTLZ1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32ZBB-NEXT: $x11 = COPY [[C]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %3:_(s64) = G_CTLZ %0(s64) + %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) + $x10 = COPY %4(s32) + $x11 = COPY %5(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ctlz_zero_poison_i8 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: ctlz_zero_poison_i8 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C1]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C1]] + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32) + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C1]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C]](s32) + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR2]], [[AND4]] + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C2]](s32) + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]] + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND6]], [[AND7]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C3]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR5]], [[ADD]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND8]], [[C]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32) + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[LSHR6]] + ; RV32I-NEXT: $x10 = COPY [[SUB1]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: ctlz_zero_poison_i8 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C1]] + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s8) = G_CTLZ_ZERO_POISON %0(s8) + %3:_(s32) = G_ANYEXT %2(s8) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: ctlz_zero_poison_i16 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: ctlz_zero_poison_i16 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C1]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C1]] + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32) + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C1]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32) + ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C1]] + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C]](s32) + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR3]], [[AND5]] + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C2]](s32) + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C6]] + ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C6]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND7]], [[AND8]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C3]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 + ; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]] + ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C4]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND9]], [[LSHR7]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C8]] + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C9]], [[AND10]] + ; RV32I-NEXT: $x10 = COPY [[SUB1]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: ctlz_zero_poison_i16 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C1]] + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s16) = G_CTLZ_ZERO_POISON %0(s16) + %3:_(s32) = G_ANYEXT %2(s16) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: ctlz_zero_poison_i32 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: ctlz_zero_poison_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C2]](s32) + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C3]](s32) + ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C4]](s32) + ; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[LSHR4]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[C]](s32) + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C5]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR4]], [[AND]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C1]](s32) + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C6]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C6]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] + ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C2]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[ADD]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C8]] + ; RV32I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C9]](s32) + ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[LSHR8]] + ; RV32I-NEXT: $x10 = COPY [[SUB1]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: ctlz_zero_poison_i32 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[CTLZ]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_CTLZ_ZERO_POISON %0(s32) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: ctlz_zero_poison_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: ctlz_zero_poison_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[LSHR]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s32) + ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[LSHR1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32) + ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[LSHR2]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C4]](s32) + ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[LSHR3]] + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C5]](s32) + ; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[LSHR4]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[C1]](s32) + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C6]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[OR4]], [[AND]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32) + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C7]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C7]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] + ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C3]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[ADD]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C8]] + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C9]] + ; RV32I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C10]](s32) + ; RV32I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C11]], [[LSHR8]] + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SUB1]], [[C11]] + ; RV32I-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32) + ; RV32I-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[LSHR9]] + ; RV32I-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[OR5]], [[C2]](s32) + ; RV32I-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[LSHR10]] + ; RV32I-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[OR6]], [[C3]](s32) + ; RV32I-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[LSHR11]] + ; RV32I-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[OR7]], [[C4]](s32) + ; RV32I-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[LSHR12]] + ; RV32I-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[OR8]], [[C5]](s32) + ; RV32I-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[LSHR13]] + ; RV32I-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[OR9]], [[C1]](s32) + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C6]] + ; RV32I-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[OR9]], [[AND4]] + ; RV32I-NEXT: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[SUB2]], [[C2]](s32) + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C7]] + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB2]], [[C7]] + ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]] + ; RV32I-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[ADD3]], [[C3]](s32) + ; RV32I-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR16]], [[ADD3]] + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD4]], [[C8]] + ; RV32I-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[C9]] + ; RV32I-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C10]](s32) + ; RV32I-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C11]], [[LSHR17]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD2]], [[SUB3]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: $x11 = COPY [[C]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; RV32ZBB-LABEL: name: ctlz_zero_poison_i64 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; RV32ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32) + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]] + ; RV32ZBB-NEXT: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32) + ; RV32ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[CTLZ1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32ZBB-NEXT: $x11 = COPY [[C]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %3:_(s64) = G_CTLZ_ZERO_POISON %0(s64) + %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) + $x10 = COPY %4(s32) + $x11 = COPY %5(s32) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir new file mode 100644 index 0000000..32288a4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir @@ -0,0 +1,556 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mattr=+m -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64I +# RUN: llc -mattr=+m -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64ZBB + +--- +name: ctlz_i8 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctlz_i8 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C]](s64) + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 85 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR3]], [[C4]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR2]], [[AND4]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C2]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 51 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR4]], [[C5]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C5]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[AND7]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C3]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR5]], [[ADD]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C6]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND8]], [[C]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C7]](s64) + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C8]], [[LSHR6]] + ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctlz_i8 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] + ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = nuw G_SUB [[CLZW]], [[C1]] + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s8) = G_CTLZ %0(s8) + %3:_(s64) = G_ANYEXT %2(s8) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: ctlz_i16 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctlz_i16 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C1]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[C]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 21845 + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR4]], [[C5]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR3]], [[AND5]] + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[C2]](s64) + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 13107 + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[C6]] + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C6]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND7]], [[AND8]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C3]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR6]], [[ADD]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855 + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C7]] + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND9]], [[C4]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND9]], [[LSHR7]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C8]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C9]], [[AND10]] + ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctlz_i16 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] + ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = nuw G_SUB [[CLZW]], [[C1]] + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s16) = G_CTLZ %0(s16) + %3:_(s64) = G_ANYEXT %2(s16) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: ctlz_i32 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctlz_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C1]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[C5]](s64) + ; RV64I-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[LSHR4]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[OR4]], [[C1]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C]](s64) + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[C6]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR4]], [[AND6]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[C2]](s64) + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[C7]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C7]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND8]], [[AND9]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG1]], [[C3]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[SEXT_INREG1]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG2]], [[C8]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 + ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND10]], [[C9]] + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]] + ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[AND11]], [[C10]](s64) + ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C11]], [[LSHR8]] + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB1]], 32 + ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctlz_i32 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[COPY]] + ; RV64ZBB-NEXT: $x10 = COPY [[CLZW]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s32) = G_CTLZ %0(s32) + %3:_(s64) = G_ANYEXT %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: ctlz_i64 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctlz_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[OR]], [[C1]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[OR1]], [[C2]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[OR2]], [[C3]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[OR3]], [[C4]](s64) + ; RV64I-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[LSHR4]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[OR4]], [[C5]](s64) + ; RV64I-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[LSHR5]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[OR5]], [[C]](s64) + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6148914691236517205 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[C6]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR5]], [[AND]] + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[SUB]], [[C1]](s64) + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3689348814741910323 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR7]], [[C7]] + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C7]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND1]], [[AND2]] + ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C2]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR8]], [[ADD]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 1085102592571150095 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C8]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673 + ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND3]], [[C9]] + ; RV64I-NEXT: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C10]](s64) + ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C11]], [[LSHR9]] + ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctlz_i64 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[COPY]](s64) + ; RV64ZBB-NEXT: $x10 = COPY [[CTLZ]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_CTLZ %0(s64) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: ctlz_zero_poison_i8 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctlz_zero_poison_i8 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C]](s64) + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 85 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR3]], [[C4]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR2]], [[AND4]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C2]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 51 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR4]], [[C5]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C5]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[AND7]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C3]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR5]], [[ADD]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C6]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND8]], [[C]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C7]](s64) + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C8]], [[LSHR6]] + ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctlz_zero_poison_i8 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] + ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = nuw G_SUB [[CLZW]], [[C1]] + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s8) = G_CTLZ_ZERO_POISON %0(s8) + %3:_(s64) = G_ANYEXT %2(s8) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: ctlz_zero_poison_i16 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctlz_zero_poison_i16 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C1]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[C]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 21845 + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR4]], [[C5]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR3]], [[AND5]] + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[C2]](s64) + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 13107 + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[C6]] + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C6]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND7]], [[AND8]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C3]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR6]], [[ADD]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855 + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C7]] + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND9]], [[C4]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND9]], [[LSHR7]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C8]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C9]], [[AND10]] + ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctlz_zero_poison_i16 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] + ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = nuw G_SUB [[CLZW]], [[C1]] + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s16) = G_CTLZ_ZERO_POISON %0(s16) + %3:_(s64) = G_ANYEXT %2(s16) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: ctlz_zero_poison_i32 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctlz_zero_poison_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C1]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[C5]](s64) + ; RV64I-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[LSHR4]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[OR4]], [[C1]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C]](s64) + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[C6]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR4]], [[AND6]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[C2]](s64) + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[C7]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C7]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND8]], [[AND9]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG1]], [[C3]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[SEXT_INREG1]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG2]], [[C8]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 + ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND10]], [[C9]] + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]] + ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[AND11]], [[C10]](s64) + ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C11]], [[LSHR8]] + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB1]], 32 + ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctlz_zero_poison_i32 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[COPY]] + ; RV64ZBB-NEXT: $x10 = COPY [[CLZW]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s32) = G_CTLZ_ZERO_POISON %0(s32) + %3:_(s64) = G_ANYEXT %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: ctlz_zero_poison_i64 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctlz_zero_poison_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[OR]], [[C1]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[OR1]], [[C2]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[OR2]], [[C3]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[OR3]], [[C4]](s64) + ; RV64I-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[LSHR4]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[OR4]], [[C5]](s64) + ; RV64I-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[LSHR5]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[OR5]], [[C]](s64) + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6148914691236517205 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[C6]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR5]], [[AND]] + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[SUB]], [[C1]](s64) + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3689348814741910323 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR7]], [[C7]] + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C7]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND1]], [[AND2]] + ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C2]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR8]], [[ADD]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 1085102592571150095 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C8]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673 + ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND3]], [[C9]] + ; RV64I-NEXT: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C10]](s64) + ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C11]], [[LSHR9]] + ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctlz_zero_poison_i64 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[COPY]](s64) + ; RV64ZBB-NEXT: $x10 = COPY [[CTLZ]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_CTLZ_ZERO_POISON %0(s64) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv32.mir new file mode 100644 index 0000000..aa26191 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv32.mir @@ -0,0 +1,231 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mattr=+m -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32I +# RUN: llc -mattr=+m -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32ZBB + +--- +name: ctpop_i8 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: ctpop_i8 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32) + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]] + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C4]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND3]], [[AND4]] + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C5]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[C]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32) + ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: ctpop_i8 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32) + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s8) = G_CTPOP %0(s8) + %3:_(s32) = G_ANYEXT %2(s8) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: ctpop_i16 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: ctpop_i16 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32) + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]] + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C4]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND3]], [[AND4]] + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C5]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C7]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[LSHR3]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C8]] + ; RV32I-NEXT: $x10 = COPY [[AND6]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: ctpop_i16 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32) + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s16) = G_CTPOP %0(s16) + %3:_(s32) = G_ANYEXT %2(s16) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: ctpop_i32 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: ctpop_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32) + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C4]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]] + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32) + ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: ctpop_i32 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[CTPOP]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_CTPOP %0(s32) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: ctpop_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: ctpop_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32) + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C4]](s32) + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]] + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32) + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32) + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]] + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[AND4]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C2]](s32) + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]] + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C3]] + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD2]], [[C4]](s32) + ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD2]] + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C5]] + ; RV32I-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[C6]] + ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C7]](s32) + ; RV32I-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[LSHR3]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: $x10 = COPY [[ADD4]](s32) + ; RV32I-NEXT: $x11 = COPY [[C8]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; RV32ZBB-LABEL: name: ctpop_i64 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s32) + ; RV32ZBB-NEXT: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[COPY1]](s32) + ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTPOP1]], [[CTPOP]] + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32ZBB-NEXT: $x10 = COPY [[ADD]](s32) + ; RV32ZBB-NEXT: $x11 = COPY [[C]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %3:_(s64) = G_CTPOP %0(s64) + %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) + $x10 = COPY %4(s32) + $x11 = COPY %5(s32) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir new file mode 100644 index 0000000..ad6d635 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir @@ -0,0 +1,330 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mattr=+m -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64I +# RUN: llc -mattr=+m -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64ZBB + +--- +name: ctpop_i8 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctpop_i8 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 85 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C2]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[AND1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 51 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C4]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C4]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND3]], [[AND4]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C5]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C6]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND5]], [[C]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C7]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctpop_i8 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[AND]](s64) + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[CTPOP]](s64) + ; RV64ZBB-NEXT: $x10 = COPY [[COPY1]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s8) = G_CTPOP %0(s8) + %3:_(s64) = G_ANYEXT %2(s8) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: ctpop_i16 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctpop_i16 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 21845 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C2]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[AND1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 13107 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C4]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C4]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND3]], [[AND4]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C5]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855 + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C6]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C7]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND5]], [[LSHR3]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C8]] + ; RV64I-NEXT: $x10 = COPY [[AND6]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctpop_i16 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[AND]](s64) + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[CTPOP]](s64) + ; RV64ZBB-NEXT: $x10 = COPY [[COPY1]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s16) = G_CTPOP %0(s16) + %3:_(s64) = G_ANYEXT %2(s16) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: ctpop_i32 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctpop_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C2]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[AND1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C4]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C4]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND3]], [[AND4]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG1]], [[C5]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[SEXT_INREG1]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG2]], [[C6]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND5]], [[C7]] + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[C8]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctpop_i32 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[AND]](s64) + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[CTPOP]](s64) + ; RV64ZBB-NEXT: $x10 = COPY [[COPY1]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s32) = G_CTPOP %0(s32) + %3:_(s64) = G_ANYEXT %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: ctpop_i64 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctpop_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s64) + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 6148914691236517205 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C1]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[AND]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[SUB]], [[C2]](s64) + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3689348814741910323 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C3]] + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C3]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND1]], [[AND2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C4]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1085102592571150095 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C5]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673 + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND3]], [[C6]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C7]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctpop_i64 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[COPY]](s64) + ; RV64ZBB-NEXT: $x10 = COPY [[CTPOP]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_CTPOP %0(s64) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: ctpop_i2 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctpop_i2 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 85 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C2]] + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND]](s64) + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY1]], [[AND1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C4]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 51 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C5]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C5]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND3]], [[AND4]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C6]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C7]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND5]], [[C]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C8]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctpop_i2 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[AND]](s64) + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[CTPOP]](s64) + ; RV64ZBB-NEXT: $x10 = COPY [[COPY1]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s2) = G_TRUNC %1(s64) + %2:_(s2) = G_CTPOP %0(s2) + %3:_(s64) = G_ANYEXT %2(s2) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: ctpop_i11 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: ctpop_i11 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2047 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 21845 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C2]] + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND]](s64) + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY1]], [[AND1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C4]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 13107 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C5]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C5]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND3]], [[AND4]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C6]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855 + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C7]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[C8]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND5]], [[LSHR3]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C9]] + ; RV64I-NEXT: $x10 = COPY [[AND6]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ctpop_i11 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2047 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[AND]](s64) + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[CTPOP]](s64) + ; RV64ZBB-NEXT: $x10 = COPY [[COPY1]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s11) = G_TRUNC %1(s64) + %2:_(s11) = G_CTPOP %0(s11) + %3:_(s64) = G_ANYEXT %2(s11) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir new file mode 100644 index 0000000..df05cf7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv32.mir @@ -0,0 +1,506 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mattr=+m -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32I +# RUN: llc -mattr=+m -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32ZBB + +--- +name: cttz_i8 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: cttz_i8 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]] + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32) + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND2]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32) + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]] + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]] + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND4]], [[AND5]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C6]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[C1]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C8]](s32) + ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: cttz_i8 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256 + ; RV32ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32) + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s8) = G_CTTZ %0(s8) + %3:_(s32) = G_ANYEXT %2(s8) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cttz_i16 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: cttz_i16 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]] + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32) + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND2]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32) + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]] + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]] + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND4]], [[AND5]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C6]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C8]](s32) + ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[AND6]], [[LSHR3]] + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C9]] + ; RV32I-NEXT: $x10 = COPY [[AND7]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: cttz_i16 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536 + ; RV32ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32) + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s16) = G_CTTZ %0(s16) + %3:_(s32) = G_ANYEXT %2(s16) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cttz_i32 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: cttz_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]] + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32) + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C3]](s32) + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]] + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C4]] + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]] + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C5]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C6]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND4]], [[C7]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C8]](s32) + ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: cttz_i32 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[CTTZ]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_CTTZ %0(s32) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: cttz_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cttz_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]] + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s32) + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C4]](s32) + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]] + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]] + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C6]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND4]], [[C8]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C9]](s32) + ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR3]], [[C10]] + ; RV32I-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]] + ; RV32I-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]] + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD4]] + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C2]](s32) + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]] + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND5]], [[AND6]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C4]](s32) + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C5]] + ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C5]] + ; RV32I-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND7]], [[AND8]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD5]], [[C6]](s32) + ; RV32I-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD5]] + ; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD6]], [[C7]] + ; RV32I-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[C8]] + ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C9]](s32) + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD3]], [[LSHR7]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: $x11 = COPY [[C]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; RV32ZBB-LABEL: name: cttz_i64 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY1]](s32) + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTTZ]], [[C1]] + ; RV32ZBB-NEXT: [[CTTZ1:%[0-9]+]]:_(s32) = G_CTTZ [[COPY]](s32) + ; RV32ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[CTTZ1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32ZBB-NEXT: $x11 = COPY [[C]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %3:_(s64) = G_CTTZ %0(s64) + %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) + $x10 = COPY %4(s32) + $x11 = COPY %5(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: cttz_zero_poison_i8 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: cttz_zero_poison_i8 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]] + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32) + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND2]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32) + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]] + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]] + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND4]], [[AND5]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C6]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[C1]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C8]](s32) + ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: cttz_zero_poison_i8 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256 + ; RV32ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32) + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s8) = G_CTTZ_ZERO_POISON %0(s8) + %3:_(s32) = G_ANYEXT %2(s8) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cttz_zero_poison_i16 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: cttz_zero_poison_i16 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]] + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32) + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND2]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]] + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32) + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]] + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]] + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND4]], [[AND5]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C6]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C8]](s32) + ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[AND6]], [[LSHR3]] + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C9]] + ; RV32I-NEXT: $x10 = COPY [[AND7]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: cttz_zero_poison_i16 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536 + ; RV32ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32) + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s16) = G_CTTZ_ZERO_POISON %0(s16) + %3:_(s32) = G_ANYEXT %2(s16) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cttz_zero_poison_i32 +body: | + bb.1: + liveins: $x10 + + ; RV32I-LABEL: name: cttz_zero_poison_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]] + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32) + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]] + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C3]](s32) + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]] + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C4]] + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]] + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C5]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C6]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND4]], [[C7]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C8]](s32) + ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: cttz_zero_poison_i32 + ; RV32ZBB: liveins: $x10 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[CTTZ]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_CTTZ_ZERO_POISON %0(s32) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: cttz_zero_poison_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cttz_zero_poison_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]] + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]] + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]] + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s32) + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]] + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]] + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C4]](s32) + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]] + ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]] + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]] + ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C6]](s32) + ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]] + ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]] + ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND4]], [[C8]] + ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C9]](s32) + ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR3]], [[C10]] + ; RV32I-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]] + ; RV32I-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]] + ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD4]] + ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C2]](s32) + ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]] + ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND5]], [[AND6]] + ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C4]](s32) + ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C5]] + ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C5]] + ; RV32I-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND7]], [[AND8]] + ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD5]], [[C6]](s32) + ; RV32I-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD5]] + ; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD6]], [[C7]] + ; RV32I-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[C8]] + ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C9]](s32) + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD3]], [[LSHR7]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: $x11 = COPY [[C]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; RV32ZBB-LABEL: name: cttz_zero_poison_i64 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY1]](s32) + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTTZ]], [[C1]] + ; RV32ZBB-NEXT: [[CTTZ1:%[0-9]+]]:_(s32) = G_CTTZ [[COPY]](s32) + ; RV32ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[CTTZ1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32ZBB-NEXT: $x11 = COPY [[C]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %3:_(s64) = G_CTTZ_ZERO_POISON %0(s64) + %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) + $x10 = COPY %4(s32) + $x11 = COPY %5(s32) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir new file mode 100644 index 0000000..289fce3 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir @@ -0,0 +1,454 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mattr=+m -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64I +# RUN: llc -mattr=+m -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64ZBB + +--- +name: cttz_i8 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: cttz_i8 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C1]](s64) + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 85 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C3]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 51 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C5]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C5]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD1]], [[C6]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C7]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C8]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: cttz_i8 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256 + ; RV64ZBB-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[OR]] + ; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s8) = G_CTTZ %0(s8) + %3:_(s64) = G_ANYEXT %2(s8) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cttz_i16 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: cttz_i16 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C1]](s64) + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 21845 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C3]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 13107 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C5]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C5]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD1]], [[C6]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C7]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[C8]](s64) + ; RV64I-NEXT: [[ADD3:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[LSHR3]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ADD3]], [[C9]] + ; RV64I-NEXT: $x10 = COPY [[AND7]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: cttz_i16 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65536 + ; RV64ZBB-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[OR]] + ; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s16) = G_CTTZ %0(s16) + %3:_(s64) = G_ANYEXT %2(s16) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cttz_i32 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: cttz_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[SEXT_INREG]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C1]](s64) + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C3]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C2]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C5]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C5]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG2]], [[C6]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[SEXT_INREG2]] + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD2]], 32 + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG3]], [[C7]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[C8]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C2]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[C9]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: cttz_i32 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[COPY]] + ; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s32) = G_CTTZ %0(s32) + %3:_(s64) = G_ANYEXT %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cttz_i64 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: cttz_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C1]](s64) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 6148914691236517205 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C2]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[SUB]], [[C3]](s64) + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3689348814741910323 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C4]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C4]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND2]], [[AND3]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD1]], [[C5]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1085102592571150095 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C6]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673 + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND4]], [[C7]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C8]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: cttz_i64 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[COPY]](s64) + ; RV64ZBB-NEXT: $x10 = COPY [[CTTZ]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_CTTZ %0(s64) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: cttz_zero_poison_i8 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: cttz_zero_poison_i8 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C1]](s64) + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 85 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C3]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 51 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C5]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C5]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD1]], [[C6]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C7]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C8]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: cttz_zero_poison_i8 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256 + ; RV64ZBB-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[OR]] + ; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s8) = G_CTTZ_ZERO_POISON %0(s8) + %3:_(s64) = G_ANYEXT %2(s8) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cttz_zero_poison_i16 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: cttz_zero_poison_i16 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C1]](s64) + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 21845 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C3]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 13107 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C5]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C5]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD1]], [[C6]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3855 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C7]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[C8]](s64) + ; RV64I-NEXT: [[ADD3:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[LSHR3]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ADD3]], [[C9]] + ; RV64I-NEXT: $x10 = COPY [[AND7]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: cttz_zero_poison_i16 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65536 + ; RV64ZBB-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[OR]] + ; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s16) = G_CTTZ_ZERO_POISON %0(s16) + %3:_(s64) = G_ANYEXT %2(s16) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cttz_zero_poison_i32 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: cttz_zero_poison_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[SEXT_INREG]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C1]](s64) + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C3]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C2]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C5]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C5]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG2]], [[C6]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[SEXT_INREG2]] + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD2]], 32 + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG3]], [[C7]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[C8]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C2]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[C9]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: cttz_zero_poison_i32 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[COPY]] + ; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s32) = G_CTTZ_ZERO_POISON %0(s32) + %3:_(s64) = G_ANYEXT %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cttz_zero_poison_i64 +body: | + bb.1: + liveins: $x10 + + ; RV64I-LABEL: name: cttz_zero_poison_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C1]](s64) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 6148914691236517205 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C2]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[SUB]], [[C3]](s64) + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3689348814741910323 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C4]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C4]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND2]], [[AND3]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD1]], [[C5]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1085102592571150095 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C6]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673 + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND4]], [[C7]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C8]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: cttz_zero_poison_i64 + ; RV64ZBB: liveins: $x10 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[COPY]](s64) + ; RV64ZBB-NEXT: $x10 = COPY [[CTTZ]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_CTTZ_ZERO_POISON %0(s64) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv32.mir new file mode 100644 index 0000000..3733a92 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv32.mir @@ -0,0 +1,629 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-I +# RUN: llc -mattr=+m -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-M +--- +name: sdiv_i7 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i7 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: sdiv_i7 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]] + ; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_SDIV %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i8 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i8 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: sdiv_i8 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]] + ; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_SDIV %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i16 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i16 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: sdiv_i16 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]] + ; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_SDIV %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i32 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i32 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: sdiv_i32 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SDIV %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i48 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i48 + ; CHECK-I: %xlo:_(s32) = COPY $x10 + ; CHECK-I-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-I-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-I-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C]](s32) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %yhi, [[C]](s32) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY %xlo(s32) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s32) + ; CHECK-I-NEXT: $x12 = COPY %ylo(s32) + ; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: sdiv_i48 + ; CHECK-M: %xlo:_(s32) = COPY $x10 + ; CHECK-M-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-M-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-M-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C]](s32) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %yhi, [[C]](s32) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY %xlo(s32) + ; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s32) + ; CHECK-M-NEXT: $x12 = COPY %ylo(s32) + ; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s32) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0 + %y:_(s48) = G_TRUNC %y0 + %z:_(s48) = G_SDIV %x, %y + %z0:_(s64) = G_ANYEXT %z + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sdiv_i64 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i64 + ; CHECK-I: %lo1:_(s32) = COPY $x10 + ; CHECK-I-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-I-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-I-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY %lo1(s32) + ; CHECK-I-NEXT: $x11 = COPY %hi1(s32) + ; CHECK-I-NEXT: $x12 = COPY %lo2(s32) + ; CHECK-I-NEXT: $x13 = COPY %hi2(s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: sdiv_i64 + ; CHECK-M: %lo1:_(s32) = COPY $x10 + ; CHECK-M-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-M-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-M-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY %lo1(s32) + ; CHECK-M-NEXT: $x11 = COPY %hi1(s32) + ; CHECK-M-NEXT: $x12 = COPY %lo2(s32) + ; CHECK-M-NEXT: $x13 = COPY %hi2(s32) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_SDIV %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: udiv_i7 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i7 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: udiv_i7 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]] + ; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_UDIV %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: udiv_i8 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i8 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: udiv_i8 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]] + ; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_UDIV %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: udiv_i16 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i16 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: udiv_i16 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]] + ; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_UDIV %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: udiv_i32 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i32 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: udiv_i32 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_UDIV %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: udiv_i48 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i48 + ; CHECK-I: %xlo:_(s32) = COPY $x10 + ; CHECK-I-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-I-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-I-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %xlo, [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xhi, [[C1]] + ; CHECK-I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %ylo, [[C]] + ; CHECK-I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %yhi, [[C1]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-I-NEXT: $x12 = COPY [[AND2]](s32) + ; CHECK-I-NEXT: $x13 = COPY [[AND3]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: udiv_i48 + ; CHECK-M: %xlo:_(s32) = COPY $x10 + ; CHECK-M-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-M-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-M-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %xlo, [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xhi, [[C1]] + ; CHECK-M-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %ylo, [[C]] + ; CHECK-M-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %yhi, [[C1]] + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-M-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-M-NEXT: $x12 = COPY [[AND2]](s32) + ; CHECK-M-NEXT: $x13 = COPY [[AND3]](s32) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0 + %y:_(s48) = G_TRUNC %y0 + %z:_(s48) = G_UDIV %x, %y + %z0:_(s64) = G_ANYEXT %z + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: udiv_i64 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i64 + ; CHECK-I: %lo1:_(s32) = COPY $x10 + ; CHECK-I-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-I-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-I-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY %lo1(s32) + ; CHECK-I-NEXT: $x11 = COPY %hi1(s32) + ; CHECK-I-NEXT: $x12 = COPY %lo2(s32) + ; CHECK-I-NEXT: $x13 = COPY %hi2(s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: udiv_i64 + ; CHECK-M: %lo1:_(s32) = COPY $x10 + ; CHECK-M-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-M-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-M-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY %lo1(s32) + ; CHECK-M-NEXT: $x11 = COPY %hi1(s32) + ; CHECK-M-NEXT: $x12 = COPY %lo2(s32) + ; CHECK-M-NEXT: $x13 = COPY %hi2(s32) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_UDIV %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: udivrem_i32 +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-I-LABEL: name: udivrem_i32 + ; CHECK-I: liveins: $x10, $x11 + ; CHECK-I-NEXT: {{ $}} + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]] + ; CHECK-I-NEXT: $x10 = COPY [[ADD]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: udivrem_i32 + ; CHECK-M: liveins: $x10, $x11 + ; CHECK-M-NEXT: {{ $}} + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UDIV]], [[UREM]] + ; CHECK-M-NEXT: $x10 = COPY [[ADD]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32), %3:_(s32) = G_UDIVREM %0, %1 + %4:_(s32) = G_ADD %2, %3 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: sdivrem_i32 +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-I-LABEL: name: sdivrem_i32 + ; CHECK-I: liveins: $x10, $x11 + ; CHECK-I-NEXT: {{ $}} + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]] + ; CHECK-I-NEXT: $x10 = COPY [[ADD]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: sdivrem_i32 + ; CHECK-M: liveins: $x10, $x11 + ; CHECK-M-NEXT: {{ $}} + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SDIV]], [[SREM]] + ; CHECK-M-NEXT: $x10 = COPY [[ADD]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32), %3:_(s32) = G_SDIVREM %0, %1 + %4:_(s32) = G_ADD %2, %3 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir new file mode 100644 index 0000000..657dd3c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir @@ -0,0 +1,698 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-I +# RUN: llc -mattr=+m -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-M +--- +name: sdiv_i8 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i8 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: sdiv_i8 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-M-NEXT: [[DIVW:%[0-9]+]]:_(s64) = G_DIVW [[ASHR]], [[ASHR1]] + ; CHECK-M-NEXT: $x10 = COPY [[DIVW]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_SDIV %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i15 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i15 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: sdiv_i15 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-M-NEXT: [[DIVW:%[0-9]+]]:_(s64) = G_DIVW [[ASHR]], [[ASHR1]] + ; CHECK-M-NEXT: $x10 = COPY [[DIVW]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_SDIV %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i16 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i16 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: sdiv_i16 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-M-NEXT: [[DIVW:%[0-9]+]]:_(s64) = G_DIVW [[ASHR]], [[ASHR1]] + ; CHECK-M-NEXT: $x10 = COPY [[DIVW]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_SDIV %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i32 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i32 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[SEXT_INREG1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: sdiv_i32 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[DIVW:%[0-9]+]]:_(s64) = G_DIVW [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: $x10 = COPY [[DIVW]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_SDIV %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i64 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i64 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: sdiv_i64 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SDIV %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i72 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i72 + ; CHECK-I: %xlo:_(s64) = COPY $x10 + ; CHECK-I-NEXT: %xhi:_(s64) = COPY $x11 + ; CHECK-I-NEXT: %ylo:_(s64) = COPY $x12 + ; CHECK-I-NEXT: %yhi:_(s64) = COPY $x13 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %xhi, [[C]](s64) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %yhi, [[C]](s64) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY %xlo(s64) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s64) + ; CHECK-I-NEXT: $x12 = COPY %ylo(s64) + ; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: sdiv_i72 + ; CHECK-M: %xlo:_(s64) = COPY $x10 + ; CHECK-M-NEXT: %xhi:_(s64) = COPY $x11 + ; CHECK-M-NEXT: %ylo:_(s64) = COPY $x12 + ; CHECK-M-NEXT: %yhi:_(s64) = COPY $x13 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %xhi, [[C]](s64) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %yhi, [[C]](s64) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY %xlo(s64) + ; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s64) + ; CHECK-M-NEXT: $x12 = COPY %ylo(s64) + ; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s64) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s64) = COPY $x10 + %xhi:_(s64) = COPY $x11 + %ylo:_(s64) = COPY $x12 + %yhi:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xlo(s64), %xhi(s64) + %y0:_(s128) = G_MERGE_VALUES %ylo(s64), %yhi(s64) + %x:_(s72) = G_TRUNC %x0 + %y:_(s72) = G_TRUNC %y0 + %z:_(s72) = G_SDIV %x, %y + %z0:_(s128) = G_ANYEXT %z + %zlo:_(s64), %zhi:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %zlo(s64) + $x11 = COPY %zhi(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sdiv_i128 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: sdiv_i128 + ; CHECK-I: %lo1:_(s64) = COPY $x10 + ; CHECK-I-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-I-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-I-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY %lo1(s64) + ; CHECK-I-NEXT: $x11 = COPY %hi1(s64) + ; CHECK-I-NEXT: $x12 = COPY %lo2(s64) + ; CHECK-I-NEXT: $x13 = COPY %hi2(s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: sdiv_i128 + ; CHECK-M: %lo1:_(s64) = COPY $x10 + ; CHECK-M-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-M-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-M-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY %lo1(s64) + ; CHECK-M-NEXT: $x11 = COPY %hi1(s64) + ; CHECK-M-NEXT: $x12 = COPY %lo2(s64) + ; CHECK-M-NEXT: $x13 = COPY %hi2(s64) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__divti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_SDIV %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: udiv_i8 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i8 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: udiv_i8 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-M-NEXT: [[DIVUW:%[0-9]+]]:_(s64) = G_DIVUW [[AND]], [[AND1]] + ; CHECK-M-NEXT: $x10 = COPY [[DIVUW]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_UDIV %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: udiv_i15 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i15 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: udiv_i15 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-M-NEXT: [[DIVUW:%[0-9]+]]:_(s64) = G_DIVUW [[AND]], [[AND1]] + ; CHECK-M-NEXT: $x10 = COPY [[DIVUW]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_UDIV %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: udiv_i16 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i16 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: udiv_i16 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-M-NEXT: [[DIVUW:%[0-9]+]]:_(s64) = G_DIVUW [[AND]], [[AND1]] + ; CHECK-M-NEXT: $x10 = COPY [[DIVUW]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_UDIV %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: udiv_i32 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i32 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: udiv_i32 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[DIVUW:%[0-9]+]]:_(s64) = G_DIVUW [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: $x10 = COPY [[DIVUW]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_UDIV %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: udiv_i64 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i64 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: udiv_i64 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_UDIV %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: udiv_i72 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i72 + ; CHECK-I: %xlo:_(s64) = COPY $x10 + ; CHECK-I-NEXT: %xhi:_(s64) = COPY $x11 + ; CHECK-I-NEXT: %ylo:_(s64) = COPY $x12 + ; CHECK-I-NEXT: %yhi:_(s64) = COPY $x13 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %xlo, [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xhi, [[C1]] + ; CHECK-I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %ylo, [[C]] + ; CHECK-I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %yhi, [[C1]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-I-NEXT: $x12 = COPY [[AND2]](s64) + ; CHECK-I-NEXT: $x13 = COPY [[AND3]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: udiv_i72 + ; CHECK-M: %xlo:_(s64) = COPY $x10 + ; CHECK-M-NEXT: %xhi:_(s64) = COPY $x11 + ; CHECK-M-NEXT: %ylo:_(s64) = COPY $x12 + ; CHECK-M-NEXT: %yhi:_(s64) = COPY $x13 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %xlo, [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xhi, [[C1]] + ; CHECK-M-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %ylo, [[C]] + ; CHECK-M-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %yhi, [[C1]] + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-M-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-M-NEXT: $x12 = COPY [[AND2]](s64) + ; CHECK-M-NEXT: $x13 = COPY [[AND3]](s64) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s64) = COPY $x10 + %xhi:_(s64) = COPY $x11 + %ylo:_(s64) = COPY $x12 + %yhi:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xlo(s64), %xhi(s64) + %y0:_(s128) = G_MERGE_VALUES %ylo(s64), %yhi(s64) + %x:_(s72) = G_TRUNC %x0 + %y:_(s72) = G_TRUNC %y0 + %z:_(s72) = G_UDIV %x, %y + %z0:_(s128) = G_ANYEXT %z + %zlo:_(s64), %zhi:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %zlo(s64) + $x11 = COPY %zhi(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: udiv_i128 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: udiv_i128 + ; CHECK-I: %lo1:_(s64) = COPY $x10 + ; CHECK-I-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-I-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-I-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY %lo1(s64) + ; CHECK-I-NEXT: $x11 = COPY %hi1(s64) + ; CHECK-I-NEXT: $x12 = COPY %lo2(s64) + ; CHECK-I-NEXT: $x13 = COPY %hi2(s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: udiv_i128 + ; CHECK-M: %lo1:_(s64) = COPY $x10 + ; CHECK-M-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-M-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-M-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY %lo1(s64) + ; CHECK-M-NEXT: $x11 = COPY %hi1(s64) + ; CHECK-M-NEXT: $x12 = COPY %lo2(s64) + ; CHECK-M-NEXT: $x13 = COPY %hi2(s64) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__udivti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_UDIV %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: udivrem_i64 +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-I-LABEL: name: udivrem_i64 + ; CHECK-I: liveins: $x10, $x11 + ; CHECK-I-NEXT: {{ $}} + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__udivdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY2]], [[COPY3]] + ; CHECK-I-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: udivrem_i64 + ; CHECK-M: liveins: $x10, $x11 + ; CHECK-M-NEXT: {{ $}} + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[UDIV]], [[UREM]] + ; CHECK-M-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64), %3:_(s64) = G_UDIVREM %0, %1 + %4:_(s64) = G_ADD %2, %3 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: sdivrem_i64 +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-I-LABEL: name: sdivrem_i64 + ; CHECK-I: liveins: $x10, $x11 + ; CHECK-I-NEXT: {{ $}} + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY2]], [[COPY3]] + ; CHECK-I-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: sdivrem_i64 + ; CHECK-M: liveins: $x10, $x11 + ; CHECK-M-NEXT: {{ $}} + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SDIV]], [[SREM]] + ; CHECK-M-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64), %3:_(s64) = G_SDIVREM %0, %1 + %4:_(s64) = G_ADD %2, %3 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-dyn-alloca-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-dyn-alloca-rv64.mir new file mode 100644 index 0000000..4810835 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-dyn-alloca-rv64.mir @@ -0,0 +1,40 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: test_simple_alloca +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: test_simple_alloca + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[AND]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x2 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0) + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND1]] + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64) + ; CHECK-NEXT: $x2 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: $x10 = COPY [[COPY2]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s64) = G_ZEXT %0(s32) + %5:_(s64) = G_CONSTANT i64 15 + %6:_(s64) = nuw G_ADD %2, %5 + %7:_(s64) = G_CONSTANT i64 -16 + %8:_(s64) = G_AND %6, %7 + %9:_(p0) = G_DYN_STACKALLOC %8(s64), 1 + $x10 = COPY %9(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir new file mode 100644 index 0000000..aff7d4d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir @@ -0,0 +1,161 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: sext_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sext_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_ADD %2, %3 + %5:_(s64) = G_SEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: zext_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: zext_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C]] + ; CHECK-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_ADD %2, %3 + %5:_(s64) = G_ZEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: anyext_16_i32 +body: | + ; CHECK-LABEL: name: anyext_16_i32 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s64), [[ANYEXT]], [[TRUNC]] + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0.entry: + bb.1: + liveins: $x10, $x11 + + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_TRUNC %1(s64) + %3:_(s32) = G_CONSTANT i32 0 + %4:_(s16) = G_LOAD %0(p0) :: (load (s16)) + %5:_(s32) = G_ANYEXT %4(s16) + %6:_(s32) = G_SELECT %2(s1), %5, %3 + %7:_(s64) = G_ANYEXT %6(s32) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: sext_16_i32 +body: | + ; CHECK-LABEL: name: sext_16_i32 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD]](s16) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s64), [[SEXT]], [[TRUNC]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0.entry: + bb.1: + liveins: $x10, $x11 + + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_TRUNC %1(s64) + %3:_(s32) = G_CONSTANT i32 0 + %4:_(s16) = G_LOAD %0(p0) :: (load (s16)) + %5:_(s32) = G_SEXT %4(s16) + %6:_(s32) = G_SELECT %2(s1), %5, %3 + %7:_(s64) = G_ANYEXT %6(s32) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: zext_16_i32 +body: | + ; CHECK-LABEL: name: zext_16_i32 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s16) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s64), [[ZEXT]], [[TRUNC]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0.entry: + bb.1: + liveins: $x10, $x11 + + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_TRUNC %1(s64) + %3:_(s32) = G_CONSTANT i32 0 + %4:_(s16) = G_LOAD %0(p0) :: (load (s16)) + %5:_(s32) = G_ZEXT %4(s16) + %6:_(s32) = G_SELECT %2(s1), %5, %3 + %7:_(s64) = G_ANYEXT %6(s32) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv32.mir new file mode 100644 index 0000000..a36ed53 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv32.mir @@ -0,0 +1,261 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: zextload_i8_i16 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i8_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8)) + %3:_(s32) = G_ANYEXT %2(s16) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: zextload_i8_i32 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i8_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8)) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: zextload_i16_i32 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i16_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16)) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: zextload_i8_i64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i8_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32) + ; CHECK-NEXT: $x11 = COPY [[C]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(p0) = COPY $x10 + %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s8)) + %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) + $x10 = COPY %3(s32) + $x11 = COPY %4(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: zextload_i16_i64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i16_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32) + ; CHECK-NEXT: $x11 = COPY [[C]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(p0) = COPY $x10 + %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s16)) + %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) + $x10 = COPY %3(s32) + $x11 = COPY %4(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: zextload_i32_i64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i32_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32) + ; CHECK-NEXT: $x11 = COPY [[C]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(p0) = COPY $x10 + %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32)) + %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) + $x10 = COPY %3(s32) + $x11 = COPY %4(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sextload_i8_i16 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i8_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8)) + %3:_(s32) = G_ANYEXT %2(s16) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: sextload_i8_i32 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i8_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8)) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: sextload_i16_i32 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i16_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16)) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: sextload_i8_i64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i8_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXTLOAD]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32) + ; CHECK-NEXT: $x11 = COPY [[ASHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(p0) = COPY $x10 + %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s8)) + %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) + $x10 = COPY %3(s32) + $x11 = COPY %4(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sextload_i16_i64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i16_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXTLOAD]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32) + ; CHECK-NEXT: $x11 = COPY [[ASHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(p0) = COPY $x10 + %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s16)) + %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) + $x10 = COPY %3(s32) + $x11 = COPY %4(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sextload_i32_i64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i32_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32) + ; CHECK-NEXT: $x11 = COPY [[ASHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(p0) = COPY $x10 + %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32)) + %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) + $x10 = COPY %3(s32) + $x11 = COPY %4(s32) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv64.mir new file mode 100644 index 0000000..031c130 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv64.mir @@ -0,0 +1,279 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: zextload_i8_i16 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i8_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8)) + %3:_(s64) = G_ANYEXT %2(s16) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: zextload_i8_i32 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i8_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8)) + %3:_(s64) = G_ANYEXT %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: zextload_i16_i32 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i16_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16)) + %3:_(s64) = G_ANYEXT %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: zextload_i8_i64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i8_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s8)) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: zextload_i16_i64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i16_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s16)) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: zextload_i32_i64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i32_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s32)) + ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32)) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: zextload_i8_i48 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: zextload_i8_i48 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s48) = G_ZEXTLOAD %0(p0) :: (load (s8)) + %3:_(s64) = G_ANYEXT %2(s48) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i8_i16 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i8_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8)) + %3:_(s64) = G_ANYEXT %2(s16) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i8_i32 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i8_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8)) + %3:_(s64) = G_ANYEXT %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i16_i32 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i16_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16)) + %3:_(s64) = G_ANYEXT %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i8_i64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i8_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s8)) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i16_i64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i16_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s16)) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i32_i64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i32_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s32)) + ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32)) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i8_i48 +alignment: 4 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sextload_i8_i48 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %2:_(s48) = G_SEXTLOAD %0(p0) :: (load (s8)) + %3:_(s64) = G_ANYEXT %2(s48) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-f16-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-f16-rv32.mir new file mode 100644 index 0000000..6aaaf50 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-f16-rv32.mir @@ -0,0 +1,312 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fcmp_oeq_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_oeq_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(oeq), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ogt_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ogt_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ogt), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ogt), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oge_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_oge_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oge), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(oge), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_olt_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_olt_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(olt), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(olt), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ole_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ole_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ole), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ole), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_one_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_one_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(one), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(one), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ord_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ord_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ord), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ord), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ueq_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ueq_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ueq), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ueq), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ugt_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ugt_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ugt), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ugt), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uge_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_uge_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(uge), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(uge), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ult_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ult_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ult), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ule_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ule_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ule), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ule), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_une_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_une_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(une), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(une), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uno_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_uno_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(uno), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(uno), %0(s16), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-f16-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-f16-rv64.mir new file mode 100644 index 0000000..0f604ca --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-f16-rv64.mir @@ -0,0 +1,312 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fcmp_oeq_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_oeq_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(oeq), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(oeq), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ogt_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ogt_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ogt), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ogt), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oge_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_oge_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(oge), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(oge), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_olt_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_olt_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(olt), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(olt), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ole_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ole_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ole), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ole), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_one_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_one_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(one), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(one), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ord_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ord_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ord), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ord), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ueq_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ueq_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ueq), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ueq), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ugt_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ugt_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ugt), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ugt), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uge_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_uge_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(uge), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(uge), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ult_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ult_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ult), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ult), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ule_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_ule_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ule), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(ule), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_une_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_une_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(une), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(une), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uno_f16 +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_uno_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(uno), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s1) = G_FCMP floatpred(uno), %0(s16), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-rv32.mir new file mode 100644 index 0000000..adc793b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-rv32.mir @@ -0,0 +1,620 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fcmp_oeq_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_oeq_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(oeq), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ogt_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ogt_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ogt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ogt), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oge_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_oge_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oge), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(oge), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_olt_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_olt_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(olt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(olt), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ole_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ole_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ole), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ole), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_one_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_one_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(one), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(one), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ord_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ord_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ord), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ueq_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ueq_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ueq), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ueq), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ugt_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ugt_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ugt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ugt), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uge_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_uge_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(uge), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(uge), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ult_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ult_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ult), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ule_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ule_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ule), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ule), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_une_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_une_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(une), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(une), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uno_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_uno_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(uno), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(uno), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oeq_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_oeq_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(oeq), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ogt_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ogt_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ogt), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ogt), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oge_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_oge_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oge), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(oge), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_olt_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_olt_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(olt), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(olt), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ole_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ole_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ole), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ole), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_one_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_one_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(one), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(one), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ord_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ord_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ord), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ord), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ueq_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ueq_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ueq), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ueq), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ugt_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ugt_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ugt), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ugt), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uge_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_uge_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(uge), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(uge), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ult_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ult_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ult), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ule_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ule_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ule), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ule), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_une_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_une_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(une), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(une), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uno_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_uno_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(uno), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(uno), %0(s64), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-rv64.mir new file mode 100644 index 0000000..9164a2b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-rv64.mir @@ -0,0 +1,620 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fcmp_oeq_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_oeq_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(oeq), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ogt_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ogt_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ogt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ogt), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oge_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_oge_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(oge), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(oge), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_olt_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_olt_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(olt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(olt), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ole_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ole_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ole), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ole), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_one_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_one_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(one), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(one), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ord_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ord_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ord), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ueq_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ueq_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ueq), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ueq), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ugt_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ugt_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ugt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ugt), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uge_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_uge_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(uge), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(uge), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ult_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ult_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ult), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ult), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ule_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_ule_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ule), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(ule), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_une_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_une_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(une), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(une), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uno_f32 +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_uno_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(uno), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s1) = G_FCMP floatpred(uno), %0(s32), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oeq_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_oeq_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(oeq), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ogt_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ogt_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ogt), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ogt), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_oge_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_oge_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(oge), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(oge), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_olt_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_olt_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(olt), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(olt), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ole_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ole_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ole), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ole), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_one_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_one_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(one), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(one), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ord_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ord_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ord), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ord), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ueq_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ueq_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ueq), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ueq), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ugt_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ugt_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ugt), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ugt), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uge_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_uge_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(uge), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(uge), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ult_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ult_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ult), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ult), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_ule_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_ule_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(ule), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(ule), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_une_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_une_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(une), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(une), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_uno_f64 +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_uno_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s64) = G_FCMP floatpred(uno), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s1) = G_FCMP floatpred(uno), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir new file mode 100644 index 0000000..6b437c1 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir @@ -0,0 +1,359 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fadd_f16 +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fadd_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FADD]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FADD %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fsub_f16 +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fsub_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FSUB]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FSUB %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fmul_f16 +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fmul_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FMUL]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FMUL %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fdiv_f16 +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fdiv_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FDIV:%[0-9]+]]:_(s16) = G_FDIV [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FDIV]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FDIV %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fma_f16 +body: | + bb.0: + liveins: $f10_h, $f11_h, $f12_h + + ; CHECK-LABEL: name: fma_f16 + ; CHECK: liveins: $f10_h, $f11_h, $f12_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f12_h + ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s16) = G_FMA [[COPY]], [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $f10_h = COPY [[FMA]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = COPY $f12_h + %3:_(s16) = G_FMA %0, %1, %2 + $f10_h = COPY %3(s16) + PseudoRET implicit $f10_h + +... +--- +name: fneg_f16 +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: fneg_f16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[COPY]] + ; CHECK-NEXT: $f10_h = COPY [[FNEG]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = G_FNEG %0 + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: fabs_f16 +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: fabs_f16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[COPY]] + ; CHECK-NEXT: $f10_h = COPY [[FABS]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = G_FABS %0 + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: fsqrt_f16 +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: fsqrt_f16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:_(s16) = G_FSQRT [[COPY]] + ; CHECK-NEXT: $f10_h = COPY [[FSQRT]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = G_FSQRT %0 + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: fmaxnum_f16 +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fmaxnum_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(s16) = G_FMAXNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FMAXNUM]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FMAXNUM %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fminnum_f16 +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fminnum_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s16) = G_FMINNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FMINNUM]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FMINNUM %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fmaximumnum_f16 +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fmaximumnum_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:_(s16) = G_FMAXIMUMNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FMAXIMUMNUM]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FMAXIMUMNUM %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fminimumnum_f16 +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fminimumnum_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:_(s16) = G_FMINIMUMNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FMINIMUMNUM]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FMINIMUMNUM %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fcopysign_f16_f16 +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcopysign_f16_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16) + ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FCOPYSIGN %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fcopysign_f16_f32 +body: | + bb.0: + liveins: $f10_h, $f11_f + + ; CHECK-LABEL: name: fcopysign_f16_f32 + ; CHECK: liveins: $f10_h, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s32) = COPY $f11_f + %2:_(s16) = G_FCOPYSIGN %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fcopysign_f32_f16 +body: | + bb.0: + liveins: $f10_f, $f11_h + + ; CHECK-LABEL: name: fcopysign_f32_f16 + ; CHECK: liveins: $f10_f, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16) + ; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s16) = COPY $f11_h + %2:_(s32) = G_FCOPYSIGN %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fcopysign_f16_f64 +body: | + bb.0: + liveins: $f10_h, $f11_d + + ; CHECK-LABEL: name: fcopysign_f16_f64 + ; CHECK: liveins: $f10_h, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s64) = COPY $f11_d + %2:_(s16) = G_FCOPYSIGN %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fcopysign_f64_f16 +body: | + bb.0: + liveins: $f10_d, $f11_h + + ; CHECK-LABEL: name: fcopysign_f64_f16 + ; CHECK: liveins: $f10_d, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s64) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16) + ; CHECK-NEXT: $f10_d = COPY [[FCOPYSIGN]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s16) = COPY $f11_h + %2:_(s64) = G_FCOPYSIGN %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir new file mode 100644 index 0000000..edd234f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir @@ -0,0 +1,586 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fadd_f32 +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fadd_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FADD]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FADD %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fsub_f32 +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fsub_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FSUB]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FSUB %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fmul_f32 +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fmul_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FMUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FMUL %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fdiv_f32 +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fdiv_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FDIV]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FDIV %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fma_f32 +body: | + bb.0: + liveins: $f10_f, $f11_f, $f12_f + + ; CHECK-LABEL: name: fma_f32 + ; CHECK: liveins: $f10_f, $f11_f, $f12_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f + ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $f10_f = COPY [[FMA]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = COPY $f12_f + %3:_(s32) = G_FMA %0, %1, %2 + $f10_f = COPY %3(s32) + PseudoRET implicit $f10_f + +... +--- +name: fneg_f32 +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: fneg_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] + ; CHECK-NEXT: $f10_f = COPY [[FNEG]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = G_FNEG %0 + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fabs_f32 +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: fabs_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]] + ; CHECK-NEXT: $f10_f = COPY [[FABS]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = G_FABS %0 + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fsqrt_f32 +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: fsqrt_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]] + ; CHECK-NEXT: $f10_f = COPY [[FSQRT]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = G_FSQRT %0 + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fmaxnum_f32 +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fmaxnum_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FMAXNUM]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FMAXNUM %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fminnum_f32 +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fminnum_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FMINNUM]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FMINNUM %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fmaximumnum_f32 +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fmaximumnum_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:_(s32) = G_FMAXIMUMNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FMAXIMUMNUM]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FMAXIMUMNUM %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fminimumnum_f32 +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fminimumnum_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:_(s32) = G_FMINIMUMNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FMINIMUMNUM]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FMINIMUMNUM %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fcopysign_f32_f32 +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcopysign_f32_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FCOPYSIGN %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fcopysign_f32_f64 +body: | + bb.0: + liveins: $f10_f, $f11_d + + ; CHECK-LABEL: name: fcopysign_f32_f64 + ; CHECK: liveins: $f10_f, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s64) = COPY $f11_d + %2:_(s32) = G_FCOPYSIGN %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fadd_f64 +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fadd_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FADD]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FADD %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fsub_f64 +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fsub_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FSUB]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FSUB %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fmul_f64 +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fmul_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FMUL]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FMUL %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fdiv_f64 +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fdiv_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FDIV]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FDIV %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fma_f64 +body: | + bb.0: + liveins: $f10_d, $f11_d, $f12_d + + ; CHECK-LABEL: name: fma_f64 + ; CHECK: liveins: $f10_d, $f11_d, $f12_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $f12_d + ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[COPY]], [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $f10_d = COPY [[FMA]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = COPY $f12_d + %3:_(s64) = G_FMA %0, %1, %2 + $f10_d = COPY %3(s64) + PseudoRET implicit $f10_d + +... +--- +name: fneg_f64 +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: fneg_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY]] + ; CHECK-NEXT: $f10_d = COPY [[FNEG]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = G_FNEG %0 + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fabs_f64 +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: fabs_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]] + ; CHECK-NEXT: $f10_d = COPY [[FABS]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = G_FABS %0 + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fsqrt_f64 +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: fsqrt_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]] + ; CHECK-NEXT: $f10_d = COPY [[FSQRT]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = G_FSQRT %0 + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fmaxnum_f64 +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fmaxnum_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(s64) = G_FMAXNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FMAXNUM]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FMAXNUM %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fminnum_f64 +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fminnum_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s64) = G_FMINNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FMINNUM]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FMINNUM %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fmaximumnum_f64 +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fmaximumnum_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:_(s64) = G_FMAXIMUMNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FMAXIMUMNUM]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FMAXIMUMNUM %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fminimumnum_f64 +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fminimumnum_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:_(s64) = G_FMINIMUMNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FMINIMUMNUM]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FMINIMUMNUM %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fcopysign_f64_f64 +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcopysign_f64_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s64) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: $f10_d = COPY [[FCOPYSIGN]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FCOPYSIGN %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fcopysign_f64_f32 +body: | + bb.0: + liveins: $f10_d, $f11_f + + ; CHECK-LABEL: name: fcopysign_f64_f32 + ; CHECK: liveins: $f10_d, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s64) = G_FCOPYSIGN [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: $f10_d = COPY [[FCOPYSIGN]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s32) = COPY $f11_f + %2:_(s64) = G_FCOPYSIGN %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ext-trunc-f16.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ext-trunc-f16.mir new file mode 100644 index 0000000..4b09154 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ext-trunc-f16.mir @@ -0,0 +1,82 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fpext_f32 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fpext_f32 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[COPY]](s16) + ; CHECK-NEXT: $f10_f = COPY [[FPEXT]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s16) = COPY $f10_h + %1:_(s32) = G_FPEXT %0(s16) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fptrunc_f32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptrunc_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY]](s32) + ; CHECK-NEXT: $f10_h = COPY [[FPTRUNC]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s32) = COPY $f10_f + %1:_(s16) = G_FPTRUNC %0(s32) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: fpext_f64 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fpext_f64 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s16) + ; CHECK-NEXT: $f10_d = COPY [[FPEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s16) = COPY $f10_h + %1:_(s64) = G_FPEXT %0(s16) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fptrunc_f64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptrunc_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY]](s64) + ; CHECK-NEXT: $f10_h = COPY [[FPTRUNC]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s64) = COPY $f10_d + %1:_(s16) = G_FPTRUNC %0(s64) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ext-trunc.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ext-trunc.mir new file mode 100644 index 0000000..29355f5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ext-trunc.mir @@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fpext +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fpext + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s32) + ; CHECK-NEXT: $f10_d = COPY [[FPEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s32) = COPY $f10_f + %1:_(s64) = G_FPEXT %0(s32) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fptrunc +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptrunc + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[COPY]](s64) + ; CHECK-NEXT: $f10_f = COPY [[FPTRUNC]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s64) = COPY $f10_d + %1:_(s32) = G_FPTRUNC %0(s64) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-load-store.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-load-store.mir new file mode 100644 index 0000000..5afc3df --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-load-store.mir @@ -0,0 +1,82 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fp_store_f32 +body: | + bb.1: + liveins: $x10, $f10_f + + ; CHECK-LABEL: name: fp_store_f32 + ; CHECK: liveins: $x10, $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32)) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_(s32) = COPY $f10_f + G_STORE %1(s32), %0(p0) :: (store (s32)) + PseudoRET + +... +--- +name: fp_store_f64 +body: | + bb.1: + liveins: $x10, $f10_d + + ; CHECK-LABEL: name: fp_store_f64 + ; CHECK: liveins: $x10, $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64)) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $f10_d + G_STORE %1(s64), %0(p0) :: (store (s64)) + PseudoRET + +... +--- +name: fp_load_f32 +body: | + bb.1: + liveins: $x10, $f10_f + + ; CHECK-LABEL: name: fp_load_f32 + ; CHECK: liveins: $x10, $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32)) + ; CHECK-NEXT: $f10_f = COPY [[LOAD]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(p0) = COPY $x10 + %2:_(s32) = G_LOAD %0(p0) :: (load (s32)) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fp_load_f64 +body: | + bb.1: + liveins: $x10, $f10_d + + ; CHECK-LABEL: name: fp_load_f64 + ; CHECK: liveins: $x10, $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64)) + ; CHECK-NEXT: $f10_d = COPY [[LOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(p0) = COPY $x10 + %2:_(s64) = G_LOAD %0(p0) :: (load (s64)) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-select-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-select-rv32.mir new file mode 100644 index 0000000..487608f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-select-rv32.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: select_f64 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10, $f10_d, $f11_d + + ; CHECK-LABEL: name: select_f64 + ; CHECK: liveins: $x10, $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $f11_d + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $f10_d = COPY [[SELECT]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %3:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s32) + %1:_(s64) = COPY $f10_d + %2:_(s64) = COPY $f11_d + %4:_(s64) = G_SELECT %0(s1), %1, %2 + $f10_d = COPY %4(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv32.mir new file mode 100644 index 0000000..27e52fe --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv32.mir @@ -0,0 +1,142 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fptoui_s1_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s1_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s1) = G_FPTOUI %0(s16) + %2:_(s32) = G_ANYEXT %1(s1) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s8_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s8_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s8) = G_FPTOSI %0(s16) + %2:_(s32) = G_ANYEXT %1(s8) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s8_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s8_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s8) = G_FPTOUI %0(s16) + %2:_(s32) = G_ANYEXT %1(s8) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s16_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s16_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = G_FPTOSI %0(s16) + %2:_(s32) = G_ANYEXT %1(s16) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s16_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s16_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = G_FPTOUI %0(s16) + %2:_(s32) = G_ANYEXT %1(s16) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s32_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s32) = G_FPTOSI %0(s16) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s32_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s32) = G_FPTOUI %0(s16) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir new file mode 100644 index 0000000..55bf47d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir @@ -0,0 +1,202 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fptosi_s1_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s1_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s1) = G_FPTOSI %0(s16) + %2:_(s64) = G_ANYEXT %1(s1) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s1_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s1_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s1) = G_FPTOUI %0(s16) + %2:_(s64) = G_ANYEXT %1(s1) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s8_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s8_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s8) = G_FPTOSI %0(s16) + %2:_(s64) = G_ANYEXT %1(s8) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s8_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s8_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s8) = G_FPTOUI %0(s16) + %2:_(s64) = G_ANYEXT %1(s8) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s16_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s16_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = G_FPTOSI %0(s16) + %2:_(s64) = G_ANYEXT %1(s16) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s16_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s16_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = G_FPTOUI %0(s16) + %2:_(s64) = G_ANYEXT %1(s16) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s32_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s32) = G_FPTOSI %0(s16) + %2:_(s64) = G_ANYEXT %1(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s32_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s32) = G_FPTOUI %0(s16) + %2:_(s64) = G_ANYEXT %1(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s64_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s64_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s64) = G_FPTOSI %0(s16) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s64_s16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s64_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s64) = G_FPTOUI %0(s16) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv32-libcall.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv32-libcall.mir new file mode 100644 index 0000000..06ebc61 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv32-libcall.mir @@ -0,0 +1,395 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=-d -mattr=-f -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fptosi_s1_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s1_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixsfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_FPTOSI %0:_(s32) + %2:_(s32) = G_ANYEXT %1:_(s1) + $x10 = COPY %2:_(s32) + PseudoRET implicit $x10 +... +--- +name: fptoui_s1_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s1_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunssfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_FPTOUI %0:_(s32) + %2:_(s32) = G_ANYEXT %1:_(s1) + $x10 = COPY %2:_(s32) + PseudoRET implicit $x10 +... +--- +name: fptosi_s8_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s8_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixsfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s8) = G_FPTOSI %0:_(s32) + %2:_(s32) = G_ANYEXT %1:_(s8) + $x10 = COPY %2:_(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s8_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s8_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunssfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s8) = G_FPTOUI %0:_(s32) + %2:_(s32) = G_ANYEXT %1:_(s8) + $x10 = COPY %2:_(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s16_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s16_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixsfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s16) = G_FPTOSI %0:_(s32) + %2:_(s32) = G_ANYEXT %1:_(s16) + $x10 = COPY %2:_(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s16_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s16_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunssfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s16) = G_FPTOUI %0:_(s32) + %2:_(s32) = G_ANYEXT %1:_(s16) + $x10 = COPY %2:_(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s32_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixsfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_FPTOSI %0:_(s32) + $x10 = COPY %1:_(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s32_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunssfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_FPTOUI %0:_(s32) + $x10 = COPY %1:_(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s1_s64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: fptosi_s1_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1:_(s32), %2:_(s32) + %3:_(s1) = G_FPTOSI %0:_(s64) + %4:_(s32) = G_ANYEXT %3:_(s1) + $x10 = COPY %4:_(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s1_s64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: fptoui_s1_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunsdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1:_(s32), %2:_(s32) + %3:_(s1) = G_FPTOUI %0:_(s64) + %4:_(s32) = G_ANYEXT %3:_(s1) + $x10 = COPY %4:_(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s8_s64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: fptosi_s8_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1:_(s32), %2:_(s32) + %3:_(s8) = G_FPTOSI %0:_(s64) + %4:_(s32) = G_ANYEXT %3:_(s8) + $x10 = COPY %4:_(s32) + PseudoRET implicit $x10 +... +--- +name: fptoui_s8_s64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: fptoui_s8_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunsdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1:_(s32), %2:_(s32) + %3:_(s8) = G_FPTOUI %0:_(s64) + %4:_(s32) = G_ANYEXT %3:_(s8) + $x10 = COPY %4:_(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s16_s64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: fptosi_s16_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1:_(s32), %2:_(s32) + %3:_(s16) = G_FPTOSI %0:_(s64) + %4:_(s32) = G_ANYEXT %3:_(s16) + $x10 = COPY %4:_(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s16_s64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: fptoui_s16_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunsdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1:_(s32), %2:_(s32) + %3:_(s16) = G_FPTOUI %0:_(s64) + %4:_(s32) = G_ANYEXT %3:_(s16) + $x10 = COPY %4:_(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: fptosi_s32_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1:_(s32), %2:_(s32) + %3:_(s32) = G_FPTOSI %0:_(s64) + $x10 = COPY %3:_(s32) + PseudoRET implicit $x10 +... +--- +name: fptoui_s32_s64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: fptoui_s32_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunsdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1:_(s32), %2:_(s32) + %3:_(s32) = G_FPTOUI %0:_(s64) + $x10 = COPY %3:_(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv32.mir new file mode 100644 index 0000000..d32b435 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv32.mir @@ -0,0 +1,320 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fptosi_s1_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s1_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s1) = G_FPTOSI %0(s32) + %2:_(s32) = G_ANYEXT %1(s1) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s1_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s1_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s1) = G_FPTOUI %0(s32) + %2:_(s32) = G_ANYEXT %1(s1) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s8_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s8_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s8) = G_FPTOSI %0(s32) + %2:_(s32) = G_ANYEXT %1(s8) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s8_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s8_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s8) = G_FPTOUI %0(s32) + %2:_(s32) = G_ANYEXT %1(s8) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s16_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s16_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s16) = G_FPTOSI %0(s32) + %2:_(s32) = G_ANYEXT %1(s16) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s16_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s16_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s16) = G_FPTOUI %0(s32) + %2:_(s32) = G_ANYEXT %1(s16) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s32_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = G_FPTOSI %0(s32) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s32_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = G_FPTOUI %0(s32) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s1_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s1_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s1) = G_FPTOSI %0(s64) + %2:_(s32) = G_ANYEXT %1(s1) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s1_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s1_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s1) = G_FPTOUI %0(s64) + %2:_(s32) = G_ANYEXT %1(s1) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s8_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s8_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s8) = G_FPTOSI %0(s64) + %2:_(s32) = G_ANYEXT %1(s8) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s8_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s8_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s8) = G_FPTOUI %0(s64) + %2:_(s32) = G_ANYEXT %1(s8) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s16_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s16_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s16) = G_FPTOSI %0(s64) + %2:_(s32) = G_ANYEXT %1(s16) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s16_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s16_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s16) = G_FPTOUI %0(s64) + %2:_(s32) = G_ANYEXT %1(s16) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s32_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s32) = G_FPTOSI %0(s64) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s32_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s32) = G_FPTOUI %0(s64) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64-libcall.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64-libcall.mir new file mode 100644 index 0000000..629ad24 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64-libcall.mir @@ -0,0 +1,471 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=-d -mattr=-f -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fptosi_s1_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s1_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixsfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1:_(s64) + %2:_(s1) = G_FPTOSI %0:_(s32) + %3:_(s64) = G_ANYEXT %2:_(s1) + $x10 = COPY %3:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s1_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s1_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunssfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1:_(s64) + %2:_(s1) = G_FPTOUI %0:_(s32) + %3:_(s64) = G_ANYEXT %2:_(s1) + $x10 = COPY %3:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s8_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s8_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixsfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1:_(s64) + %2:_(s8) = G_FPTOSI %0:_(s32) + %3:_(s64) = G_ANYEXT %2:_(s8) + $x10 = COPY %3:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s8_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s8_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunssfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1:_(s64) + %2:_(s8) = G_FPTOUI %0:_(s32) + %3:_(s64) = G_ANYEXT %2:_(s8) + $x10 = COPY %3:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s16_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s16_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixsfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1:_(s64) + %2:_(s16) = G_FPTOSI %0:_(s32) + %3:_(s64) = G_ANYEXT %2:_(s16) + $x10 = COPY %3:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s16_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s16_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunssfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1:_(s64) + %2:_(s16) = G_FPTOUI %0:_(s32) + %3:_(s64) = G_ANYEXT %2:_(s16) + $x10 = COPY %3:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s32_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixsfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1:_(s64) + %2:_(s32) = G_FPTOSI %0:_(s32) + %3:_(s64) = G_ANYEXT %2:_(s32) + $x10 = COPY %3:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s32 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s32_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunssfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1:_(s64) + %2:_(s32) = G_FPTOUI %0:_(s32) + %3:_(s64) = G_ANYEXT %2:_(s32) + $x10 = COPY %3:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s64_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s64_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixsfdi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s64) = G_FPTOSI %0(s32) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s64_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s64_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunssfdi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s64) = G_FPTOUI %0(s32) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s1_s64 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s1_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_FPTOSI %0:_(s64) + %2:_(s64) = G_ANYEXT %1:_(s1) + $x10 = COPY %2:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s1_s64 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s1_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunsdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_FPTOUI %0:_(s64) + %2:_(s64) = G_ANYEXT %1:_(s1) + $x10 = COPY %2:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s8_s64 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s8_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s8) = G_FPTOSI %0:_(s64) + %2:_(s64) = G_ANYEXT %1:_(s8) + $x10 = COPY %2:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s8_s64 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s8_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunsdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s8) = G_FPTOUI %0:_(s64) + %2:_(s64) = G_ANYEXT %1:_(s8) + $x10 = COPY %2:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s16_s64 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s16_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s16) = G_FPTOSI %0:_(s64) + %2:_(s64) = G_ANYEXT %1:_(s16) + $x10 = COPY %2:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s16_s64 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s16_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunsdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s16) = G_FPTOUI %0:_(s64) + %2:_(s64) = G_ANYEXT %1:_(s16) + $x10 = COPY %2:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s64 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s32_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s32) = G_FPTOSI %0:_(s64) + %2:_(s64) = G_ANYEXT %1:_(s32) + $x10 = COPY %2:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s64 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s32_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunsdfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s32) = G_FPTOUI %0:_(s64) + %2:_(s64) = G_ANYEXT %1:_(s32) + $x10 = COPY %2:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s64_s64 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptosi_s64_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixdfdi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_FPTOSI %0:_(s64) + $x10 = COPY %1:_(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s64_s64 +body: | + bb.1: + liveins: $x10 + ; CHECK-LABEL: name: fptoui_s64_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__fixunsdfdi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_FPTOUI %0:_(s64) + $x10 = COPY %1:_(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64.mir new file mode 100644 index 0000000..657d3a4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64.mir @@ -0,0 +1,400 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fptosi_s1_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s1_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s32), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s1) = G_FPTOSI %0(s32) + %2:_(s64) = G_ANYEXT %1(s1) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s1_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s1_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s32), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s1) = G_FPTOUI %0(s32) + %2:_(s64) = G_ANYEXT %1(s1) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s8_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s8_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s32), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s8) = G_FPTOSI %0(s32) + %2:_(s64) = G_ANYEXT %1(s8) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s8_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s8_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s32), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s8) = G_FPTOUI %0(s32) + %2:_(s64) = G_ANYEXT %1(s8) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s16_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s16_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s32), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s16) = G_FPTOSI %0(s32) + %2:_(s64) = G_ANYEXT %1(s16) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s16_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s16_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s32), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s16) = G_FPTOUI %0(s32) + %2:_(s64) = G_ANYEXT %1(s16) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s32_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s32), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = G_FPTOSI %0(s32) + %2:_(s64) = G_ANYEXT %1(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s32_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s32), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = G_FPTOUI %0(s32) + %2:_(s64) = G_ANYEXT %1(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s64_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s64_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s64) = G_FPTOSI %0(s32) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s64_s32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s64_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s64) = G_FPTOUI %0(s32) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s1_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s1_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s64), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s1) = G_FPTOSI %0(s64) + %2:_(s64) = G_ANYEXT %1(s1) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s1_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s1_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s64), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s1) = G_FPTOUI %0(s64) + %2:_(s64) = G_ANYEXT %1(s1) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s8_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s8_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s64), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s8) = G_FPTOSI %0(s64) + %2:_(s64) = G_ANYEXT %1(s8) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s8_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s8_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s64), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s8) = G_FPTOUI %0(s64) + %2:_(s64) = G_ANYEXT %1(s8) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s16_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s16_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s64), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s16) = G_FPTOSI %0(s64) + %2:_(s64) = G_ANYEXT %1(s16) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s16_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s16_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s64), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s16) = G_FPTOUI %0(s64) + %2:_(s64) = G_ANYEXT %1(s16) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s32_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:_(s64) = G_FCVT_W_RV64 [[COPY]](s64), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s32) = G_FPTOSI %0(s64) + %2:_(s64) = G_ANYEXT %1(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s32_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:_(s64) = G_FCVT_WU_RV64 [[COPY]](s64), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s32) = G_FPTOUI %0(s64) + %2:_(s64) = G_ANYEXT %1(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s64_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s64_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = G_FPTOSI %0(s64) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s64_s64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s64_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = G_FPTOUI %0(s64) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frame-index-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frame-index-rv32.mir new file mode 100644 index 0000000..1e1879a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frame-index-rv32.mir @@ -0,0 +1,29 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- | + + define ptr @alloca32() { + entry: + %ptr0 = alloca i32, align 4 + ret ptr %ptr0 + } + +... +--- +name: alloca32 +stack: + - { id: 0, name: ptr0, type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.1.entry: + ; CHECK-LABEL: name: alloca32 + ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr0 + ; CHECK-NEXT: $x10 = COPY [[FRAME_INDEX]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = G_FRAME_INDEX %stack.0.ptr0 + $x10 = COPY %0(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frame-index-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frame-index-rv64.mir new file mode 100644 index 0000000..6d083d8 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frame-index-rv64.mir @@ -0,0 +1,29 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- | + + define ptr @alloca64() { + entry: + %ptr0 = alloca i64, align 4 + ret ptr %ptr0 + } + +... +--- +name: alloca64 +stack: + - { id: 0, name: ptr0, type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.1.entry: + ; CHECK-LABEL: name: alloca64 + ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr0 + ; CHECK-NEXT: $x10 = COPY [[FRAME_INDEX]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = G_FRAME_INDEX %stack.0.ptr0 + $x10 = COPY %0(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir new file mode 100644 index 0000000..4217910 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir @@ -0,0 +1,62 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -mattr=+f,+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: freeze_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: freeze_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FREEZE]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = G_FREEZE %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: freeze_f32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: freeze_f32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]] + ; CHECK-NEXT: $f10_f = COPY [[FREEZE]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s32) = COPY $f10_f + %2:_(s32) = G_FREEZE %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: freeze_nxv2i1 +body: | + bb.0.entry: + ; CHECK-LABEL: name: freeze_nxv2i1 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_() = G_FREEZE [[COPY]] + ; CHECK-NEXT: $v8 = COPY [[FREEZE]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %2:_() = G_FREEZE %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: freeze_nxv2i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: freeze_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_() = G_FREEZE [[COPY]] + ; CHECK-NEXT: $v8 = COPY [[FREEZE]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %2:_() = G_FREEZE %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv64.mir new file mode 100644 index 0000000..355e225 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv64.mir @@ -0,0 +1,96 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv64 -mattr=+f,+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: freeze_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: freeze_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[TRUNC]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s32) = G_TRUNC %1(s64) + %3:_(s32) = G_FREEZE %2 + %4:_(s64) = G_ANYEXT %3(s32) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: freeze_f32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: freeze_f32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]] + ; CHECK-NEXT: $f10_f = COPY [[FREEZE]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s32) = COPY $f10_f + %2:_(s32) = G_FREEZE %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: freeze_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: freeze_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FREEZE]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = G_FREEZE %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: freeze_nxv2i1 +body: | + bb.0.entry: + ; CHECK-LABEL: name: freeze_nxv2i1 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_() = G_FREEZE [[COPY]] + ; CHECK-NEXT: $v8 = COPY [[FREEZE]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %2:_() = G_FREEZE %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: freeze_nxv2i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: freeze_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_() = G_FREEZE [[COPY]] + ; CHECK-NEXT: $v8 = COPY [[FREEZE]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %2:_() = G_FREEZE %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: freeze_nxv2i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: freeze_nxv2i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_() = G_FREEZE [[COPY]] + ; CHECK-NEXT: $v8m2 = COPY [[FREEZE]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %2:_() = G_FREEZE %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv32.mir new file mode 100644 index 0000000..adf3f45 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv32.mir @@ -0,0 +1,130 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv32 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s +--- +name: frem_f32 +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: frem_f32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_FREM %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: frem_f64 +body: | + bb.1.entry: + liveins: $x10, $x11, $x12, $x13 + + ; CHECK-LABEL: name: frem_f64 + ; CHECK: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: $x12 = COPY [[COPY2]](s32) + ; CHECK-NEXT: $x13 = COPY [[COPY3]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmod, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: $x10 = COPY [[COPY4]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY5]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64) = G_FREM %0, %1 + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $x10 = COPY %7(s32) + $x11 = COPY %8(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: frem_f16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: frem_f16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) + ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16) + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[FPEXT]](s32) + ; CHECK-NEXT: $x11 = COPY [[FPEXT1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_FREM %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: frem_v2f32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: frem_v2f32 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $v9 + ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) + ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[UV]](s32) + ; CHECK-NEXT: $x11 = COPY [[UV2]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[UV1]](s32) + ; CHECK-NEXT: $x11 = COPY [[UV3]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: $v8 = COPY [[BUILD_VECTOR]](<2 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(<2 x s32>) = COPY $v8 + %1:_(<2 x s32>) = COPY $v9 + %2:_(<2 x s32>) = G_FREM %0, %1 + $v8 = COPY %2(<2 x s32>) + PseudoRET implicit $v8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv64.mir new file mode 100644 index 0000000..5db66bb --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv64.mir @@ -0,0 +1,130 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s +--- +name: frem_f32 +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: frem_f32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32) = G_FREM %0, %1 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: frem_f64 +body: | + bb.1.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: frem_f64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmod, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_FREM %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: frem_f16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: frem_f16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) + ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16) + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPEXT]](s32) + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[FPEXT1]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: $x11 = COPY [[ANYEXT1]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64) + ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[TRUNC2]](s32) + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTRUNC]](s16) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_FREM %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: frem_v2f32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: frem_v2f32 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $v9 + ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) + ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32) + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV2]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: $x11 = COPY [[ANYEXT1]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64) + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32) + ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[UV3]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT2]](s64) + ; CHECK-NEXT: $x11 = COPY [[ANYEXT3]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64) + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32) + ; CHECK-NEXT: $v8 = COPY [[BUILD_VECTOR]](<2 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(<2 x s32>) = COPY $v8 + %1:_(<2 x s32>) = COPY $v9 + %2:_(<2 x s32>) = G_FREM %0, %1 + $v8 = COPY %2(<2 x s32>) + PseudoRET implicit $v8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv32.mir new file mode 100644 index 0000000..1b77262 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv32.mir @@ -0,0 +1,364 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fshl_i8 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshl_i8 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND1]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %3:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %3(s32) + %4:_(s32) = COPY $x11 + %1:_(s8) = G_TRUNC %4(s32) + %5:_(s32) = COPY $x12 + %2:_(s8) = G_TRUNC %5(s32) + %6:_(s8) = G_FSHL %0, %1, %2(s8) + %7:_(s32) = G_ANYEXT %6(s8) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 + +... +--- +name: fshl_i16 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshl_i16 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND1]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %3:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %3(s32) + %4:_(s32) = COPY $x11 + %1:_(s16) = G_TRUNC %4(s32) + %5:_(s32) = COPY $x12 + %2:_(s16) = G_TRUNC %5(s32) + %6:_(s16) = G_FSHL %0, %1, %2(s16) + %7:_(s32) = G_ANYEXT %6(s16) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 + +... +--- +name: fshl_i32 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshl_i32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND1]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = G_FSHL %0, %1, %2(s32) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fshl_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13, $x14, $x15 + + ; CHECK-LABEL: name: fshl_i64 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14, $x15 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY4]], [[C2]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[C4]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[AND]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[C4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[SUB1]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[AND]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SHL]], [[C1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY1]], [[SELECT1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C3]](s32) + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C5]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL3]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C3]](s32) + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[AND1]], [[C4]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[AND1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[C4]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[C1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR2]], [[AND1]](s32) + ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[AND1]](s32) + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SUB3]](s32) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[SHL4]] + ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR2]], [[SUB2]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR2]], [[LSHR5]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[OR1]], [[SELECT3]] + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[LSHR3]], [[C1]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[SELECT4]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[SELECT2]], [[SELECT5]] + ; CHECK-NEXT: $x10 = COPY [[OR3]](s32) + ; CHECK-NEXT: $x11 = COPY [[OR4]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %3:_(s32) = COPY $x10 + %4:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %3(s32), %4(s32) + %5:_(s32) = COPY $x12 + %6:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %5(s32), %6(s32) + %7:_(s32) = COPY $x14 + %8:_(s32) = COPY $x15 + %2:_(s64) = G_MERGE_VALUES %7(s32), %8(s32) + %9:_(s64) = G_FSHL %0, %1, %2(s64) + %10:_(s32), %11:_(s32) = G_UNMERGE_VALUES %9(s64) + $x10 = COPY %10(s32) + $x11 = COPY %11(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: fshr_i8 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshr_i8 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %3:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %3(s32) + %4:_(s32) = COPY $x11 + %1:_(s8) = G_TRUNC %4(s32) + %5:_(s32) = COPY $x12 + %2:_(s8) = G_TRUNC %5(s32) + %6:_(s8) = G_FSHR %0, %1, %2(s8) + %7:_(s32) = G_ANYEXT %6(s8) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 + +... +--- +name: fshr_i16 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshr_i16 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %3:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %3(s32) + %4:_(s32) = COPY $x11 + %1:_(s16) = G_TRUNC %4(s32) + %5:_(s32) = COPY $x12 + %2:_(s16) = G_TRUNC %5(s32) + %6:_(s16) = G_FSHR %0, %1, %2(s16) + %7:_(s32) = G_ANYEXT %6(s16) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 + +... +--- +name: fshr_i32 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshr_i32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[AND]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = G_FSHR %0, %1, %2(s32) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: fshr_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13, $x14, $x15 + + ; CHECK-LABEL: name: fshr_i64 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14, $x15 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY4]], [[C2]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C3]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C3]](s32) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C4]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND1]], [[C5]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C5]], [[AND1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[C5]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[C1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SHL]], [[SUB1]](s32) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[AND1]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL3]] + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[SUB]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SHL2]], [[C1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR1]], [[SHL4]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[OR]], [[SELECT1]] + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[C5]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C5]], [[AND]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[C5]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C1]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[AND]](s32) + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[AND]](s32) + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[SUB3]](s32) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL5]] + ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[SUB2]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR2]], [[LSHR4]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[COPY2]], [[SELECT3]] + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[LSHR2]], [[C1]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[SELECT4]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[SELECT2]], [[SELECT5]] + ; CHECK-NEXT: $x10 = COPY [[OR3]](s32) + ; CHECK-NEXT: $x11 = COPY [[OR4]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %3:_(s32) = COPY $x10 + %4:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %3(s32), %4(s32) + %5:_(s32) = COPY $x12 + %6:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %5(s32), %6(s32) + %7:_(s32) = COPY $x14 + %8:_(s32) = COPY $x15 + %2:_(s64) = G_MERGE_VALUES %7(s32), %8(s32) + %9:_(s64) = G_FSHR %0, %1, %2(s64) + %10:_(s32), %11:_(s32) = G_UNMERGE_VALUES %9(s64) + $x10 = COPY %10(s32) + $x11 = COPY %11(s32) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir new file mode 100644 index 0000000..f3d95d3 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir @@ -0,0 +1,294 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: fshl_i8 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshl_i8 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C2]](s64) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[AND1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %3:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %1:_(s8) = G_TRUNC %4(s64) + %5:_(s64) = COPY $x12 + %2:_(s8) = G_TRUNC %5(s64) + %6:_(s8) = G_FSHL %0, %1, %2(s8) + %7:_(s64) = G_ANYEXT %6(s8) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: fshl_i16 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshl_i16 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C2]](s64) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[AND1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %3:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %1:_(s16) = G_TRUNC %4(s64) + %5:_(s64) = COPY $x12 + %2:_(s16) = G_TRUNC %5(s64) + %6:_(s16) = G_FSHL %0, %1, %2(s16) + %7:_(s64) = G_ANYEXT %6(s16) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: fshl_i32 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshl_i32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C2]](s64) + ; CHECK-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[LSHR]], [[AND1]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SLLW]], [[SRLW]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %3:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %4(s64) + %5:_(s64) = COPY $x12 + %2:_(s32) = G_TRUNC %5(s64) + %6:_(s32) = G_FSHL %0, %1, %2(s32) + %7:_(s64) = G_ANYEXT %6(s32) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: fshl_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshl_i64 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s64) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[AND1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + %3:_(s64) = G_FSHL %0, %1, %2(s64) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: fshr_i8 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshr_i8 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[AND1]](s64) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL1]], [[LSHR]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %3:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %1:_(s8) = G_TRUNC %4(s64) + %5:_(s64) = COPY $x12 + %2:_(s8) = G_TRUNC %5(s64) + %6:_(s8) = G_FSHR %0, %1, %2(s8) + %7:_(s64) = G_ANYEXT %6(s8) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: fshr_i16 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshr_i16 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[AND1]](s64) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL1]], [[LSHR]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %3:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %1:_(s16) = G_TRUNC %4(s64) + %5:_(s64) = COPY $x12 + %2:_(s16) = G_TRUNC %5(s64) + %6:_(s16) = G_FSHR %0, %1, %2(s16) + %7:_(s64) = G_ANYEXT %6(s16) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: fshr_i32 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshr_i32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[SHL]], [[AND1]] + ; CHECK-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY1]], [[AND]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SLLW]], [[SRLW]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %3:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %4(s64) + %5:_(s64) = COPY $x12 + %2:_(s32) = G_TRUNC %5(s64) + %6:_(s32) = G_FSHR %0, %1, %2(s32) + %7:_(s64) = G_ANYEXT %6(s32) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: fshr_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: fshr_i64 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[AND1]](s64) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[AND]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL1]], [[LSHR]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + %3:_(s64) = G_FSHR %0, %1, %2(s64) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-global-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-global-rv32.mir new file mode 100644 index 0000000..8e7daa6 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-global-rv32.mir @@ -0,0 +1,33 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s + +--- | + @var = global i32 0 + + define ptr @test_global() { + ret ptr @var + } + +... +--- +name: test_global +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1 (%ir-block.0): + ; CHECK-LABEL: name: test_global + ; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var + ; CHECK-NEXT: $x10 = COPY [[GV]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = G_GLOBAL_VALUE @var + $x10 = COPY %0(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-global-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-global-rv64.mir new file mode 100644 index 0000000..9e50121 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-global-rv64.mir @@ -0,0 +1,33 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s + +--- | + @var = global i32 0 + + define ptr @test_global() { + ret ptr @var + } + +... +--- +name: test_global +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1 (%ir-block.0): + ; CHECK-LABEL: name: test_global + ; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var + ; CHECK-NEXT: $x10 = COPY [[GV]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = G_GLOBAL_VALUE @var + $x10 = COPY %0(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir new file mode 100644 index 0000000..e93f82a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir @@ -0,0 +1,1585 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: cmp_sgt_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(sgt), %2(s7), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(sgt), %2(s8), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(sgt), %2(s16), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s1) = G_ICMP intpred(sgt), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i48 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xlo, [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y0:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s1) = G_ICMP intpred(sgt), %x(s48), %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i64 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), %xlo(s32), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %z:_(s1) = G_ICMP intpred(sgt), %x, %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(slt), %2(s7), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(slt), %2(s8), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(slt), %2(s16), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s1) = G_ICMP intpred(slt), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i48 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xlo, [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xhi(s32), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y0:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s1) = G_ICMP intpred(slt), %x(s48), %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i64 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xhi(s32), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), %xlo(s32), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %z:_(s1) = G_ICMP intpred(slt), %x, %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(sge), %2(s7), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(sge), %2(s8), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(sge), %2(s16), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s1) = G_ICMP intpred(sge), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i48 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xlo, [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y0:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s1) = G_ICMP intpred(sge), %x(s48), %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i64 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), %xlo(s32), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %z:_(s1) = G_ICMP intpred(sge), %x, %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(sle), %2(s7), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(sle), %2(s8), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(sle), %2(s16), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s1) = G_ICMP intpred(sle), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i48 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xlo, [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y0:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s1) = G_ICMP intpred(sle), %x(s48), %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i64 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), %xlo(s32), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %z:_(s1) = G_ICMP intpred(sle), %x, %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(ugt), %2(s7), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(ugt), %2(s8), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(ugt), %2(s16), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s1) = G_ICMP intpred(ugt), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i48 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %xhi, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xlo, [[C1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %yhi, [[C]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %ylo, [[C1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[AND2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND1]](s32), [[AND3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y0:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s1) = G_ICMP intpred(ugt), %x(s48), %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i64 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xlo(s32), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %z:_(s1) = G_ICMP intpred(ugt), %x, %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(ult), %2(s7), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(ult), %2(s8), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(ult), %2(s16), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s1) = G_ICMP intpred(ult), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i48 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %xhi, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xlo, [[C1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %yhi, [[C]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %ylo, [[C1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[AND3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y0:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s1) = G_ICMP intpred(ult), %x(s48), %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i64 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), %xlo(s32), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %z:_(s1) = G_ICMP intpred(sge), %x, %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(uge), %2(s7), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(uge), %2(s8), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(uge), %2(s16), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s1) = G_ICMP intpred(uge), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i48 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %xhi, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xlo, [[C1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %yhi, [[C]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %ylo, [[C1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[AND]](s32), [[AND2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[AND1]](s32), [[AND3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y0:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s1) = G_ICMP intpred(uge), %x(s48), %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i64 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xlo(s32), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %z:_(s1) = G_ICMP intpred(uge), %x, %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(ule), %2(s7), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(ule), %2(s8), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(ule), %2(s16), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s1) = G_ICMP intpred(ule), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i48 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %xhi, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xlo, [[C1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %yhi, [[C]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %ylo, [[C1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[AND]](s32), [[AND2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[AND1]](s32), [[AND3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y0:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s1) = G_ICMP intpred(ule), %x(s48), %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i64 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xlo(s32), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %z:_(s1) = G_ICMP intpred(ule), %x, %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(eq), %2(s7), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(eq), %2(s8), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(eq), %2(s16), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s1) = G_ICMP intpred(eq), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i48 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %xhi, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xlo, [[C1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %yhi, [[C]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %ylo, [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[AND]], [[AND2]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[AND1]], [[AND3]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C2]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y0:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s1) = G_ICMP intpred(eq), %x(s48), %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i64 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR %xhi, %yhi + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR %xlo, %ylo + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %z:_(s1) = G_ICMP intpred(eq), %x, %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(ne), %2(s7), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(ne), %2(s8), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s1) = G_ICMP intpred(ne), %2(s16), %3 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s1) = G_ICMP intpred(ne), %0(s32), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i48 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %xhi, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xlo, [[C1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %yhi, [[C]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %ylo, [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[AND]], [[AND2]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[AND1]], [[AND3]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s32), [[C2]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y0:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s1) = G_ICMP intpred(ne), %x(s48), %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i64 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR %xhi, %yhi + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR %xlo, %ylo + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s32), [[C]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %x:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %z:_(s1) = G_ICMP intpred(ne), %x, %y + %z0:_(s32) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_ptr +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_ptr + ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + %2:_(s1) = G_ICMP intpred(eq), %0(p0), %1 + %3:_(s32) = G_ANYEXT %2(s1) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i128 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: cmp_slt_i128 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 8) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s32) + ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32) from unknown-address + 8, align 8) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from unknown-address + 12) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s32), align 8) + ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p0) :: (load (s32) from unknown-address + 4) + ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s32) + ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p0) :: (load (s32) from unknown-address + 8, align 8) + ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s32) + ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s32) from unknown-address + 12) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD]](s32), [[LOAD4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD1]](s32), [[LOAD5]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD1]](s32), [[LOAD5]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD2]](s32), [[LOAD6]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD2]](s32), [[LOAD6]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[SELECT]], [[ICMP3]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[LOAD3]](s32), [[LOAD7]] + ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD3]](s32), [[LOAD7]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[SELECT1]], [[ICMP5]] + ; CHECK-NEXT: $x10 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(p0) = COPY $x10 + %0:_(s128) = G_LOAD %2(p0) :: (load (s128), align 8) + %3:_(p0) = COPY $x11 + %1:_(s128) = G_LOAD %3(p0) :: (load (s128), align 8) + %4:_(s1) = G_ICMP intpred(slt), %0(s128), %1 + %5:_(s32) = G_ANYEXT %4(s1) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv64.mir new file mode 100644 index 0000000..d7b9a4a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv64.mir @@ -0,0 +1,1803 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: cmp_sgt_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(sgt), %2(s8), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(sgt), %2(s15), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(sgt), %2(s16), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(sgt), %2(s32), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_ICMP intpred(sgt), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i72 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %xlo, [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %ylo, [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y0:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s1) = G_ICMP intpred(sgt), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sgt_i128 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), %xlo(s64), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %z:_(s1) = G_ICMP intpred(sgt), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(slt), %2(s8), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(slt), %2(s15), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(slt), %2(s16), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(slt), %2(s32), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_ICMP intpred(slt), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i72 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %xlo, [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %ylo, [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y0:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s1) = G_ICMP intpred(sge), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_slt_i128 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %xhi(s64), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), %xlo(s64), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %z:_(s1) = G_ICMP intpred(slt), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(sge), %2(s8), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(sge), %2(s15), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(sge), %2(s16), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(sge), %2(s32), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_ICMP intpred(sge), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i72 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %xlo, [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %ylo, [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y0:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s1) = G_ICMP intpred(sge), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sge_i128 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), %xlo(s64), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %z:_(s1) = G_ICMP intpred(sge), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(sle), %2(s8), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(sle), %2(s15), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(sle), %2(s16), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(sle), %2(s32), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_ICMP intpred(sle), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i72 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %xlo, [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %ylo, [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y0:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s1) = G_ICMP intpred(sle), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_sle_i128 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), %xlo(s64), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %z:_(s1) = G_ICMP intpred(sle), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ugt), %2(s8), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ugt), %2(s15), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ugt), %2(s16), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ugt), %2(s32), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_ICMP intpred(ugt), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i72 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %xhi, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xlo, [[C1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %yhi, [[C]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %ylo, [[C1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND]](s64), [[AND2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND1]](s64), [[AND3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y0:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s1) = G_ICMP intpred(ugt), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ugt_i128 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xlo(s64), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %z:_(s1) = G_ICMP intpred(ugt), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ult), %2(s8), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ult), %2(s15), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ult), %2(s16), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ult), %2(s32), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_ICMP intpred(ult), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i72 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %xhi, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xlo, [[C1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %yhi, [[C]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %ylo, [[C1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND1]](s64), [[AND3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y0:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s1) = G_ICMP intpred(ult), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ult_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ult_i128 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), %xlo(s64), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %z:_(s1) = G_ICMP intpred(sge), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(uge), %2(s8), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(uge), %2(s15), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(uge), %2(s16), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(uge), %2(s32), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_ICMP intpred(uge), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i72 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %xhi, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xlo, [[C1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %yhi, [[C]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %ylo, [[C1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[AND]](s64), [[AND2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[AND1]](s64), [[AND3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y0:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s1) = G_ICMP intpred(uge), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_uge_i128 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xlo(s64), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %z:_(s1) = G_ICMP intpred(uge), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ule), %2(s8), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ule), %2(s15), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ule), %2(s16), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ule), %2(s32), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_ICMP intpred(ule), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i72 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %xhi, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xlo, [[C1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %yhi, [[C]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %ylo, [[C1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[AND]](s64), [[AND2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[AND1]](s64), [[AND3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y0:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s1) = G_ICMP intpred(ule), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ule_i128 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xlo(s64), %ylo + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: %z0:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY %z0(s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %z:_(s1) = G_ICMP intpred(ule), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(eq), %2(s8), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(eq), %2(s15), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(eq), %2(s16), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(eq), %2(s32), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_ICMP intpred(eq), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i72 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %xhi, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xlo, [[C1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %yhi, [[C]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %ylo, [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[OR]](s64), [[C2]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y0:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s1) = G_ICMP intpred(eq), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_eq_i128 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR %xhi, %yhi + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR %xlo, %ylo + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[OR]](s64), [[C]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %z:_(s1) = G_ICMP intpred(eq), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ne), %2(s8), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ne), %2(s15), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ne), %2(s16), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s1) = G_ICMP intpred(ne), %2(s32), %3 + %5:_(s64) = G_ANYEXT %4(s1) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s1) = G_ICMP intpred(ne), %0(s64), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i72 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %xhi, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xlo, [[C1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %yhi, [[C]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %ylo, [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[OR]](s64), [[C2]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y0:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s1) = G_ICMP intpred(ne), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_i128 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR %xhi, %yhi + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR %xlo, %ylo + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[OR]](s64), [[C]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %x:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %z:_(s1) = G_ICMP intpred(ne), %x, %y + %z0:_(s64) = G_ANYEXT %z(s1) + $x10 = COPY %z0(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_ptr +body: | + bb.0.entry: + ; CHECK-LABEL: name: cmp_ne_ptr + ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY]](p0), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + %2:_(s1) = G_ICMP intpred(ne), %0(p0), %1 + %3:_(s64) = G_ANYEXT %2(s1) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-implicit-def-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-implicit-def-rv32.mir new file mode 100644 index 0000000..b6a7bff --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-implicit-def-rv32.mir @@ -0,0 +1,109 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: implicit_def_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i7 + ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s7) = G_IMPLICIT_DEF + %1:_(s32) = G_ANYEXT %0(s7) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: implicit_def_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i8 + ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s8) = G_IMPLICIT_DEF + %1:_(s32) = G_ANYEXT %0(s8) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: implicit_def_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i16 + ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = G_IMPLICIT_DEF + %1:_(s32) = G_ANYEXT %0(s16) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: implicit_def_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i32 + ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_IMPLICIT_DEF + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: implicit_def_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i48 + ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s32) + ; CHECK-NEXT: $x11 = COPY [[DEF]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s48) = G_IMPLICIT_DEF + %1:_(s64) = G_ANYEXT %0(s48) + %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) + $x10 = COPY %2(s32) + $x11 = COPY %3(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: implicit_def_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i64 + ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s32) + ; CHECK-NEXT: $x11 = COPY [[DEF]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = G_IMPLICIT_DEF + %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64) + $x10 = COPY %1(s32) + $x11 = COPY %2(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: implicit_def_i96 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i96 + ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s32) + ; CHECK-NEXT: $x11 = COPY [[DEF]](s32) + ; CHECK-NEXT: $x12 = COPY [[DEF]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %0:_(s96) = G_IMPLICIT_DEF + %1:_(s32), %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %0(s96) + $x10 = COPY %1(s32) + $x11 = COPY %2(s32) + $x12 = COPY %3(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-implicit-def-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-implicit-def-rv64.mir new file mode 100644 index 0000000..c024033 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-implicit-def-rv64.mir @@ -0,0 +1,123 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: implicit_def_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i8 + ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s8) = G_IMPLICIT_DEF + %1:_(s64) = G_ANYEXT %0(s8) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: implicit_def_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i15 + ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s15) = G_IMPLICIT_DEF + %1:_(s64) = G_ANYEXT %0(s15) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: implicit_def_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i16 + ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = G_IMPLICIT_DEF + %1:_(s64) = G_ANYEXT %0(s16) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: implicit_def_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i32 + ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_IMPLICIT_DEF + %1:_(s64) = G_ANYEXT %0(s32) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: implicit_def_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i64 + ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_IMPLICIT_DEF + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: implicit_def_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i72 + ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s64) + ; CHECK-NEXT: $x11 = COPY [[DEF]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s72) = G_IMPLICIT_DEF + %1:_(s128) = G_ANYEXT %0(s72) + %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %1(s128) + $x10 = COPY %2(s64) + $x11 = COPY %3(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: implicit_def_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i128 + ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s64) + ; CHECK-NEXT: $x11 = COPY [[DEF]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s128) = G_IMPLICIT_DEF + %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(s128) + $x10 = COPY %1(s64) + $x11 = COPY %2(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: implicit_def_i192 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_def_i192 + ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]](s64) + ; CHECK-NEXT: $x11 = COPY [[DEF]](s64) + ; CHECK-NEXT: $x12 = COPY [[DEF]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %0:_(s192) = G_IMPLICIT_DEF + %1:_(s64), %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %0(s192) + $x10 = COPY %1(s64) + $x11 = COPY %2(s64) + $x12 = COPY %3(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-inttoptr-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-inttoptr-rv32.mir new file mode 100644 index 0000000..074c5c2 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-inttoptr-rv32.mir @@ -0,0 +1,131 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: p0_s32 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(p0) = G_INTTOPTR %0(s32) + $x10 = COPY %1(p0) + PseudoRET implicit $x10 + +... +--- +name: p0_s16 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(p0) = G_INTTOPTR %0(s16) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... +--- +name: p0_s8 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(p0) = G_INTTOPTR %0(s8) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... +--- +name: p0_s1 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s32) + %2:_(p0) = G_INTTOPTR %0(s1) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... +--- +name: p0_s64 +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: p0_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %3:_(p0) = G_INTTOPTR %0(s64) + $x10 = COPY %3(p0) + PseudoRET implicit $x10 + +... +--- +name: p0_s44 +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: p0_s44 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %3:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %0:_(s44) = G_TRUNC %3(s64) + %4:_(p0) = G_INTTOPTR %0(s44) + $x10 = COPY %4(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-inttoptr-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-inttoptr-rv64.mir new file mode 100644 index 0000000..cff8d36 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-inttoptr-rv64.mir @@ -0,0 +1,153 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: p0_s64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(p0) = G_INTTOPTR %0(s64) + $x10 = COPY %1(p0) + PseudoRET implicit $x10 + +... +--- +name: p0_s32 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(p0) = G_INTTOPTR %0(s32) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... +--- +name: p0_s16 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(p0) = G_INTTOPTR %0(s16) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... +--- +name: p0_s8 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(p0) = G_INTTOPTR %0(s8) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... +--- +name: p0_s1 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s64) + %2:_(p0) = G_INTTOPTR %0(s1) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... +--- +name: p0_s128 +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: p0_s128 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = COPY $x11 + %0:_(s128) = G_MERGE_VALUES %1(s64), %2(s64) + %3:_(p0) = G_INTTOPTR %0(s128) + $x10 = COPY %3(p0) + PseudoRET implicit $x10 + +... +--- +name: p0_s88 +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: p0_s88 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %2:_(s64) = COPY $x11 + %3:_(s128) = G_MERGE_VALUES %1(s64), %2(s64) + %0:_(s88) = G_TRUNC %3(s128) + %4:_(p0) = G_INTTOPTR %0(s88) + $x10 = COPY %4(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-f16-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-f16-rv32.mir new file mode 100644 index 0000000..1cbbaf0 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-f16-rv32.mir @@ -0,0 +1,28 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: is_fpclass_f16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: is_fpclass_f16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 152 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:_(s32) = G_FCLASS [[COPY]](s16) + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCLASS]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[AND]](s32), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s1) = G_IS_FPCLASS %0(s16), 608 + %2:_(s32) = G_ANYEXT %1(s1) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-f16-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-f16-rv64.mir new file mode 100644 index 0000000..ad02f5b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-f16-rv64.mir @@ -0,0 +1,28 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: is_fpclass_f16 +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: is_fpclass_f16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 152 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:_(s64) = G_FCLASS [[COPY]](s16) + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[FCLASS]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[AND]](s64), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s1) = G_IS_FPCLASS %0(s16), 608 + %2:_(s64) = G_ANYEXT %1(s1) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-rv32.mir new file mode 100644 index 0000000..fb8c5c3 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-rv32.mir @@ -0,0 +1,52 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: is_fpclass_f32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: is_fpclass_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 152 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:_(s32) = G_FCLASS [[COPY]](s32) + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCLASS]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[AND]](s32), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s1) = G_IS_FPCLASS %0(s32), 608 + %2:_(s32) = G_ANYEXT %1(s1) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: is_fpclass_f64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: is_fpclass_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 152 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:_(s32) = G_FCLASS [[COPY]](s64) + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCLASS]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[AND]](s32), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s1) = G_IS_FPCLASS %0(s64), 608 + %2:_(s32) = G_ANYEXT %1(s1) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-rv64.mir new file mode 100644 index 0000000..735398b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-rv64.mir @@ -0,0 +1,52 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: is_fpclass_f32 +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: is_fpclass_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 152 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:_(s64) = G_FCLASS [[COPY]](s32) + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[FCLASS]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[AND]](s64), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s1) = G_IS_FPCLASS %0(s32), 608 + %2:_(s64) = G_ANYEXT %1(s1) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: is_fpclass_f64 +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: is_fpclass_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 152 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:_(s64) = G_FCLASS [[COPY]](s64) + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[FCLASS]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[AND]](s64), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s1) = G_IS_FPCLASS %0(s64), 608 + %2:_(s64) = G_ANYEXT %1(s1) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv32.mir new file mode 100644 index 0000000..f68902c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv32.mir @@ -0,0 +1,185 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: sitofp_s16_s1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s16_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32) + ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s32) + %2:_(s16) = G_SITOFP %0(s1) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s16_s1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s16_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32) + ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s32) + %2:_(s16) = G_UITOFP %0(s1) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: sitofp_s16_s8 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s16_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32) + ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s16) = G_SITOFP %0(s8) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s16_s8 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s16_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32) + ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s16) = G_UITOFP %0(s8) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: sitofp_s16_s16 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s16_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32) + ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s16) = G_SITOFP %0(s16) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s16_s16 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s16_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32) + ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s16) = G_UITOFP %0(s16) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: sitofp_s16_s32 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s16_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[COPY]](s32) + ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s32) = COPY $x10 + %1:_(s16) = G_SITOFP %0(s32) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s16_s32 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s16_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[COPY]](s32) + ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s32) = COPY $x10 + %1:_(s16) = G_UITOFP %0(s32) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir new file mode 100644 index 0000000..6a70a33 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir @@ -0,0 +1,230 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: sitofp_s16_s1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s16_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s64) + ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s64) + %2:_(s16) = G_SITOFP %0(s1) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s16_s1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s16_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s64) + ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s64) + %2:_(s16) = G_UITOFP %0(s1) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: sitofp_s16_s8 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s16_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s64) + ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s16) = G_SITOFP %0(s8) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s16_s8 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s16_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s64) + ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s16) = G_UITOFP %0(s8) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: sitofp_s16_s16 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s16_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s64) + ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s16) = G_SITOFP %0(s16) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s16_s16 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s16_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s64) + ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s16) = G_UITOFP %0(s16) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: sitofp_s16_s32 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s16_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[SEXT_INREG]](s64) + ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s16) = G_SITOFP %0(s32) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s16_s32 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s16_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s64) + ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s16) = G_UITOFP %0(s32) + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: sitofp_s16_s64 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s16_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[COPY]](s64) + ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s64) = COPY $x10 + %1:_(s16) = G_SITOFP %0(s64) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s16_s64 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s16_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[COPY]](s64) + ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s64) = COPY $x10 + %1:_(s16) = G_UITOFP %0(s64) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv32.mir new file mode 100644 index 0000000..6142965 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv32.mir @@ -0,0 +1,366 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: sitofp_s32_s1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32) + ; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s32) + %2:_(s32) = G_SITOFP %0(s1) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32) + ; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s32) + %2:_(s32) = G_UITOFP %0(s1) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s32_s8 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32) + ; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s32) = G_SITOFP %0(s8) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s8 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32) + ; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s32) = G_UITOFP %0(s8) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s32_s16 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32) + ; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s32) = G_SITOFP %0(s16) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s16 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32) + ; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s32) = G_UITOFP %0(s16) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s32_s32 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32) + ; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $x10 + %1:_(s32) = G_SITOFP %0(s32) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s32 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s32) + ; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $x10 + %1:_(s32) = G_UITOFP %0(s32) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s64_s1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32) + ; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s32) + %2:_(s64) = G_SITOFP %0(s1) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32) + ; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s32) + %2:_(s64) = G_UITOFP %0(s1) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: sitofp_s64_s8 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32) + ; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s64) = G_SITOFP %0(s8) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s8 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32) + ; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s64) = G_UITOFP %0(s8) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: sitofp_s64_s16 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32) + ; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s64) = G_SITOFP %0(s16) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s16 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32) + ; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s64) = G_UITOFP %0(s16) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: sitofp_s64_s32 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32) + ; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s32) = COPY $x10 + %1:_(s64) = G_SITOFP %0(s32) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s32 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s32) + ; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s32) = COPY $x10 + %1:_(s64) = G_UITOFP %0(s32) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir new file mode 100644 index 0000000..2d6ee62 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir @@ -0,0 +1,456 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: sitofp_s32_s1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s64) + ; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s64) + %2:_(s32) = G_SITOFP %0(s1) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s64) + ; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s64) + %2:_(s32) = G_UITOFP %0(s1) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s32_s8 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s64) + ; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s32) = G_SITOFP %0(s8) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s8 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s64) + ; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s32) = G_UITOFP %0(s8) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s32_s16 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s64) + ; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s32) = G_SITOFP %0(s16) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s16 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s64) + ; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s32) = G_UITOFP %0(s16) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s32_s32 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s64) + ; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s32) = G_SITOFP %0(s32) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s32 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s64) + ; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s32) = G_UITOFP %0(s32) + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s32_s64 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s64) + ; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s64) = COPY $x10 + %1:_(s32) = G_SITOFP %0(s64) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s64 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s64) + ; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s64) = COPY $x10 + %1:_(s32) = G_UITOFP %0(s64) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s64_s1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s64) + ; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s64) + %2:_(s64) = G_SITOFP %0(s1) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s64) + ; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s64) + %2:_(s64) = G_UITOFP %0(s1) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: sitofp_s64_s8 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s64) + ; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s64) = G_SITOFP %0(s8) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s8 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s64) + ; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %2:_(s64) = G_UITOFP %0(s8) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: sitofp_s64_s16 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s64) + ; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s64) = G_SITOFP %0(s16) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s16 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s64) + ; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %2:_(s64) = G_UITOFP %0(s16) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: sitofp_s64_s32 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s64) + ; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s64) = G_SITOFP %0(s32) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s32 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s64) + ; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %2:_(s64) = G_UITOFP %0(s32) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: sitofp_s64_s64 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s64) + ; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $x10 + %1:_(s64) = G_SITOFP %0(s64) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s64 +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s64) + ; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $x10 + %1:_(s64) = G_UITOFP %0(s64) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-medium-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-medium-rv64.mir new file mode 100644 index 0000000..4b1cb14 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-medium-rv64.mir @@ -0,0 +1,162 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: -code-model=medium | FileCheck %s + +--- | + define i32 @jt_test(i32 signext %in) { + entry: + %0 = sext i32 %in to i64 + switch i64 %0, label %default [ + i64 1, label %bb1 + i64 2, label %bb2 + i64 3, label %bb3 + i64 4, label %bb4 + i64 5, label %bb5 + i64 6, label %bb6 + ] + + bb1: + ret i32 4 + + bb2: + ret i32 3 + + bb3: + ret i32 2 + + bb4: + ret i32 1 + + bb5: + ret i32 100 + + bb6: + ret i32 200 + + default: + ret i32 1000 + } + +... +--- +name: jt_test +tracksRegLiveness: true +jumpTable: + kind: block-address + entries: + - id: 0 + blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ] +body: | + ; CHECK-LABEL: name: jt_test + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT]], [[C1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SUB]](s64), [[C]] + ; CHECK-NEXT: G_BRCOND [[ICMP]](s64), %bb.8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.entry: + ; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SUB]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[SHL]](s64) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from jump-table) + ; CHECK-NEXT: G_BRINDIRECT [[LOAD]](p0) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.bb1: + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: $x10 = COPY [[C3]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.bb2: + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: $x10 = COPY [[C4]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.bb3: + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: $x10 = COPY [[C5]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.bb4: + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: $x10 = COPY [[C6]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6.bb5: + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 100 + ; CHECK-NEXT: $x10 = COPY [[C7]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.7.bb6: + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 200 + ; CHECK-NEXT: $x10 = COPY [[C8]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.8.default: + ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 1000 + ; CHECK-NEXT: $x10 = COPY [[C9]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + successors: %bb.8, %bb.9 + liveins: $x10 + + %1:_(s64) = COPY $x10 + %2:_(s64) = G_ASSERT_SEXT %1, 32 + %0:_(s32) = G_TRUNC %2(s64) + %7:_(s64) = G_CONSTANT i64 5 + %3:_(s64) = G_SEXT %0(s32) + %4:_(s64) = G_CONSTANT i64 1 + %5:_(s64) = G_SUB %3, %4 + %9:_(s1) = G_ICMP intpred(ugt), %5(s64), %7 + G_BRCOND %9(s1), %bb.8 + + bb.9.entry: + successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7 + + %10:_(p0) = G_JUMP_TABLE %jump-table.0 + G_BRJT %10(p0), %jump-table.0, %5(s64) + + bb.2.bb1: + %22:_(s64) = G_CONSTANT i64 4 + $x10 = COPY %22(s64) + PseudoRET implicit $x10 + + bb.3.bb2: + %20:_(s64) = G_CONSTANT i64 3 + $x10 = COPY %20(s64) + PseudoRET implicit $x10 + + bb.4.bb3: + %18:_(s64) = G_CONSTANT i64 2 + $x10 = COPY %18(s64) + PseudoRET implicit $x10 + + bb.5.bb4: + %16:_(s64) = G_CONSTANT i64 1 + $x10 = COPY %16(s64) + PseudoRET implicit $x10 + + bb.6.bb5: + %14:_(s64) = G_CONSTANT i64 100 + $x10 = COPY %14(s64) + PseudoRET implicit $x10 + + bb.7.bb6: + %12:_(s64) = G_CONSTANT i64 200 + $x10 = COPY %12(s64) + PseudoRET implicit $x10 + + bb.8.default: + %24:_(s64) = G_CONSTANT i64 1000 + $x10 = COPY %24(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv32.mir new file mode 100644 index 0000000..d48d218 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv32.mir @@ -0,0 +1,158 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: -relocation-model=pic | FileCheck %s + +--- | + define i32 @jt_test(i32 signext %in) { + entry: + switch i32 %in, label %default [ + i32 1, label %bb1 + i32 2, label %bb2 + i32 3, label %bb3 + i32 4, label %bb4 + i32 5, label %bb5 + i32 6, label %bb6 + ] + + bb1: ; preds = %entry + ret i32 4 + + bb2: ; preds = %entry + ret i32 3 + + bb3: ; preds = %entry + ret i32 2 + + bb4: ; preds = %entry + ret i32 1 + + bb5: ; preds = %entry + ret i32 100 + + bb6: ; preds = %entry + ret i32 200 + + default: ; preds = %entry + ret i32 1000 + } + +... +--- +name: jt_test +tracksRegLiveness: true +jumpTable: + kind: label-difference32 + entries: + - id: 0 + blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ] +body: | + ; CHECK-LABEL: name: jt_test + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 200 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 100 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000 + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C8]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD]](s32), [[C]] + ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.entry: + ; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0 + ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C9]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[SHL]](s32) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from jump-table) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[LOAD]](s32) + ; CHECK-NEXT: G_BRINDIRECT [[PTR_ADD1]](p0) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.bb1: + ; CHECK-NEXT: $x10 = COPY [[C6]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.bb2: + ; CHECK-NEXT: $x10 = COPY [[C5]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.bb3: + ; CHECK-NEXT: $x10 = COPY [[C4]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.bb4: + ; CHECK-NEXT: $x10 = COPY [[C3]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6.bb5: + ; CHECK-NEXT: $x10 = COPY [[C2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.7.bb6: + ; CHECK-NEXT: $x10 = COPY [[C1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.8.default: + ; CHECK-NEXT: $x10 = COPY [[C7]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + successors: %bb.8, %bb.9 + liveins: $x10 + + %0:_(s32) = COPY $x10 + %4:_(s32) = G_CONSTANT i32 5 + %8:_(s32) = G_CONSTANT i32 200 + %9:_(s32) = G_CONSTANT i32 100 + %10:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_CONSTANT i32 2 + %12:_(s32) = G_CONSTANT i32 3 + %13:_(s32) = G_CONSTANT i32 4 + %14:_(s32) = G_CONSTANT i32 1000 + %1:_(s32) = G_CONSTANT i32 -1 + %2:_(s32) = G_ADD %0, %1 + %6:_(s1) = G_ICMP intpred(ugt), %2(s32), %4 + G_BRCOND %6(s1), %bb.8 + + bb.9.entry: + successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7 + + %7:_(p0) = G_JUMP_TABLE %jump-table.0 + G_BRJT %7(p0), %jump-table.0, %2(s32) + + bb.2.bb1: + $x10 = COPY %13(s32) + PseudoRET implicit $x10 + + bb.3.bb2: + $x10 = COPY %12(s32) + PseudoRET implicit $x10 + + bb.4.bb3: + $x10 = COPY %11(s32) + PseudoRET implicit $x10 + + bb.5.bb4: + $x10 = COPY %10(s32) + PseudoRET implicit $x10 + + bb.6.bb5: + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + + bb.7.bb6: + $x10 = COPY %8(s32) + PseudoRET implicit $x10 + + bb.8.default: + $x10 = COPY %14(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv64.mir new file mode 100644 index 0000000..0b5357a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-pic-rv64.mir @@ -0,0 +1,163 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: -relocation-model=pic | FileCheck %s + +--- | + define i32 @jt_test(i32 signext %in) { + entry: + %0 = sext i32 %in to i64 + switch i64 %0, label %default [ + i64 1, label %bb1 + i64 2, label %bb2 + i64 3, label %bb3 + i64 4, label %bb4 + i64 5, label %bb5 + i64 6, label %bb6 + ] + + bb1: + ret i32 4 + + bb2: + ret i32 3 + + bb3: + ret i32 2 + + bb4: + ret i32 1 + + bb5: + ret i32 100 + + bb6: + ret i32 200 + + default: + ret i32 1000 + } + +... +--- +name: jt_test +tracksRegLiveness: true +jumpTable: + kind: label-difference32 + entries: + - id: 0 + blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ] +body: | + ; CHECK-LABEL: name: jt_test + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT]], [[C1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SUB]](s64), [[C]] + ; CHECK-NEXT: G_BRCOND [[ICMP]](s64), %bb.8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.entry: + ; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SUB]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[SHL]](s64) + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[PTR_ADD]](p0) :: (load (s32) from jump-table) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[SEXTLOAD]](s64) + ; CHECK-NEXT: G_BRINDIRECT [[PTR_ADD1]](p0) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.bb1: + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: $x10 = COPY [[C3]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.bb2: + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: $x10 = COPY [[C4]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.bb3: + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: $x10 = COPY [[C5]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.bb4: + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: $x10 = COPY [[C6]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6.bb5: + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 100 + ; CHECK-NEXT: $x10 = COPY [[C7]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.7.bb6: + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 200 + ; CHECK-NEXT: $x10 = COPY [[C8]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.8.default: + ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 1000 + ; CHECK-NEXT: $x10 = COPY [[C9]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + successors: %bb.8, %bb.9 + liveins: $x10 + + %1:_(s64) = COPY $x10 + %2:_(s64) = G_ASSERT_SEXT %1, 32 + %0:_(s32) = G_TRUNC %2(s64) + %7:_(s64) = G_CONSTANT i64 5 + %3:_(s64) = G_SEXT %0(s32) + %4:_(s64) = G_CONSTANT i64 1 + %5:_(s64) = G_SUB %3, %4 + %9:_(s1) = G_ICMP intpred(ugt), %5(s64), %7 + G_BRCOND %9(s1), %bb.8 + + bb.9.entry: + successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7 + + %10:_(p0) = G_JUMP_TABLE %jump-table.0 + G_BRJT %10(p0), %jump-table.0, %5(s64) + + bb.2.bb1: + %22:_(s64) = G_CONSTANT i64 4 + $x10 = COPY %22(s64) + PseudoRET implicit $x10 + + bb.3.bb2: + %20:_(s64) = G_CONSTANT i64 3 + $x10 = COPY %20(s64) + PseudoRET implicit $x10 + + bb.4.bb3: + %18:_(s64) = G_CONSTANT i64 2 + $x10 = COPY %18(s64) + PseudoRET implicit $x10 + + bb.5.bb4: + %16:_(s64) = G_CONSTANT i64 1 + $x10 = COPY %16(s64) + PseudoRET implicit $x10 + + bb.6.bb5: + %14:_(s64) = G_CONSTANT i64 100 + $x10 = COPY %14(s64) + PseudoRET implicit $x10 + + bb.7.bb6: + %12:_(s64) = G_CONSTANT i64 200 + $x10 = COPY %12(s64) + PseudoRET implicit $x10 + + bb.8.default: + %24:_(s64) = G_CONSTANT i64 1000 + $x10 = COPY %24(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv32.mir new file mode 100644 index 0000000..97e2bad --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv32.mir @@ -0,0 +1,159 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: -code-model=small | FileCheck %s +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: -code-model=medium | FileCheck %s + +--- | + define i32 @jt_test(i32 signext %in) { + entry: + switch i32 %in, label %default [ + i32 1, label %bb1 + i32 2, label %bb2 + i32 3, label %bb3 + i32 4, label %bb4 + i32 5, label %bb5 + i32 6, label %bb6 + ] + + bb1: ; preds = %entry + ret i32 4 + + bb2: ; preds = %entry + ret i32 3 + + bb3: ; preds = %entry + ret i32 2 + + bb4: ; preds = %entry + ret i32 1 + + bb5: ; preds = %entry + ret i32 100 + + bb6: ; preds = %entry + ret i32 200 + + default: ; preds = %entry + ret i32 1000 + } + +... +--- +name: jt_test +tracksRegLiveness: true +jumpTable: + kind: block-address + entries: + - id: 0 + blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ] +body: | + ; CHECK-LABEL: name: jt_test + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 200 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 100 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000 + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C8]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[SUB]](s32), [[C]] + ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.entry: + ; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0 + ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C9]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[SHL]](s32) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from jump-table) + ; CHECK-NEXT: G_BRINDIRECT [[LOAD]](p0) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.bb1: + ; CHECK-NEXT: $x10 = COPY [[C6]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.bb2: + ; CHECK-NEXT: $x10 = COPY [[C5]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.bb3: + ; CHECK-NEXT: $x10 = COPY [[C4]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.bb4: + ; CHECK-NEXT: $x10 = COPY [[C3]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6.bb5: + ; CHECK-NEXT: $x10 = COPY [[C2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.7.bb6: + ; CHECK-NEXT: $x10 = COPY [[C1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.8.default: + ; CHECK-NEXT: $x10 = COPY [[C7]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + successors: %bb.8, %bb.9 + liveins: $x10 + + %0:_(s32) = COPY $x10 + %4:_(s32) = G_CONSTANT i32 5 + %8:_(s32) = G_CONSTANT i32 200 + %9:_(s32) = G_CONSTANT i32 100 + %10:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_CONSTANT i32 2 + %12:_(s32) = G_CONSTANT i32 3 + %13:_(s32) = G_CONSTANT i32 4 + %14:_(s32) = G_CONSTANT i32 1000 + %1:_(s32) = G_CONSTANT i32 1 + %2:_(s32) = G_SUB %0, %1 + %6:_(s1) = G_ICMP intpred(ugt), %2(s32), %4 + G_BRCOND %6(s1), %bb.8 + + bb.9.entry: + successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7 + + %7:_(p0) = G_JUMP_TABLE %jump-table.0 + G_BRJT %7(p0), %jump-table.0, %2(s32) + + bb.2.bb1: + $x10 = COPY %13(s32) + PseudoRET implicit $x10 + + bb.3.bb2: + $x10 = COPY %12(s32) + PseudoRET implicit $x10 + + bb.4.bb3: + $x10 = COPY %11(s32) + PseudoRET implicit $x10 + + bb.5.bb4: + $x10 = COPY %10(s32) + PseudoRET implicit $x10 + + bb.6.bb5: + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + + bb.7.bb6: + $x10 = COPY %8(s32) + PseudoRET implicit $x10 + + bb.8.default: + $x10 = COPY %14(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-small-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-small-rv64.mir new file mode 100644 index 0000000..f3b8310 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-small-rv64.mir @@ -0,0 +1,163 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: -code-model=small | FileCheck %s + +--- | + define i32 @jt_test(i32 signext %in) { + entry: + %0 = sext i32 %in to i64 + switch i64 %0, label %default [ + i64 1, label %bb1 + i64 2, label %bb2 + i64 3, label %bb3 + i64 4, label %bb4 + i64 5, label %bb5 + i64 6, label %bb6 + ] + + bb1: + ret i32 4 + + bb2: + ret i32 3 + + bb3: + ret i32 2 + + bb4: + ret i32 1 + + bb5: + ret i32 100 + + bb6: + ret i32 200 + + default: + ret i32 1000 + } + +... +--- +name: jt_test +tracksRegLiveness: true +jumpTable: + kind: custom32 + entries: + - id: 0 + blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ] +body: | + ; CHECK-LABEL: name: jt_test + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT]], [[C1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SUB]](s64), [[C]] + ; CHECK-NEXT: G_BRCOND [[ICMP]](s64), %bb.8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.entry: + ; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SUB]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[JUMP_TABLE]], [[SHL]](s64) + ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[PTR_ADD]](p0) :: (load (s32) from jump-table) + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SEXTLOAD]](s64) + ; CHECK-NEXT: G_BRINDIRECT [[INTTOPTR]](p0) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.bb1: + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: $x10 = COPY [[C3]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.bb2: + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: $x10 = COPY [[C4]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.bb3: + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: $x10 = COPY [[C5]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.bb4: + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: $x10 = COPY [[C6]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6.bb5: + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 100 + ; CHECK-NEXT: $x10 = COPY [[C7]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.7.bb6: + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 200 + ; CHECK-NEXT: $x10 = COPY [[C8]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.8.default: + ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 1000 + ; CHECK-NEXT: $x10 = COPY [[C9]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + successors: %bb.8, %bb.9 + liveins: $x10 + + %1:_(s64) = COPY $x10 + %2:_(s64) = G_ASSERT_SEXT %1, 32 + %0:_(s32) = G_TRUNC %2(s64) + %7:_(s64) = G_CONSTANT i64 5 + %3:_(s64) = G_SEXT %0(s32) + %4:_(s64) = G_CONSTANT i64 1 + %5:_(s64) = G_SUB %3, %4 + %9:_(s1) = G_ICMP intpred(ugt), %5(s64), %7 + G_BRCOND %9(s1), %bb.8 + + bb.9.entry: + successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7 + + %10:_(p0) = G_JUMP_TABLE %jump-table.0 + G_BRJT %10(p0), %jump-table.0, %5(s64) + + bb.2.bb1: + %22:_(s64) = G_CONSTANT i64 4 + $x10 = COPY %22(s64) + PseudoRET implicit $x10 + + bb.3.bb2: + %20:_(s64) = G_CONSTANT i64 3 + $x10 = COPY %20(s64) + PseudoRET implicit $x10 + + bb.4.bb3: + %18:_(s64) = G_CONSTANT i64 2 + $x10 = COPY %18(s64) + PseudoRET implicit $x10 + + bb.5.bb4: + %16:_(s64) = G_CONSTANT i64 1 + $x10 = COPY %16(s64) + PseudoRET implicit $x10 + + bb.6.bb5: + %14:_(s64) = G_CONSTANT i64 100 + $x10 = COPY %14(s64) + PseudoRET implicit $x10 + + bb.7.bb6: + %12:_(s64) = G_CONSTANT i64 200 + $x10 = COPY %12(s64) + PseudoRET implicit $x10 + + bb.8.default: + %24:_(s64) = G_CONSTANT i64 1000 + $x10 = COPY %24(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir new file mode 100644 index 0000000..9d2b6c1 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir @@ -0,0 +1,431 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=UNALIGNED + +--- +name: load_i8 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i8 + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s8)) + ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16) + ; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s32) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s8) = G_LOAD %0(p0) :: (load (s8)) + %2:_(s32) = G_ANYEXT %1(s8) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: load_i16 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i16 + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16)) + ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16) + ; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s32) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s16) = G_LOAD %0(p0) :: (load (s16)) + %2:_(s32) = G_ANYEXT %1(s16) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: load_i32 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32)) + ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i32 + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32)) + ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s32) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_LOAD %0(p0) :: (load (s32)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: load_i64 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 8) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4) + ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32) + ; CHECK-NEXT: $x11 = COPY [[LOAD1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; UNALIGNED-LABEL: name: load_i64 + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 8) + ; UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) + ; UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4) + ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s32) + ; UNALIGNED-NEXT: $x11 = COPY [[LOAD1]](s32) + ; UNALIGNED-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_LOAD %0(p0) :: (load (s64)) + %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) + $x10 = COPY %2(s32) + $x11 = COPY %3(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: load_ptr +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_ptr + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load (p0), align 8) + ; CHECK-NEXT: $x10 = COPY [[LOAD]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_ptr + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load (p0), align 8) + ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](p0) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(p0) = G_LOAD %0(p0) :: (load (p0), align 8) + $x10 = COPY %1(p0) + PseudoRET implicit $x10 + +... +--- +name: load_i16_unaligned +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i16_unaligned + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[C1]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i16_unaligned + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16), align 1) + ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16) + ; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s32) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s16) = G_LOAD %0(p0) :: (load (s16), align 1) + %2:_(s32) = G_ANYEXT %1(s16) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: load_i32_unaligned +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i32_unaligned + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD1]], [[C1]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s32) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD2]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]] + ; CHECK-NEXT: $x10 = COPY [[OR2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i32_unaligned + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 1) + ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s32) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_LOAD %0(p0) :: (load (s32), align 1) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: load_i32_align2 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i32_align2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i32_align2 + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 2) + ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s32) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_LOAD %0(p0) :: (load (s32), align 2) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: load_i64_unaligned +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i64_unaligned + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD1]], [[C1]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s32) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD2]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s32) + ; CHECK-NEXT: [[ZEXTLOAD3:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD3]](p0) :: (load (s8) from unknown-address + 4) + ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C]](s32) + ; CHECK-NEXT: [[ZEXTLOAD4:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD4]](p0) :: (load (s8) from unknown-address + 5) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD4]], [[C1]](s32) + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]] + ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C2]](s32) + ; CHECK-NEXT: [[ZEXTLOAD5:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6) + ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD5]], [[C]](s32) + ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7) + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LOAD1]], [[C1]](s32) + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[SHL4]], [[ZEXTLOAD5]] + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C3]](s32) + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]] + ; CHECK-NEXT: $x10 = COPY [[OR2]](s32) + ; CHECK-NEXT: $x11 = COPY [[OR5]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; UNALIGNED-LABEL: name: load_i64_unaligned + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 1) + ; UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) + ; UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4, align 1) + ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s32) + ; UNALIGNED-NEXT: $x11 = COPY [[LOAD1]](s32) + ; UNALIGNED-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_LOAD %0(p0) :: (load (s64), align 1) + %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) + $x10 = COPY %2(s32) + $x11 = COPY %3(s32) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir new file mode 100644 index 0000000..06e84fd --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir @@ -0,0 +1,637 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+unaligned-scalar-mem -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=UNALIGNED + +--- +name: load_i8 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i8 + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s8)) + ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16) + ; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s8) = G_LOAD %0(p0) :: (load (s8)) + %2:_(s64) = G_ANYEXT %1(s8) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i16 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i16 + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16)) + ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16) + ; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s16) = G_LOAD %0(p0) :: (load (s16)) + %2:_(s64) = G_ANYEXT %1(s16) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i32 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32)) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i32 + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32)) + ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32) + ; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_LOAD %0(p0) :: (load (s32)) + %2:_(s64) = G_ANYEXT %1(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i64 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64)) + ; CHECK-NEXT: $x10 = COPY [[LOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i64 + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64)) + ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s64) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_LOAD %0(p0) :: (load (s64)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i128 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i128 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from unknown-address + 8) + ; CHECK-NEXT: $x10 = COPY [[LOAD]](s64) + ; CHECK-NEXT: $x11 = COPY [[LOAD1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; UNALIGNED-LABEL: name: load_i128 + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64)) + ; UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) + ; UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from unknown-address + 8) + ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s64) + ; UNALIGNED-NEXT: $x11 = COPY [[LOAD1]](s64) + ; UNALIGNED-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(p0) = COPY $x10 + %1:_(s128) = G_LOAD %0(p0) :: (load (s128), align 8) + %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %1(s128) + $x10 = COPY %2(s64) + $x11 = COPY %3(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: load_ptr +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_ptr + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load (p0)) + ; CHECK-NEXT: $x10 = COPY [[LOAD]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_ptr + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load (p0)) + ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](p0) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(p0) = G_LOAD %0(p0) :: (load (p0)) + $x10 = COPY %1(p0) + PseudoRET implicit $x10 + +... +--- +name: load_i16_unaligned +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i16_unaligned + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i16_unaligned + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16), align 1) + ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16) + ; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s16) = G_LOAD %0(p0) :: (load (s16), align 1) + %2:_(s64) = G_ANYEXT %1(s16) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i32_unaligned +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i32_unaligned + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD1]], [[C1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s64) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C1]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ZEXTLOAD2]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C3]](s64) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[OR]] + ; CHECK-NEXT: $x10 = COPY [[OR2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i32_unaligned + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 1) + ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32) + ; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_LOAD %0(p0) :: (load (s32), align 1) + %2:_(s64) = G_ANYEXT %1(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i32_align2 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i32_align2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i32_align2 + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 2) + ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32) + ; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_LOAD %0(p0) :: (load (s32), align 2) + %2:_(s64) = G_ANYEXT %1(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i64_unaligned +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i64_unaligned + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD1]], [[C1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s64) + ; CHECK-NEXT: [[ZEXTLOAD3:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD3]], [[C1]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ZEXTLOAD2]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C3]](s64) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[OR]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64) + ; CHECK-NEXT: [[ZEXTLOAD4:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD3]](p0) :: (load (s8) from unknown-address + 4) + ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C]](s64) + ; CHECK-NEXT: [[ZEXTLOAD5:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD4]](p0) :: (load (s8) from unknown-address + 5) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD5]], [[C1]](s64) + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SHL3]], [[ZEXTLOAD4]] + ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C2]](s64) + ; CHECK-NEXT: [[ZEXTLOAD6:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6) + ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD5]], [[C]](s64) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7) + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[LOAD]], [[C1]](s64) + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[ZEXTLOAD6]] + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[OR4]], [[C3]](s64) + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL5]], [[OR3]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[OR5]], [[C5]](s64) + ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[OR2]] + ; CHECK-NEXT: $x10 = COPY [[OR6]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i64_unaligned + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64), align 1) + ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s64) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_LOAD %0(p0) :: (load (s64), align 1) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i64_align2 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i64_align2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD1]], [[C1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s16) from unknown-address + 4) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s64) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[LOAD]], [[C1]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ZEXTLOAD2]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C3]](s64) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[OR]] + ; CHECK-NEXT: $x10 = COPY [[OR2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + ; + ; UNALIGNED-LABEL: name: load_i64_align2 + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64), align 2) + ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s64) + ; UNALIGNED-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_LOAD %0(p0) :: (load (s64), align 2) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i128_unaligned +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: load_i128_unaligned + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD1]], [[C1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s64) + ; CHECK-NEXT: [[ZEXTLOAD3:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD3]], [[C1]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ZEXTLOAD2]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C3]](s64) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[OR]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64) + ; CHECK-NEXT: [[ZEXTLOAD4:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD3]](p0) :: (load (s8) from unknown-address + 4) + ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C]](s64) + ; CHECK-NEXT: [[ZEXTLOAD5:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD4]](p0) :: (load (s8) from unknown-address + 5) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD5]], [[C1]](s64) + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SHL3]], [[ZEXTLOAD4]] + ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C2]](s64) + ; CHECK-NEXT: [[ZEXTLOAD6:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6) + ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD5]], [[C]](s64) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7) + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[LOAD]], [[C1]](s64) + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[ZEXTLOAD6]] + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[OR4]], [[C3]](s64) + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL5]], [[OR3]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[OR5]], [[C5]](s64) + ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[OR2]] + ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64) + ; CHECK-NEXT: [[ZEXTLOAD7:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD7]](p0) :: (load (s8) from unknown-address + 8) + ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD7]], [[C]](s64) + ; CHECK-NEXT: [[ZEXTLOAD8:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD8]](p0) :: (load (s8) from unknown-address + 9) + ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD8]], [[C1]](s64) + ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s64) = G_OR [[SHL7]], [[ZEXTLOAD7]] + ; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD7]], [[C2]](s64) + ; CHECK-NEXT: [[ZEXTLOAD9:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD9]](p0) :: (load (s8) from unknown-address + 10) + ; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD9]], [[C]](s64) + ; CHECK-NEXT: [[ZEXTLOAD10:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD10]](p0) :: (load (s8) from unknown-address + 11) + ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD10]], [[C1]](s64) + ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s64) = G_OR [[SHL8]], [[ZEXTLOAD9]] + ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[OR8]], [[C3]](s64) + ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s64) = G_OR [[SHL9]], [[OR7]] + ; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD7]], [[C4]](s64) + ; CHECK-NEXT: [[ZEXTLOAD11:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD11]](p0) :: (load (s8) from unknown-address + 12) + ; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD11]], [[C]](s64) + ; CHECK-NEXT: [[ZEXTLOAD12:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD12]](p0) :: (load (s8) from unknown-address + 13) + ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD12]], [[C1]](s64) + ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s64) = G_OR [[SHL10]], [[ZEXTLOAD11]] + ; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD11]], [[C2]](s64) + ; CHECK-NEXT: [[ZEXTLOAD13:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD13]](p0) :: (load (s8) from unknown-address + 14) + ; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD13]], [[C]](s64) + ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD14]](p0) :: (load (s8) from unknown-address + 15) + ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(s64) = G_SHL [[LOAD1]], [[C1]](s64) + ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s64) = G_OR [[SHL11]], [[ZEXTLOAD13]] + ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(s64) = G_SHL [[OR11]], [[C3]](s64) + ; CHECK-NEXT: [[OR12:%[0-9]+]]:_(s64) = G_OR [[SHL12]], [[OR10]] + ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(s64) = G_SHL [[OR12]], [[C5]](s64) + ; CHECK-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[OR9]] + ; CHECK-NEXT: $x10 = COPY [[OR6]](s64) + ; CHECK-NEXT: $x11 = COPY [[OR13]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; UNALIGNED-LABEL: name: load_i128_unaligned + ; UNALIGNED: liveins: $x10 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64), align 1) + ; UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) + ; UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from unknown-address + 8, align 1) + ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s64) + ; UNALIGNED-NEXT: $x11 = COPY [[LOAD1]](s64) + ; UNALIGNED-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(p0) = COPY $x10 + %1:_(s128) = G_LOAD %0(p0) :: (load (s128), align 1) + %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %1(s128) + $x10 = COPY %2(s64) + $x11 = COPY %3(s64) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv32.mir new file mode 100644 index 0000000..71d7e83 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv32.mir @@ -0,0 +1,259 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: lshr_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_LSHR %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: lshr_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_LSHR %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: lshr_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_LSHR %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: lshr_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_LSHR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: lshr_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i48 + ; CHECK: %xlo:_(s32) = COPY $x10 + ; CHECK-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %xlo, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xhi, [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %ylo, [[C2]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], %ylo + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %ylo(s32), [[C2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %ylo(s32), [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], %ylo(s32) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], %ylo(s32) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[SUB1]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[SUB]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[LSHR2]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[AND]], [[SELECT]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[LSHR]], [[C3]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s48) = G_LSHR %x, %y + %z0:_(s64) = G_ANYEXT %z(s48) + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: lshr_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i64 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], %lo2 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %hi1, %lo2(s32) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR %lo1, %lo2(s32) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %hi1, [[SUB1]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %hi1, [[SUB]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[LSHR2]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %lo1, [[SELECT]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_LSHR %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: lshr_i96 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i96 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s32) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C1]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C1]], %lo2 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C1]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C2]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], %lo2 + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C2]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %hi1, %lo2(s32) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[SUB3]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[C]], [[SUB2]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR]], [[LSHR1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), %hi1, [[SELECT]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C2]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %mid1, %lo2(s32) + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR %lo1, %lo2(s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %mid1, [[SUB3]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL1]] + ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR %mid1, [[SUB2]](s32) + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[OR1]], [[LSHR4]] + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), %lo1, [[SELECT2]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[LSHR2]], [[C]] + ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]] + ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]] + ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]] + ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL %hi1, [[SUB1]](s32) + ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR %hi1, [[SUB5]](s32) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C]], [[SUB1]](s32) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL3]] + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %hi1, [[SUB4]](s32) + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[SHL2]], [[C]] + ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[OR2]], [[SHL4]] + ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s32), [[C]], [[SELECT6]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SELECT3]], [[SELECT5]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[SELECT4]], [[SELECT7]] + ; CHECK-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]] + ; CHECK-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]] + ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]] + ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB]](s32), [[C]] + ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[C]], [[SUB]](s32) + ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR %hi1, [[SUB]](s32) + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[C]], [[SUB7]](s32) + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR7]], [[SHL5]] + ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[C]], [[SUB6]](s32) + ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[ICMP8]](s32), [[OR5]], [[LSHR8]] + ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s32) = G_SELECT [[ICMP9]](s32), %hi1, [[SELECT8]] + ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s32) = G_SELECT [[ICMP8]](s32), [[LSHR6]], [[C]] + ; CHECK-NEXT: [[SELECT11:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR3]], [[SELECT9]] + ; CHECK-NEXT: [[SELECT12:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR4]], [[SELECT10]] + ; CHECK-NEXT: [[SELECT13:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %lo1, [[SELECT11]] + ; CHECK-NEXT: [[SELECT14:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %mid1, [[SELECT12]] + ; CHECK-NEXT: [[SELECT15:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SELECT1]], [[C]] + ; CHECK-NEXT: $x10 = COPY [[SELECT13]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT14]](s32) + ; CHECK-NEXT: $x12 = COPY [[SELECT15]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s32) = COPY $x10 + %mid1:_(s32) = COPY $x11 + %hi1:_(s32) = COPY $x12 + %lo2:_(s32) = COPY $x13 + %mid2:_(s32) = COPY $x14 + %hi2:_(s32) = COPY $x15 + %x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32) + %x2:_(s96) = G_MERGE_VALUES %lo2(s32), %mid2(s32), %hi2(s32) + %y:_(s96) = G_LSHR %x1, %x2 + %lo:_(s32), %mid:_(s32), %hi:_(s32) = G_UNMERGE_VALUES %y(s96) + $x10 = COPY %lo(s32) + $x11 = COPY %mid(s32) + $x12 = COPY %hi(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir new file mode 100644 index 0000000..ae58e2c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir @@ -0,0 +1,332 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: lshr_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_LSHR %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: lshr_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_LSHR %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: lshr_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_LSHR %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: lshr_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SRLW]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_LSHR %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: lshr_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_LSHR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: lshr_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i72 + ; CHECK: %x00:_(s64) = COPY $x10 + ; CHECK-NEXT: %x01:_(s64) = COPY $x11 + ; CHECK-NEXT: %y00:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %x00, [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %x01, [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %y00, [[C2]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C2]], %y00 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %y00(s64), [[C2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %y00(s64), [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], %y00(s64) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND]], %y00(s64) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[SUB1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[SUB]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR]], [[LSHR2]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[AND]], [[SELECT]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[LSHR]], [[C3]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s64) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %x00:_(s64) = COPY $x10 + %x01:_(s64) = COPY $x11 + %y00:_(s64) = COPY $x12 + %y01:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %x00(s64), %x01 + %y0:_(s128) = G_MERGE_VALUES %y00(s64), %y01 + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s72) = G_LSHR %x, %y + %z0:_(s128) = G_ANYEXT %z(s72) + %z00:_(s64), %z01:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %z00(s64) + $x11 = COPY %z01(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: lshr_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i128 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C]], %lo2 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR %hi1, %lo2(s64) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR %lo1, %lo2(s64) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %hi1, [[SUB1]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR %hi1, [[SUB]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR]], [[LSHR2]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %lo1, [[SELECT]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s64) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_LSHR %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: lshr_i192 +body: | + bb.0.entry: + ; CHECK-LABEL: name: lshr_i192 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s64) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 128 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C1]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C1]], %lo2 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C1]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C2]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s64) = G_SUB [[C2]], %lo2 + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C2]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR %hi1, %lo2(s64) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C]], [[SUB3]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[C]], [[SUB2]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s64), [[OR]], [[LSHR1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s64), %hi1, [[SELECT]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C2]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR %mid1, %lo2(s64) + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR %lo1, %lo2(s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %mid1, [[SUB3]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL1]] + ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR %mid1, [[SUB2]](s64) + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s64), [[OR1]], [[LSHR4]] + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s64), %lo1, [[SELECT2]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s64), [[LSHR2]], [[C]] + ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C2]] + ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s64) = G_SUB [[C2]], [[SUB1]] + ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB1]](s64), [[C2]] + ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL %hi1, [[SUB1]](s64) + ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR %hi1, [[SUB5]](s64) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[C]], [[SUB1]](s64) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR5]], [[SHL3]] + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL %hi1, [[SUB4]](s64) + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s64), [[SHL2]], [[C]] + ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s64), [[OR2]], [[SHL4]] + ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s64), [[C]], [[SELECT6]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT3]], [[SELECT5]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT7]] + ; CHECK-NEXT: [[SUB6:%[0-9]+]]:_(s64) = G_SUB [[SUB]], [[C2]] + ; CHECK-NEXT: [[SUB7:%[0-9]+]]:_(s64) = G_SUB [[C2]], [[SUB]] + ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB]](s64), [[C2]] + ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB]](s64), [[C]] + ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[C]], [[SUB]](s64) + ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR %hi1, [[SUB]](s64) + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[C]], [[SUB7]](s64) + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR7]], [[SHL5]] + ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[C]], [[SUB6]](s64) + ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s64), [[OR5]], [[LSHR8]] + ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s64), %hi1, [[SELECT8]] + ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s64), [[LSHR6]], [[C]] + ; CHECK-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR3]], [[SELECT9]] + ; CHECK-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR4]], [[SELECT10]] + ; CHECK-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %lo1, [[SELECT11]] + ; CHECK-NEXT: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %mid1, [[SELECT12]] + ; CHECK-NEXT: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SELECT1]], [[C]] + ; CHECK-NEXT: $x10 = COPY [[SELECT13]](s64) + ; CHECK-NEXT: $x11 = COPY [[SELECT14]](s64) + ; CHECK-NEXT: $x12 = COPY [[SELECT15]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s64) = COPY $x10 + %mid1:_(s64) = COPY $x11 + %hi1:_(s64) = COPY $x12 + %lo2:_(s64) = COPY $x13 + %mid2:_(s64) = COPY $x14 + %hi2:_(s64) = COPY $x15 + %x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64) + %x2:_(s192) = G_MERGE_VALUES %lo2(s64), %mid2(s64), %hi2(s64) + %y:_(s192) = G_LSHR %x1, %x2 + %lo:_(s64), %mid:_(s64), %hi:_(s64) = G_UNMERGE_VALUES %y(s192) + $x10 = COPY %lo(s64) + $x11 = COPY %mid(s64) + $x12 = COPY %hi(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... +--- +name: lshr_i48 +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: lshr_i48 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[AND1]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s48) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s48) = G_TRUNC %3(s64) + %4:_(s48) = G_LSHR %0, %1(s48) + %5:_(s64) = G_ANYEXT %4(s48) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: lshr_i32_i48 +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: lshr_i32_i48 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = COPY $x10 + %0:_(s48) = G_TRUNC %1(s64) + %2:_(s48) = G_CONSTANT i48 16 + %6:_(s32) = G_TRUNC %0(s48) + %7:_(s32) = G_LSHR %6, %2(s48) + %5:_(s64) = G_ANYEXT %7(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-memcpy-inline.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-memcpy-inline.mir new file mode 100644 index 0000000..671ac10 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-memcpy-inline.mir @@ -0,0 +1,48 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=riscv32 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=RISCV32 +# RUN: llc -mtriple=riscv64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=RISCV64 + +--- +name: test_memcpy_inline +alignment: 4 +liveins: + - { reg: '$x10', virtual-reg: '' } + - { reg: '$x11', virtual-reg: '' } +body: | + bb.0.entry: + liveins: $x10, $x11 + ; RISCV32-LABEL: name: test_memcpy_inline + ; RISCV32: liveins: $x10, $x11 + ; RISCV32-NEXT: {{ $}} + ; RISCV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RISCV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RISCV32-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY1]](p0) :: (load (s8), align 4) + ; RISCV32-NEXT: G_STORE [[LOAD]](s16), [[COPY]](p0) :: (store (s8), align 4) + ; RISCV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RISCV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s32) + ; RISCV32-NEXT: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) + ; RISCV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) + ; RISCV32-NEXT: G_STORE [[LOAD1]](s16), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1) + ; RISCV32-NEXT: PseudoRET + ; + ; RISCV64-LABEL: name: test_memcpy_inline + ; RISCV64: liveins: $x10, $x11 + ; RISCV64-NEXT: {{ $}} + ; RISCV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RISCV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RISCV64-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY1]](p0) :: (load (s8), align 4) + ; RISCV64-NEXT: G_STORE [[LOAD]](s16), [[COPY]](p0) :: (store (s8), align 4) + ; RISCV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RISCV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64) + ; RISCV64-NEXT: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) + ; RISCV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) + ; RISCV64-NEXT: G_STORE [[LOAD1]](s16), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1) + ; RISCV64-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + %2:_(s64) = G_CONSTANT i64 2 + %3:_(s32) = G_TRUNC %2(s64) + G_MEMCPY_INLINE %0(p0), %1(p0), %3(s32) :: (store (s8), align 4), (load (s8), align 4) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv32.mir new file mode 100644 index 0000000..fb9e6a7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv32.mir @@ -0,0 +1,230 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mattr=+m -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mattr=+zmmul -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: mul_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_MUL %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: mul_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_MUL %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: mul_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_MUL %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: mul_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_MUL %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: mul_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i48 + ; CHECK: %xlo:_(s32) = COPY $x10 + ; CHECK-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL %xlo, %ylo + ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH %xlo, %ylo + ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL %xlo, %yhi + ; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL %xhi, %ylo + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UMULH]], [[MUL1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: $x11 = COPY [[ADD1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s48) = G_MUL %x, %y + %z0:_(s64) = G_ANYEXT %z(s48) + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: mul_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i64 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL %lo1, %lo2 + ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH %lo1, %lo2 + ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL %lo1, %hi2 + ; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL %hi1, %lo2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UMULH]], [[MUL1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: $x11 = COPY [[ADD1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_MUL %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: mul_i96 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i96 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s32) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x13 + ; CHECK-NEXT: %mid2:_(s32) = COPY $x14 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x15 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL %lo1, %lo2 + ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH %lo1, %lo2 + ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL %lo1, %mid2 + ; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL %mid1, %lo2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UMULH]], [[MUL1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL1]] + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[MUL2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[MUL2]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32) + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH %mid1, %lo2 + ; CHECK-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH %lo1, %mid2 + ; CHECK-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL %lo1, %hi2 + ; CHECK-NEXT: [[MUL4:%[0-9]+]]:_(s32) = G_MUL %mid1, %mid2 + ; CHECK-NEXT: [[MUL5:%[0-9]+]]:_(s32) = G_MUL %hi1, %lo2 + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH1]], [[UMULH2]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD3]](s32) + ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[MUL3]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD4]](s32) + ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[MUL4]] + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD5]](s32) + ; CHECK-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[MUL5]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD6]](s32) + ; CHECK-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[COPY5]], [[ADD2]] + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD7]](s32) + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: $x12 = COPY [[COPY6]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s32) = COPY $x10 + %mid1:_(s32) = COPY $x11 + %hi1:_(s32) = COPY $x12 + %lo2:_(s32) = COPY $x13 + %mid2:_(s32) = COPY $x14 + %hi2:_(s32) = COPY $x15 + %x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32) + %x2:_(s96) = G_MERGE_VALUES %lo2(s32), %mid2(s32), %hi2(s32) + %y:_(s96) = G_MUL %x1, %x2 + %lo:_(s32), %mid:_(s32), %hi:_(s32) = G_UNMERGE_VALUES %y(s96) + $x10 = COPY %lo(s32) + $x11 = COPY %mid(s32) + $x12 = COPY %hi(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... +--- +name: smulh_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: smulh_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[MUL]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[ASHR2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_SMULH %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv64.mir new file mode 100644 index 0000000..56579c1 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv64.mir @@ -0,0 +1,248 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mattr=+m -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mattr=+zmmul -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: mul_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_MUL %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_MUL %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_MUL %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_MUL %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_MUL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i72 + ; CHECK: %xlo:_(s64) = COPY $x10 + ; CHECK-NEXT: %xhi:_(s64) = COPY $x11 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x12 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x13 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL %xlo, %ylo + ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s64) = G_UMULH %xlo, %ylo + ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL %xlo, %yhi + ; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(s64) = G_MUL %xhi, %ylo + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[UMULH]], [[MUL1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[MUL2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: $x11 = COPY [[ADD1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s64) = COPY $x10 + %xhi:_(s64) = COPY $x11 + %ylo:_(s64) = COPY $x12 + %yhi:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xlo(s64), %xhi(s64) + %y0:_(s128) = G_MERGE_VALUES %ylo(s64), %yhi(s64) + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s72) = G_MUL %x, %y + %z0:_(s128) = G_ANYEXT %z(s72) + %zlo:_(s64), %zhi:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %zlo(s64) + $x11 = COPY %zhi(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: mul_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i128 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL %lo1, %lo2 + ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s64) = G_UMULH %lo1, %lo2 + ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL %lo1, %hi2 + ; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(s64) = G_MUL %hi1, %lo2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[UMULH]], [[MUL1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[MUL2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: $x11 = COPY [[ADD1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_MUL %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: mul_i192 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i192 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s64) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x13 + ; CHECK-NEXT: %mid2:_(s64) = COPY $x14 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x15 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL %lo1, %lo2 + ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s64) = G_UMULH %lo1, %lo2 + ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL %lo1, %mid2 + ; CHECK-NEXT: [[MUL2:%[0-9]+]]:_(s64) = G_MUL %mid1, %lo2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[UMULH]], [[MUL1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), [[MUL1]] + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[ADD]](s64) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[MUL2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD1]](s64), [[MUL2]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ADD1]](s64) + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[UMULH1:%[0-9]+]]:_(s64) = G_UMULH %mid1, %lo2 + ; CHECK-NEXT: [[UMULH2:%[0-9]+]]:_(s64) = G_UMULH %lo1, %mid2 + ; CHECK-NEXT: [[MUL3:%[0-9]+]]:_(s64) = G_MUL %lo1, %hi2 + ; CHECK-NEXT: [[MUL4:%[0-9]+]]:_(s64) = G_MUL %mid1, %mid2 + ; CHECK-NEXT: [[MUL5:%[0-9]+]]:_(s64) = G_MUL %hi1, %lo2 + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s64) = G_ADD [[UMULH1]], [[UMULH2]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ADD3]](s64) + ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s64) = G_ADD [[COPY2]], [[MUL3]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[ADD4]](s64) + ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s64) = G_ADD [[COPY3]], [[MUL4]] + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY [[ADD5]](s64) + ; CHECK-NEXT: [[ADD6:%[0-9]+]]:_(s64) = G_ADD [[COPY4]], [[MUL5]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY [[ADD6]](s64) + ; CHECK-NEXT: [[ADD7:%[0-9]+]]:_(s64) = G_ADD [[COPY5]], [[ADD2]] + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY [[ADD7]](s64) + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-NEXT: $x12 = COPY [[COPY6]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s64) = COPY $x10 + %mid1:_(s64) = COPY $x11 + %hi1:_(s64) = COPY $x12 + %lo2:_(s64) = COPY $x13 + %mid2:_(s64) = COPY $x14 + %hi2:_(s64) = COPY $x15 + %x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64) + %x2:_(s192) = G_MERGE_VALUES %lo2(s64), %mid2(s64), %hi2(s64) + %y:_(s192) = G_MUL %x1, %x2 + %lo:_(s64), %mid:_(s64), %hi:_(s64) = G_UNMERGE_VALUES %y(s192) + $x10 = COPY %lo(s64) + $x11 = COPY %mid(s64) + $x12 = COPY %hi(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... +--- +name: smulh_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: smulh_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[MUL]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[ASHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_SMULH %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv32.mir new file mode 100644 index 0000000..70de06b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv32.mir @@ -0,0 +1,161 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: mul_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_MUL %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: mul_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_MUL %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: mul_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_MUL %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: mul_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_MUL %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: mul_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i64 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY %lo1(s32) + ; CHECK-NEXT: $x11 = COPY %hi1(s32) + ; CHECK-NEXT: $x12 = COPY %lo2(s32) + ; CHECK-NEXT: $x13 = COPY %hi2(s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_MUL %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: smulh_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: smulh_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C]](s32) + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-NEXT: $x11 = COPY [[ASHR]](s32) + ; CHECK-NEXT: $x12 = COPY [[COPY1]](s32) + ; CHECK-NEXT: $x13 = COPY [[ASHR1]](s32) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SMULH %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv64.mir new file mode 100644 index 0000000..401483c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv64.mir @@ -0,0 +1,186 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: mul_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_MUL %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_MUL %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_MUL %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_MUL %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_MUL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: mul_i128 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY %lo1(s64) + ; CHECK-NEXT: $x11 = COPY %hi1(s64) + ; CHECK-NEXT: $x12 = COPY %lo2(s64) + ; CHECK-NEXT: $x13 = COPY %hi2(s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_MUL %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: smulh_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: smulh_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[COPY1]], [[C]](s64) + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: $x11 = COPY [[ASHR]](s64) + ; CHECK-NEXT: $x12 = COPY [[COPY1]](s64) + ; CHECK-NEXT: $x13 = COPY [[ASHR1]](s64) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SMULH %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv32.mir new file mode 100644 index 0000000..42de607 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv32.mir @@ -0,0 +1,336 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mattr=+m -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mattr=+zmmul -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=LIBCALL + +--- +name: smulo_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: smulo_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[MUL]](s32), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: smulo_i8 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; LIBCALL-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; LIBCALL-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; LIBCALL-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; LIBCALL-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[ASHR]](s32) + ; LIBCALL-NEXT: $x11 = COPY [[ASHR1]](s32) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; LIBCALL-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) + ; LIBCALL-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY2]](s32), [[ASHR2]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s32) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s32) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8), %5:_(s1) = G_SMULO %0, %1 + %6:_(s32) = G_ANYEXT %4(s8) + %7:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %6(s32) + $x11 = COPY %7(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: smulo_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: smulo_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[MUL]](s32), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: smulo_i16 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; LIBCALL-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; LIBCALL-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; LIBCALL-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; LIBCALL-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[ASHR]](s32) + ; LIBCALL-NEXT: $x11 = COPY [[ASHR1]](s32) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; LIBCALL-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) + ; LIBCALL-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY2]](s32), [[ASHR2]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s32) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s32) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16), %5:_(s1) = G_SMULO %0, %1 + %6:_(s32) = G_ANYEXT %4(s16) + %7:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %6(s32) + $x11 = COPY %7(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: smulo_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: smulo_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SMULH:%[0-9]+]]:_(s32) = G_SMULH [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[MUL]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SMULH]](s32), [[ASHR]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: smulo_i32 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; LIBCALL-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; LIBCALL-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32) + ; LIBCALL-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C]](s32) + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[COPY]](s32) + ; LIBCALL-NEXT: $x11 = COPY [[ASHR]](s32) + ; LIBCALL-NEXT: $x12 = COPY [[COPY1]](s32) + ; LIBCALL-NEXT: $x13 = COPY [[ASHR1]](s32) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; LIBCALL-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11 + ; LIBCALL-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[COPY2]], [[C]](s32) + ; LIBCALL-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY2]] + ; LIBCALL-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[ASHR2]] + ; LIBCALL-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]] + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s32), [[C1]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s32) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s32) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32), %3:_(s1) = G_SMULO %0, %1 + %4:_(s32) = G_ANYEXT %3(s1) + $x10 = COPY %2(s32) + $x11 = COPY %4(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: umulo_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: umulo_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: umulo_i8 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; LIBCALL-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; LIBCALL-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[AND]](s32) + ; LIBCALL-NEXT: $x11 = COPY [[AND1]](s32) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; LIBCALL-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY2]](s32), [[AND2]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s32) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s32) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8), %5:_(s1) = G_UMULO %0, %1 + %6:_(s32) = G_ANYEXT %4(s8) + %7:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %6(s32) + $x11 = COPY %7(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: umulo_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: umulo_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: umulo_i16 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; LIBCALL-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; LIBCALL-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[AND]](s32) + ; LIBCALL-NEXT: $x11 = COPY [[AND1]](s32) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; LIBCALL-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY2]](s32), [[AND2]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s32) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s32) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16), %5:_(s1) = G_UMULO %0, %1 + %6:_(s32) = G_ANYEXT %4(s16) + %7:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %6(s32) + $x11 = COPY %7(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: umulo_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: umulo_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: umulo_i32 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[COPY]](s32) + ; LIBCALL-NEXT: $x11 = COPY [[C]](s32) + ; LIBCALL-NEXT: $x12 = COPY [[COPY1]](s32) + ; LIBCALL-NEXT: $x13 = COPY [[C]](s32) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; LIBCALL-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11 + ; LIBCALL-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; LIBCALL-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] + ; LIBCALL-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; LIBCALL-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[AND]] + ; LIBCALL-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[AND1]] + ; LIBCALL-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]] + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s32), [[C]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s32) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s32) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32), %3:_(s1) = G_UMULO %0, %1 + %4:_(s32) = G_ANYEXT %3(s1) + $x10 = COPY %2(s32) + $x11 = COPY %4(s32) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv64.mir new file mode 100644 index 0000000..996885b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv64.mir @@ -0,0 +1,438 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mattr=+m -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mattr=+zmmul -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=LIBCALL + +--- +name: smulo_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: smulo_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[MUL]], [[C]](s64) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[MUL]](s64), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: smulo_i8 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; LIBCALL-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; LIBCALL-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; LIBCALL-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; LIBCALL-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[ASHR]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[ASHR1]](s64) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[C]](s64) + ; LIBCALL-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY2]](s64), [[ASHR2]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s64) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s64) + %4:_(s8), %5:_(s1) = G_SMULO %0, %1 + %6:_(s64) = G_ANYEXT %4(s8) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: smulo_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: smulo_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[MUL]], [[C]](s64) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[MUL]](s64), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: smulo_i16 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; LIBCALL-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; LIBCALL-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; LIBCALL-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; LIBCALL-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[ASHR]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[ASHR1]](s64) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[C]](s64) + ; LIBCALL-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY2]](s64), [[ASHR2]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s64) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s64) + %4:_(s16), %5:_(s1) = G_SMULO %0, %1 + %6:_(s64) = G_ANYEXT %4(s16) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: smulo_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: smulo_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]] + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[MUL]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[MUL]](s64), [[SEXT_INREG2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: smulo_i32 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; LIBCALL-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; LIBCALL-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[SEXT_INREG1]](s64) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 32 + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY2]](s64), [[SEXT_INREG2]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s64) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32), %5:_(s1) = G_SMULO %0, %1 + %6:_(s64) = G_ANYEXT %4(s32) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: smulo_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: smulo_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SMULH:%[0-9]+]]:_(s64) = G_SMULH [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[MUL]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[SMULH]](s64), [[ASHR]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: smulo_i64 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; LIBCALL-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64) + ; LIBCALL-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[COPY1]], [[C]](s64) + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[COPY]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[ASHR]](s64) + ; LIBCALL-NEXT: $x12 = COPY [[COPY1]](s64) + ; LIBCALL-NEXT: $x13 = COPY [[ASHR1]](s64) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x11 + ; LIBCALL-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[COPY2]], [[C]](s64) + ; LIBCALL-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; LIBCALL-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[COPY2]] + ; LIBCALL-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[COPY3]], [[ASHR2]] + ; LIBCALL-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]] + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[OR]](s64), [[C1]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s64) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64), %3:_(s1) = G_SMULO %0, %1 + %4:_(s64) = G_ANYEXT %3(s1) + $x10 = COPY %2(s64) + $x11 = COPY %4(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: umulo_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: umulo_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND]], [[AND1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[MUL]](s64), [[AND2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: umulo_i8 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; LIBCALL-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; LIBCALL-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[AND]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[AND1]](s64) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY2]](s64), [[AND2]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s64) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s64) + %4:_(s8), %5:_(s1) = G_UMULO %0, %1 + %6:_(s64) = G_ANYEXT %4(s8) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: umulo_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: umulo_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND]], [[AND1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[MUL]](s64), [[AND2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: umulo_i16 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; LIBCALL-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; LIBCALL-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[AND]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[AND1]](s64) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY2]](s64), [[AND2]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s64) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s64) + %4:_(s16), %5:_(s1) = G_UMULO %0, %1 + %6:_(s64) = G_ANYEXT %4(s16) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: umulo_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: umulo_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND]], [[AND1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[MUL]](s64), [[AND2]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: umulo_i32 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; LIBCALL-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; LIBCALL-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[AND]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[AND1]](s64) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY2]](s64), [[AND2]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s64) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32), %5:_(s1) = G_UMULO %0, %1 + %6:_(s64) = G_ANYEXT %4(s32) + %7:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %6(s64) + $x11 = COPY %7(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: umulo_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: umulo_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s64) = G_UMULH [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[UMULH]](s64), [[C]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; LIBCALL-LABEL: name: umulo_i64 + ; LIBCALL: liveins: $x10, $x11 + ; LIBCALL-NEXT: {{ $}} + ; LIBCALL-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; LIBCALL-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; LIBCALL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: $x10 = COPY [[COPY]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[C]](s64) + ; LIBCALL-NEXT: $x12 = COPY [[COPY1]](s64) + ; LIBCALL-NEXT: $x13 = COPY [[C]](s64) + ; LIBCALL-NEXT: PseudoCALL target-flags(riscv-call) &__multi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; LIBCALL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; LIBCALL-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; LIBCALL-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x11 + ; LIBCALL-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; LIBCALL-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]] + ; LIBCALL-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY3]], [[C]] + ; LIBCALL-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[AND]] + ; LIBCALL-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[COPY3]], [[AND1]] + ; LIBCALL-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]] + ; LIBCALL-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[OR]](s64), [[C]] + ; LIBCALL-NEXT: $x10 = COPY [[COPY2]](s64) + ; LIBCALL-NEXT: $x11 = COPY [[ICMP]](s64) + ; LIBCALL-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64), %3:_(s1) = G_UMULO %0, %1 + %4:_(s64) = G_ANYEXT %3(s1) + $x10 = COPY %2(s64) + $x11 = COPY %4(s64) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-or-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-or-rv32.mir new file mode 100644 index 0000000..881f826 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-or-rv32.mir @@ -0,0 +1,171 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: or_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_OR %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: or_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_OR %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: or_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_OR %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: or_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_OR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: or_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i48 + ; CHECK: %xlo:_(s32) = COPY $x10 + ; CHECK-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR %xlo, %ylo + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR %xhi, %yhi + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: $x11 = COPY [[OR1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s48) = G_OR %x, %y + %z0:_(s64) = G_ANYEXT %z(s48) + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: or_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i64 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR %lo1, %lo2 + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR %hi1, %hi2 + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: $x11 = COPY [[OR1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_OR %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: or_i96 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i96 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s32) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x13 + ; CHECK-NEXT: %mid2:_(s32) = COPY $x14 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x15 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR %lo1, %lo2 + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR %mid1, %mid2 + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR %hi1, %hi2 + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: $x11 = COPY [[OR1]](s32) + ; CHECK-NEXT: $x12 = COPY [[OR2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s32) = COPY $x10 + %mid1:_(s32) = COPY $x11 + %hi1:_(s32) = COPY $x12 + %lo2:_(s32) = COPY $x13 + %mid2:_(s32) = COPY $x14 + %hi2:_(s32) = COPY $x15 + %x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32) + %x2:_(s96) = G_MERGE_VALUES %lo2(s32), %mid2(s32), %hi2(s32) + %y:_(s96) = G_OR %x1, %x2 + %lo:_(s32), %mid:_(s32), %hi:_(s32) = G_UNMERGE_VALUES %y(s96) + $x10 = COPY %lo(s32) + $x11 = COPY %mid(s32) + $x12 = COPY %hi(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-or-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-or-rv64.mir new file mode 100644 index 0000000..d5b26a4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-or-rv64.mir @@ -0,0 +1,191 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: or_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_OR %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: or_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_OR %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: or_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_OR %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: or_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_OR %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: or_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_OR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: or_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i72 + ; CHECK: %x00:_(s64) = COPY $x10 + ; CHECK-NEXT: %x01:_(s64) = COPY $x11 + ; CHECK-NEXT: %y00:_(s64) = COPY $x12 + ; CHECK-NEXT: %y01:_(s64) = COPY $x13 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR %x00, %y00 + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR %x01, %y01 + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: $x11 = COPY [[OR1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %x00:_(s64) = COPY $x10 + %x01:_(s64) = COPY $x11 + %y00:_(s64) = COPY $x12 + %y01:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %x00(s64), %x01 + %y0:_(s128) = G_MERGE_VALUES %y00(s64), %y01 + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s72) = G_OR %x, %y + %z0:_(s128) = G_ANYEXT %z(s72) + %z00:_(s64), %z01:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %z00(s64) + $x11 = COPY %z01(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: or_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i128 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR %lo1, %lo2 + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR %hi1, %hi2 + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: $x11 = COPY [[OR1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_OR %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: or_i192 +body: | + bb.0.entry: + ; CHECK-LABEL: name: or_i192 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s64) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x13 + ; CHECK-NEXT: %mid2:_(s64) = COPY $x14 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x15 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR %lo1, %lo2 + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR %mid1, %mid2 + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR %hi1, %hi2 + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: $x11 = COPY [[OR1]](s64) + ; CHECK-NEXT: $x12 = COPY [[OR2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s64) = COPY $x10 + %mid1:_(s64) = COPY $x11 + %hi1:_(s64) = COPY $x12 + %lo2:_(s64) = COPY $x13 + %mid2:_(s64) = COPY $x14 + %hi2:_(s64) = COPY $x15 + %x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64) + %x2:_(s192) = G_MERGE_VALUES %lo2(s64), %mid2(s64), %hi2(s64) + %y:_(s192) = G_OR %x1, %x2 + %lo:_(s64), %mid:_(s64), %hi:_(s64) = G_UNMERGE_VALUES %y(s192) + $x10 = COPY %lo(s64) + $x11 = COPY %mid(s64) + $x12 = COPY %hi(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv32.mir new file mode 100644 index 0000000..c8f73af --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv32.mir @@ -0,0 +1,622 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- | + define i1 @phi_i1(i1 %cnd, i1 %a, i1 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i1 [ %b, %cond.false ], [ %a, %entry ] + ret i1 %cond + } + + define i8 @phi_i8(i1 %cnd, i8 %a, i8 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i8 [ %b, %cond.false ], [ %a, %entry ] + ret i8 %cond + } + + define i16 @phi_i16(i1 %cnd, i16 %a, i16 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i16 [ %b, %cond.false ], [ %a, %entry ] + ret i16 %cond + } + + define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i32 [ %b, %cond.false ], [ %a, %entry ] + ret i32 %cond + } + + define ptr @phi_ptr(i1 %cnd, ptr %a, ptr %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi ptr [ %b, %cond.false ], [ %a, %entry ] + ret ptr %cond + } + + define i48 @phi_i48(i1 %cnd, i48 %a, i48 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i48 [ %b, %cond.false ], [ %a, %entry ] + ret i48 %cond + } + + define i64 @phi_i64(i1 %cnd, i64 %a, i64 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i64 [ %b, %cond.false ], [ %a, %entry ] + ret i64 %cond + } + + define i72 @phi_i72(i1 %cnd, i72 %a, i72 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i72 [ %b, %cond.false ], [ %a, %entry ] + ret i72 %cond + } + +... +--- +name: phi_i1 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i1 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY2]](s32), %bb.1, [[COPY1]](s32), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s32) + %4:_(s32) = COPY $x11 + %1:_(s1) = G_TRUNC %4(s32) + %5:_(s32) = COPY $x12 + %2:_(s1) = G_TRUNC %5(s32) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %6:_(s1) = G_PHI %2(s1), %bb.2, %1(s1), %bb.1 + %7:_(s32) = G_ANYEXT %6(s1) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 + +... +--- +name: phi_i8 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i8 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY2]](s32), %bb.1, [[COPY1]](s32), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s32) + %4:_(s32) = COPY $x11 + %1:_(s8) = G_TRUNC %4(s32) + %5:_(s32) = COPY $x12 + %2:_(s8) = G_TRUNC %5(s32) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %6:_(s8) = G_PHI %2(s8), %bb.2, %1(s8), %bb.1 + %7:_(s32) = G_ANYEXT %6(s8) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 + +... +--- +name: phi_i16 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i16 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY2]](s32), %bb.1, [[COPY1]](s32), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s32) + %4:_(s32) = COPY $x11 + %1:_(s16) = G_TRUNC %4(s32) + %5:_(s32) = COPY $x12 + %2:_(s16) = G_TRUNC %5(s32) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %6:_(s16) = G_PHI %2(s16), %bb.2, %1(s16), %bb.1 + %7:_(s32) = G_ANYEXT %6(s16) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 + +... +--- +name: phi_i32 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i32 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY2]](s32), %bb.1, [[COPY1]](s32), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s32) + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %4:_(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: phi_ptr +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_ptr + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p0) = G_PHI [[COPY2]](p0), %bb.1, [[COPY1]](p0), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s32) + %1:_(p0) = COPY $x11 + %2:_(p0) = COPY $x12 + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %4:_(p0) = G_PHI %2(p0), %bb.2, %1(p0), %bb.1 + $x10 = COPY %4(p0) + PseudoRET implicit $x10 + +... +--- +name: phi_i48 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } + - { id: 9, class: _ } + - { id: 10, class: _ } + - { id: 11, class: _ } + - { id: 12, class: _ } + - { id: 13, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i48 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY3]](s32), %bb.1, [[COPY1]](s32), %bb.0 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[COPY4]](s32), %bb.1, [[COPY2]](s32), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](s32) + ; CHECK-NEXT: $x11 = COPY [[PHI1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + bb.1.entry: + liveins: $x10, $x11, $x12, $x13, $x14 + + %3:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s32) + %4:_(s32) = COPY $x11 + %5:_(s32) = COPY $x12 + %6:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %1:_(s48) = G_TRUNC %6(s64) + %7:_(s32) = COPY $x13 + %8:_(s32) = COPY $x14 + %9:_(s64) = G_MERGE_VALUES %7(s32), %8(s32) + %2:_(s48) = G_TRUNC %9(s64) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %10:_(s48) = G_PHI %2(s48), %bb.2, %1(s48), %bb.1 + %13:_(s64) = G_ANYEXT %10(s48) + %11:_(s32), %12:_(s32) = G_UNMERGE_VALUES %13(s64) + $x10 = COPY %11(s32) + $x11 = COPY %12(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: phi_i64 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } + - { id: 9, class: _ } + - { id: 10, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i64 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY3]](s32), %bb.1, [[COPY1]](s32), %bb.0 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[COPY4]](s32), %bb.1, [[COPY2]](s32), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](s32) + ; CHECK-NEXT: $x11 = COPY [[PHI1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + bb.1.entry: + liveins: $x10, $x11, $x12, $x13, $x14 + + %3:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s32) + %4:_(s32) = COPY $x11 + %5:_(s32) = COPY $x12 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s32) = COPY $x13 + %7:_(s32) = COPY $x14 + %2:_(s64) = G_MERGE_VALUES %6(s32), %7(s32) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %8:_(s64) = G_PHI %2(s64), %bb.2, %1(s64), %bb.1 + %9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(s64) + $x10 = COPY %9(s32) + $x11 = COPY %10(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: phi_i72 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } + - { id: 9, class: _ } + - { id: 10, class: _ } + - { id: 11, class: _ } + - { id: 12, class: _ } + - { id: 13, class: _ } + - { id: 14, class: _ } + - { id: 15, class: _ } + - { id: 16, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i72 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY4]](s32), %bb.1, [[COPY1]](s32), %bb.0 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[COPY5]](s32), %bb.1, [[COPY2]](s32), %bb.0 + ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[COPY6]](s32), %bb.1, [[COPY3]](s32), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](s32) + ; CHECK-NEXT: $x10 = COPY [[PHI1]](s32) + ; CHECK-NEXT: $x10 = COPY [[PHI2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x10, implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s32) + %4:_(s32) = COPY $x11 + %5:_(s32) = COPY $x11 + %6:_(s32) = COPY $x11 + %7:_(s96) = G_MERGE_VALUES %4(s32), %5(s32), %6(s32) + %1:_(s72) = G_TRUNC %7(s96) + %8:_(s32) = COPY $x12 + %9:_(s32) = COPY $x12 + %10:_(s32) = COPY $x12 + %11:_(s96) = G_MERGE_VALUES %8(s32), %9(s32), %10(s32) + %2:_(s72) = G_TRUNC %11(s96) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %12:_(s72) = G_PHI %2(s72), %bb.2, %1(s72), %bb.1 + %16:_(s96) = G_ANYEXT %12(s72) + %13:_(s32), %14:_(s32), %15:_(s32) = G_UNMERGE_VALUES %16(s96) + $x10 = COPY %13(s32) + $x10 = COPY %14(s32) + $x10 = COPY %15(s32) + PseudoRET implicit $x10, implicit $x10, implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv64.mir new file mode 100644 index 0000000..9806826 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv64.mir @@ -0,0 +1,703 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- | + define i1 @phi_i1(i1 %cnd, i1 %a, i1 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i1 [ %b, %cond.false ], [ %a, %entry ] + ret i1 %cond + } + + define i8 @phi_i8(i1 %cnd, i8 %a, i8 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i8 [ %b, %cond.false ], [ %a, %entry ] + ret i8 %cond + } + + define i16 @phi_i16(i1 %cnd, i16 %a, i16 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i16 [ %b, %cond.false ], [ %a, %entry ] + ret i16 %cond + } + + define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i32 [ %b, %cond.false ], [ %a, %entry ] + ret i32 %cond + } + + define i64 @phi_i64(i1 %cnd, i64 %a, i64 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i64 [ %b, %cond.false ], [ %a, %entry ] + ret i64 %cond + } + + define ptr @phi_ptr(i1 %cnd, ptr %a, ptr %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi ptr [ %b, %cond.false ], [ %a, %entry ] + ret ptr %cond + } + + define i72 @phi_i72(i1 %cnd, i72 %a, i72 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i72 [ %b, %cond.false ], [ %a, %entry ] + ret i72 %cond + } + + define i128 @phi_i128(i1 %cnd, i128 %a, i128 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i128 [ %b, %cond.false ], [ %a, %entry ] + ret i128 %cond + } + + define i192 @phi_i192(i1 %cnd, i192 %a, i192 %b) { + entry: + br i1 %cnd, label %cond.end, label %cond.false + + cond.false: ; preds = %entry + br label %cond.end + + cond.end: ; preds = %entry, %cond.false + %cond = phi i192 [ %b, %cond.false ], [ %a, %entry ] + ret i192 %cond + } + +... +--- +name: phi_i1 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i1 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s64), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[PHI]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %1:_(s1) = G_TRUNC %4(s64) + %5:_(s64) = COPY $x12 + %2:_(s1) = G_TRUNC %5(s64) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %6:_(s1) = G_PHI %2(s1), %bb.2, %1(s1), %bb.1 + %7:_(s64) = G_ANYEXT %6(s1) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: phi_i8 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i8 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s64), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[PHI]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %1:_(s8) = G_TRUNC %4(s64) + %5:_(s64) = COPY $x12 + %2:_(s8) = G_TRUNC %5(s64) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %6:_(s8) = G_PHI %2(s8), %bb.2, %1(s8), %bb.1 + %7:_(s64) = G_ANYEXT %6(s8) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: phi_i16 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i16 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s64), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[PHI]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %1:_(s16) = G_TRUNC %4(s64) + %5:_(s64) = COPY $x12 + %2:_(s16) = G_TRUNC %5(s64) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %6:_(s16) = G_PHI %2(s16), %bb.2, %1(s16), %bb.1 + %7:_(s64) = G_ANYEXT %6(s16) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: phi_i32 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i32 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s64), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[PHI]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %4(s64) + %5:_(s64) = COPY $x12 + %2:_(s32) = G_TRUNC %5(s64) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %6:_(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1 + %7:_(s64) = G_ANYEXT %6(s32) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: phi_i64 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i64 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s64), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[COPY2]](s64), %bb.1, [[COPY1]](s64), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s64) + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %4:_(s64) = G_PHI %2(s64), %bb.2, %1(s64), %bb.1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: phi_ptr +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_ptr + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s64), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p0) = G_PHI [[COPY2]](p0), %bb.1, [[COPY1]](p0), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s64) + %1:_(p0) = COPY $x11 + %2:_(p0) = COPY $x12 + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %4:_(p0) = G_PHI %2(p0), %bb.2, %1(p0), %bb.1 + $x10 = COPY %4(p0) + PseudoRET implicit $x10 + +... +--- +name: phi_i72 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } + - { id: 9, class: _ } + - { id: 10, class: _ } + - { id: 11, class: _ } + - { id: 12, class: _ } + - { id: 13, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i72 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s64), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[COPY3]](s64), %bb.1, [[COPY1]](s64), %bb.0 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s64) = G_PHI [[COPY4]](s64), %bb.1, [[COPY2]](s64), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](s64) + ; CHECK-NEXT: $x11 = COPY [[PHI1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + bb.1.entry: + liveins: $x10, $x11, $x12, $x13, $x14 + + %3:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %5:_(s64) = COPY $x12 + %6:_(s128) = G_MERGE_VALUES %4(s64), %5(s64) + %1:_(s72) = G_TRUNC %6(s128) + %7:_(s64) = COPY $x13 + %8:_(s64) = COPY $x14 + %9:_(s128) = G_MERGE_VALUES %7(s64), %8(s64) + %2:_(s72) = G_TRUNC %9(s128) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %10:_(s72) = G_PHI %2(s72), %bb.2, %1(s72), %bb.1 + %13:_(s128) = G_ANYEXT %10(s72) + %11:_(s64), %12:_(s64) = G_UNMERGE_VALUES %13(s128) + $x10 = COPY %11(s64) + $x11 = COPY %12(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: phi_i128 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } + - { id: 9, class: _ } + - { id: 10, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i128 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s64), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[COPY3]](s64), %bb.1, [[COPY1]](s64), %bb.0 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s64) = G_PHI [[COPY4]](s64), %bb.1, [[COPY2]](s64), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](s64) + ; CHECK-NEXT: $x11 = COPY [[PHI1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + bb.1.entry: + liveins: $x10, $x11, $x12, $x13, $x14 + + %3:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %5:_(s64) = COPY $x12 + %1:_(s128) = G_MERGE_VALUES %4(s64), %5(s64) + %6:_(s64) = COPY $x13 + %7:_(s64) = COPY $x14 + %2:_(s128) = G_MERGE_VALUES %6(s64), %7(s64) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %8:_(s128) = G_PHI %2(s128), %bb.2, %1(s128), %bb.1 + %9:_(s64), %10:_(s64) = G_UNMERGE_VALUES %8(s128) + $x10 = COPY %9(s64) + $x11 = COPY %10(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: phi_i192 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } + - { id: 9, class: _ } + - { id: 10, class: _ } + - { id: 11, class: _ } + - { id: 12, class: _ } + - { id: 13, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: phi_i192 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: G_BRCOND [[AND]](s64), %bb.2 + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.cond.false: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.cond.end: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[COPY4]](s64), %bb.1, [[COPY1]](s64), %bb.0 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s64) = G_PHI [[COPY5]](s64), %bb.1, [[COPY2]](s64), %bb.0 + ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(s64) = G_PHI [[COPY6]](s64), %bb.1, [[COPY3]](s64), %bb.0 + ; CHECK-NEXT: $x10 = COPY [[PHI]](s64) + ; CHECK-NEXT: $x10 = COPY [[PHI1]](s64) + ; CHECK-NEXT: $x10 = COPY [[PHI2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x10, implicit $x10 + bb.1.entry: + liveins: $x10, $x11, $x12 + + %3:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %3(s64) + %4:_(s64) = COPY $x11 + %5:_(s64) = COPY $x11 + %6:_(s64) = COPY $x11 + %1:_(s192) = G_MERGE_VALUES %4(s64), %5(s64), %6(s64) + %7:_(s64) = COPY $x12 + %8:_(s64) = COPY $x12 + %9:_(s64) = COPY $x12 + %2:_(s192) = G_MERGE_VALUES %7(s64), %8(s64), %9(s64) + G_BRCOND %0(s1), %bb.3 + G_BR %bb.2 + + bb.2.cond.false: + + bb.3.cond.end: + %10:_(s192) = G_PHI %2(s192), %bb.2, %1(s192), %bb.1 + %11:_(s64), %12:_(s64), %13:_(s64) = G_UNMERGE_VALUES %10(s192) + $x10 = COPY %11(s64) + $x10 = COPY %12(s64) + $x10 = COPY %13(s64) + PseudoRET implicit $x10, implicit $x10, implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir new file mode 100644 index 0000000..dd645b0 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv32.mir @@ -0,0 +1,22 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: ptrmask_p0_s32 +body: | + bb.0: + liveins: $x10, $x11 + ; CHECK-LABEL: name: ptrmask_p0_s32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: $x10 = COPY [[PTRMASK]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(p0) = G_PTRMASK %0(p0), %1(s32) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir new file mode 100644 index 0000000..eced48f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrmask-rv64.mir @@ -0,0 +1,22 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: ptrmask_p0_s64 +body: | + bb.0: + liveins: $x10, $x11 + ; CHECK-LABEL: name: ptrmask_p0_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: $x10 = COPY [[PTRMASK]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(p0) = G_PTRMASK %0(p0), %1(s64) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrtoint-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrtoint-rv32.mir new file mode 100644 index 0000000..9fba2dd --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrtoint-rv32.mir @@ -0,0 +1,125 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: p0_s32 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_PTRTOINT %0(p0) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: p0_s16 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s16) = G_PTRTOINT %0(p0) + %2:_(s32) = G_ANYEXT %1(s16) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: p0_s8 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s8) = G_PTRTOINT %0(p0) + %2:_(s32) = G_ANYEXT %1(s8) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: p0_s1 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s1) = G_PTRTOINT %0(p0) + %2:_(s32) = G_ANYEXT %1(s1) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: p0_s64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32) + ; CHECK-NEXT: $x11 = COPY [[C]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_PTRTOINT %0(p0) + %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) + $x10 = COPY %2(s32) + $x11 = COPY %3(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: p0_s44 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s44 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s44) = G_PTRTOINT %0(p0) + %4:_(s32) = G_TRUNC %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrtoint-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrtoint-rv64.mir new file mode 100644 index 0000000..7299c59 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ptrtoint-rv64.mir @@ -0,0 +1,145 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: p0_s64 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_PTRTOINT %0(p0) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: p0_s32 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_PTRTOINT %0(p0) + %2:_(s64) = G_ANYEXT %1(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: p0_s16 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s16) = G_PTRTOINT %0(p0) + %2:_(s64) = G_ANYEXT %1(s16) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: p0_s8 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s8) = G_PTRTOINT %0(p0) + %2:_(s64) = G_ANYEXT %1(s8) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: p0_s1 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s1) = G_PTRTOINT %0(p0) + %2:_(s64) = G_ANYEXT %1(s1) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: p0_s128 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s128 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64) + ; CHECK-NEXT: $x11 = COPY [[C]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(p0) = COPY $x10 + %1:_(s128) = G_PTRTOINT %0(p0) + %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %1(s128) + $x10 = COPY %2(s64) + $x11 = COPY %3(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: p0_s88 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: p0_s88 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0) + ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s88) = G_PTRTOINT %0(p0) + %4:_(s64) = G_TRUNC %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv32.mir new file mode 100644 index 0000000..090acca --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv32.mir @@ -0,0 +1,539 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-I +# RUN: llc -mattr=+m -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-M +--- +name: srem_i7 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i7 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: srem_i7 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-M-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]] + ; CHECK-M-NEXT: $x10 = COPY [[SREM]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_SREM %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: srem_i8 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i8 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: srem_i8 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-M-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]] + ; CHECK-M-NEXT: $x10 = COPY [[SREM]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_SREM %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: srem_i16 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i16 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: srem_i16 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-M-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]] + ; CHECK-M-NEXT: $x10 = COPY [[SREM]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_SREM %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: srem_i32 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i32 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: srem_i32 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: $x10 = COPY [[SREM]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SREM %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: srem_i48 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i48 + ; CHECK-I: %xlo:_(s32) = COPY $x10 + ; CHECK-I-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-I-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-I-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C]](s32) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %yhi, [[C]](s32) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY %xlo(s32) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s32) + ; CHECK-I-NEXT: $x12 = COPY %ylo(s32) + ; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: srem_i48 + ; CHECK-M: %xlo:_(s32) = COPY $x10 + ; CHECK-M-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-M-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-M-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C]](s32) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %yhi, [[C]](s32) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY %xlo(s32) + ; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s32) + ; CHECK-M-NEXT: $x12 = COPY %ylo(s32) + ; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s32) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0 + %y:_(s48) = G_TRUNC %y0 + %z:_(s48) = G_SREM %x, %y + %z0:_(s64) = G_ANYEXT %z + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: srem_i64 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i64 + ; CHECK-I: %lo1:_(s32) = COPY $x10 + ; CHECK-I-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-I-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-I-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY %lo1(s32) + ; CHECK-I-NEXT: $x11 = COPY %hi1(s32) + ; CHECK-I-NEXT: $x12 = COPY %lo2(s32) + ; CHECK-I-NEXT: $x13 = COPY %hi2(s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: srem_i64 + ; CHECK-M: %lo1:_(s32) = COPY $x10 + ; CHECK-M-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-M-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-M-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY %lo1(s32) + ; CHECK-M-NEXT: $x11 = COPY %hi1(s32) + ; CHECK-M-NEXT: $x12 = COPY %lo2(s32) + ; CHECK-M-NEXT: $x13 = COPY %hi2(s32) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_SREM %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: urem_i7 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i7 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: urem_i7 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-M-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]] + ; CHECK-M-NEXT: $x10 = COPY [[UREM]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_UREM %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: urem_i8 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i8 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: urem_i8 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-M-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]] + ; CHECK-M-NEXT: $x10 = COPY [[UREM]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_UREM %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: urem_i16 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i16 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: urem_i16 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-M-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]] + ; CHECK-M-NEXT: $x10 = COPY [[UREM]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_UREM %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: urem_i32 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i32 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodsi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: urem_i32 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: $x10 = COPY [[UREM]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_UREM %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: urem_i48 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i48 + ; CHECK-I: %xlo:_(s32) = COPY $x10 + ; CHECK-I-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-I-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-I-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %xlo, [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xhi, [[C1]] + ; CHECK-I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %ylo, [[C]] + ; CHECK-I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %yhi, [[C1]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-I-NEXT: $x12 = COPY [[AND2]](s32) + ; CHECK-I-NEXT: $x13 = COPY [[AND3]](s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: urem_i48 + ; CHECK-M: %xlo:_(s32) = COPY $x10 + ; CHECK-M-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-M-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-M-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %xlo, [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %xhi, [[C1]] + ; CHECK-M-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND %ylo, [[C]] + ; CHECK-M-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND %yhi, [[C1]] + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY [[AND]](s32) + ; CHECK-M-NEXT: $x11 = COPY [[AND1]](s32) + ; CHECK-M-NEXT: $x12 = COPY [[AND2]](s32) + ; CHECK-M-NEXT: $x13 = COPY [[AND3]](s32) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0 + %y:_(s48) = G_TRUNC %y0 + %z:_(s48) = G_UREM %x, %y + %z0:_(s64) = G_ANYEXT %z + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: urem_i64 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i64 + ; CHECK-I: %lo1:_(s32) = COPY $x10 + ; CHECK-I-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-I-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-I-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY %lo1(s32) + ; CHECK-I-NEXT: $x11 = COPY %hi1(s32) + ; CHECK-I-NEXT: $x12 = COPY %lo2(s32) + ; CHECK-I-NEXT: $x13 = COPY %hi2(s32) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: urem_i64 + ; CHECK-M: %lo1:_(s32) = COPY $x10 + ; CHECK-M-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-M-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-M-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY %lo1(s32) + ; CHECK-M-NEXT: $x11 = COPY %hi1(s32) + ; CHECK-M-NEXT: $x12 = COPY %lo2(s32) + ; CHECK-M-NEXT: $x13 = COPY %hi2(s32) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s32) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s32) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_UREM %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir new file mode 100644 index 0000000..8239bb6 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir @@ -0,0 +1,610 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-I +# RUN: llc -mattr=+m -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s -check-prefix=CHECK-M +--- +name: srem_i8 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i8 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: srem_i8 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-M-NEXT: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[ASHR]], [[ASHR1]] + ; CHECK-M-NEXT: $x10 = COPY [[SREM]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_SREM %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: srem_i15 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i15 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: srem_i15 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-M-NEXT: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[ASHR]], [[ASHR1]] + ; CHECK-M-NEXT: $x10 = COPY [[SREM]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_SREM %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: srem_i16 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i16 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: srem_i16 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-M-NEXT: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[ASHR]], [[ASHR1]] + ; CHECK-M-NEXT: $x10 = COPY [[SREM]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_SREM %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: srem_i32 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i32 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[SEXT_INREG1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: srem_i32 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-M-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-M-NEXT: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]] + ; CHECK-M-NEXT: $x10 = COPY [[SREM]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_SREM %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: srem_i64 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i64 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: srem_i64 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: $x10 = COPY [[SREM]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SREM %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: srem_i72 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i72 + ; CHECK-I: %xlo:_(s64) = COPY $x10 + ; CHECK-I-NEXT: %xhi:_(s64) = COPY $x11 + ; CHECK-I-NEXT: %ylo:_(s64) = COPY $x12 + ; CHECK-I-NEXT: %yhi:_(s64) = COPY $x13 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %xhi, [[C]](s64) + ; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %yhi, [[C]](s64) + ; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY %xlo(s64) + ; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s64) + ; CHECK-I-NEXT: $x12 = COPY %ylo(s64) + ; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: srem_i72 + ; CHECK-M: %xlo:_(s64) = COPY $x10 + ; CHECK-M-NEXT: %xhi:_(s64) = COPY $x11 + ; CHECK-M-NEXT: %ylo:_(s64) = COPY $x12 + ; CHECK-M-NEXT: %yhi:_(s64) = COPY $x13 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %xhi, [[C]](s64) + ; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %yhi, [[C]](s64) + ; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY %xlo(s64) + ; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s64) + ; CHECK-M-NEXT: $x12 = COPY %ylo(s64) + ; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s64) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s64) = COPY $x10 + %xhi:_(s64) = COPY $x11 + %ylo:_(s64) = COPY $x12 + %yhi:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xlo(s64), %xhi(s64) + %y0:_(s128) = G_MERGE_VALUES %ylo(s64), %yhi(s64) + %x:_(s72) = G_TRUNC %x0 + %y:_(s72) = G_TRUNC %y0 + %z:_(s72) = G_SREM %x, %y + %z0:_(s128) = G_ANYEXT %z + %zlo:_(s64), %zhi:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %zlo(s64) + $x11 = COPY %zhi(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: srem_i128 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: srem_i128 + ; CHECK-I: %lo1:_(s64) = COPY $x10 + ; CHECK-I-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-I-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-I-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY %lo1(s64) + ; CHECK-I-NEXT: $x11 = COPY %hi1(s64) + ; CHECK-I-NEXT: $x12 = COPY %lo2(s64) + ; CHECK-I-NEXT: $x13 = COPY %hi2(s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: srem_i128 + ; CHECK-M: %lo1:_(s64) = COPY $x10 + ; CHECK-M-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-M-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-M-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY %lo1(s64) + ; CHECK-M-NEXT: $x11 = COPY %hi1(s64) + ; CHECK-M-NEXT: $x12 = COPY %lo2(s64) + ; CHECK-M-NEXT: $x13 = COPY %hi2(s64) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_SREM %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: urem_i8 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i8 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: urem_i8 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-M-NEXT: [[REMUW:%[0-9]+]]:_(s64) = G_REMUW [[AND]], [[AND1]] + ; CHECK-M-NEXT: $x10 = COPY [[REMUW]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_UREM %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: urem_i15 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i15 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: urem_i15 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-M-NEXT: [[REMUW:%[0-9]+]]:_(s64) = G_REMUW [[AND]], [[AND1]] + ; CHECK-M-NEXT: $x10 = COPY [[REMUW]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_UREM %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: urem_i16 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i16 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: urem_i16 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-M-NEXT: [[REMUW:%[0-9]+]]:_(s64) = G_REMUW [[AND]], [[AND1]] + ; CHECK-M-NEXT: $x10 = COPY [[REMUW]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_UREM %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: urem_i32 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i32 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: urem_i32 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[REMUW:%[0-9]+]]:_(s64) = G_REMUW [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: $x10 = COPY [[REMUW]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_UREM %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: urem_i64 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i64 + ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-M-LABEL: name: urem_i64 + ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[COPY]], [[COPY1]] + ; CHECK-M-NEXT: $x10 = COPY [[UREM]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_UREM %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: urem_i72 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i72 + ; CHECK-I: %xlo:_(s64) = COPY $x10 + ; CHECK-I-NEXT: %xhi:_(s64) = COPY $x11 + ; CHECK-I-NEXT: %ylo:_(s64) = COPY $x12 + ; CHECK-I-NEXT: %yhi:_(s64) = COPY $x13 + ; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %xlo, [[C]] + ; CHECK-I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xhi, [[C1]] + ; CHECK-I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %ylo, [[C]] + ; CHECK-I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %yhi, [[C1]] + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-I-NEXT: $x12 = COPY [[AND2]](s64) + ; CHECK-I-NEXT: $x13 = COPY [[AND3]](s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: urem_i72 + ; CHECK-M: %xlo:_(s64) = COPY $x10 + ; CHECK-M-NEXT: %xhi:_(s64) = COPY $x11 + ; CHECK-M-NEXT: %ylo:_(s64) = COPY $x12 + ; CHECK-M-NEXT: %yhi:_(s64) = COPY $x13 + ; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %xlo, [[C]] + ; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND %xhi, [[C1]] + ; CHECK-M-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND %ylo, [[C]] + ; CHECK-M-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND %yhi, [[C1]] + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-M-NEXT: $x11 = COPY [[AND1]](s64) + ; CHECK-M-NEXT: $x12 = COPY [[AND2]](s64) + ; CHECK-M-NEXT: $x13 = COPY [[AND3]](s64) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s64) = COPY $x10 + %xhi:_(s64) = COPY $x11 + %ylo:_(s64) = COPY $x12 + %yhi:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %xlo(s64), %xhi(s64) + %y0:_(s128) = G_MERGE_VALUES %ylo(s64), %yhi(s64) + %x:_(s72) = G_TRUNC %x0 + %y:_(s72) = G_TRUNC %y0 + %z:_(s72) = G_UREM %x, %y + %z0:_(s128) = G_ANYEXT %z + %zlo:_(s64), %zhi:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %zlo(s64) + $x11 = COPY %zhi(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: urem_i128 +body: | + bb.0.entry: + ; CHECK-I-LABEL: name: urem_i128 + ; CHECK-I: %lo1:_(s64) = COPY $x10 + ; CHECK-I-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-I-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-I-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: $x10 = COPY %lo1(s64) + ; CHECK-I-NEXT: $x11 = COPY %hi1(s64) + ; CHECK-I-NEXT: $x12 = COPY %lo2(s64) + ; CHECK-I-NEXT: $x13 = COPY %hi2(s64) + ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-I-NEXT: PseudoRET implicit $x10, implicit $x11 + ; + ; CHECK-M-LABEL: name: urem_i128 + ; CHECK-M: %lo1:_(s64) = COPY $x10 + ; CHECK-M-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-M-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-M-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-M-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: $x10 = COPY %lo1(s64) + ; CHECK-M-NEXT: $x11 = COPY %hi1(s64) + ; CHECK-M-NEXT: $x12 = COPY %lo2(s64) + ; CHECK-M-NEXT: $x13 = COPY %hi2(s64) + ; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11 + ; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-M-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-M-NEXT: $x11 = COPY [[COPY1]](s64) + ; CHECK-M-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_UREM %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir new file mode 100644 index 0000000..144de91 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir @@ -0,0 +1,338 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32I +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB_OR_RV32ZBKB +# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB_OR_RV32ZBKB + +--- +name: rotl_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotl_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8) = G_ROTL %0, %1(s8) + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: rotl_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotl_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16) = G_ROTL %0, %1(s16) + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: rotl_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: rotl_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32) + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND1]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]] + ; RV32I-NEXT: $x10 = COPY [[OR]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB_OR_RV32ZBKB-LABEL: name: rotl_i32 + ; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11 + ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}} + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[COPY1]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[ROTL]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_ROTL %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: rotl_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13 + + ; CHECK-LABEL: name: rotl_i64 + ; CHECK: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[C2]] + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[AND]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[C2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[SUB2]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[AND]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB1]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SHL]], [[C]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY1]], [[SELECT1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[AND1]], [[C2]] + ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[AND1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[C2]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[C]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[AND1]](s32) + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND1]](s32) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[SUB4]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL3]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[SUB3]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR1]], [[LSHR3]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[COPY]], [[SELECT3]] + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[LSHR1]], [[C]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[SELECT4]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SELECT2]], [[SELECT5]] + ; CHECK-NEXT: $x10 = COPY [[OR2]](s32) + ; CHECK-NEXT: $x11 = COPY [[OR3]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64) = G_ROTL %0, %1(s64) + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $x10 = COPY %7(s32) + $x11 = COPY %8(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: rotr_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotr_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND3]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8) = G_ROTR %0, %1(s8) + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: rotr_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotr_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND3]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16) = G_ROTR %0, %1(s16) + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: rotr_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: rotr_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND]](s32) + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]] + ; RV32I-NEXT: $x10 = COPY [[OR]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB_OR_RV32ZBKB-LABEL: name: rotr_i32 + ; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11 + ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}} + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[COPY1]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[ROTR]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_ROTR %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: rotr_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13 + + ; CHECK-LABEL: name: rotr_i64 + ; CHECK: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[C2]] + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[AND]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[C2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[AND]](s32) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND]](s32) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[SUB2]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[SUB1]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[LSHR2]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY]], [[SELECT]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[LSHR]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[AND1]], [[C2]] + ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[AND1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[C2]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[C]] + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32) + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[SUB4]](s32) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[AND1]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL2]] + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB3]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[SHL1]], [[C]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR1]], [[SHL3]] + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[COPY1]], [[SELECT4]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT1]], [[SELECT3]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SELECT2]], [[SELECT5]] + ; CHECK-NEXT: $x10 = COPY [[OR2]](s32) + ; CHECK-NEXT: $x11 = COPY [[OR3]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64) = G_ROTR %0, %1(s64) + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $x10 = COPY %7(s32) + $x11 = COPY %8(s32) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir new file mode 100644 index 0000000..8419f77 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir @@ -0,0 +1,300 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV64I +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB_OR_RV64ZBKB +# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB_OR_RV64ZBKB + +--- +name: rotl_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotl_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s64) + %4:_(s8) = G_ROTL %0, %1(s8) + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: rotl_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotl_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s64) + %4:_(s16) = G_ROTL %0, %1(s16) + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: rotl_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: rotl_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; RV64I-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] + ; RV64I-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[AND1]] + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SLLW]], [[SRLW]] + ; RV64I-NEXT: $x10 = COPY [[OR]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotl_i32 + ; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11 + ; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}} + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROLW:%[0-9]+]]:_(s64) = G_ROLW [[COPY]], [[COPY1]] + ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ROLW]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32) = G_ROTL %0, %1(s32) + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: rotl_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: rotl_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND1]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]] + ; RV64I-NEXT: $x10 = COPY [[OR]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotl_i64 + ; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11 + ; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}} + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[COPY]], [[COPY1]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ROTL]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_ROTL %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: rotr_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotr_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND3]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s64) + %4:_(s8) = G_ROTR %0, %1(s8) + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: rotr_i16 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotr_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND3]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s16) = G_TRUNC %3(s64) + %4:_(s16) = G_ROTR %0, %1(s16) + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: rotr_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: rotr_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; RV64I-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[AND]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] + ; RV64I-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND1]] + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SRLW]], [[SLLW]] + ; RV64I-NEXT: $x10 = COPY [[OR]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotr_i32 + ; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11 + ; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}} + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[RORW:%[0-9]+]]:_(s64) = G_RORW [[COPY]], [[COPY1]] + ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[RORW]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32) = G_ROTR %0, %1(s32) + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: rotr_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: rotr_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s64) + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[LSHR]], [[SHL]] + ; RV64I-NEXT: $x10 = COPY [[OR]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotr_i64 + ; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11 + ; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}} + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[COPY]], [[COPY1]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ROTR]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_ROTR %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sadde-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sadde-rv32.mir new file mode 100644 index 0000000..c67998e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sadde-rv32.mir @@ -0,0 +1,184 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: sadde_i8 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: sadde_i8 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY3]](s32), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[COPY3]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s8) = G_TRUNC %0(s32) + %2:_(s32) = COPY $x11 + %3:_(s8) = G_TRUNC %2(s32) + %4:_(s32) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s32) + %6:_(s8), %7:_(s1) = G_SADDE %1, %3, %5 + %8:_(s32) = G_ANYEXT %6(s8) + %9:_(s32) = G_ANYEXT %7(s1) + $x10 = COPY %8(s32) + $x11 = COPY %9(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sadde_i16 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: sadde_i16 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY3]](s32), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[COPY3]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s16) = G_TRUNC %0(s32) + %2:_(s32) = COPY $x11 + %3:_(s16) = G_TRUNC %2(s32) + %4:_(s32) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s32) + %6:_(s16), %7:_(s1) = G_SADDE %1, %3, %5 + %8:_(s32) = G_ANYEXT %6(s16) + %9:_(s32) = G_ANYEXT %7(s1) + $x10 = COPY %8(s32) + $x11 = COPY %9(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sadde_i32 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: sadde_i32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[COPY]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD1]], [[COPY1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[AND1]](s32), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[COPY3]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s1) = G_TRUNC %2(s32) + %4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3 + %6:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %4(s32) + $x11 = COPY %6(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sadde_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: sadde_i64 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY2]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]] + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[COPY5]], [[AND]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[AND]] + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD3]](s32) + ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[AND1]] + ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ICMP1]] + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD5]](s32) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY7]], [[COPY]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY8]], [[COPY1]] + ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[COPY7]], [[COPY2]] + ; CHECK-NEXT: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[COPY8]], [[COPY3]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[XOR2]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[XOR3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND2]](s32), [[C]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[AND3]](s32), [[C]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND3]](s32), [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[ICMP2]], [[ICMP3]] + ; CHECK-NEXT: $x10 = COPY [[COPY7]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY8]](s32) + ; CHECK-NEXT: $x12 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $x12 + %4:_(s32) = COPY $x13 + %5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32) + %6:_(s32) = COPY $x14 + %7:_(s1) = G_TRUNC %6(s32) + %8:_(s64), %9:_(s1) = G_SADDE %2, %5, %7 + %10:_(s32), %11:_(s32) = G_UNMERGE_VALUES %8(s64) + %12:_(s32) = G_ANYEXT %9(s1) + $x10 = COPY %10(s32) + $x11 = COPY %11(s32) + $x12 = COPY %12(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sadde-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sadde-rv64.mir new file mode 100644 index 0000000..413aaff --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sadde-rv64.mir @@ -0,0 +1,225 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: sadde_i8 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: sadde_i8 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[AND]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[ADD1]](s64) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[COPY3]], [[C]](s64) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY3]](s64), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[COPY3]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s8) = G_TRUNC %0(s64) + %2:_(s64) = COPY $x11 + %3:_(s8) = G_TRUNC %2(s64) + %4:_(s64) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s64) + %6:_(s8), %7:_(s1) = G_SADDE %1, %3, %5 + %8:_(s64) = G_ANYEXT %6(s8) + %9:_(s64) = G_ANYEXT %7(s1) + $x10 = COPY %8(s64) + $x11 = COPY %9(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sadde_i16 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: sadde_i16 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[AND]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[ADD1]](s64) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[COPY3]], [[C]](s64) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY3]](s64), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[COPY3]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s16) = G_TRUNC %0(s64) + %2:_(s64) = COPY $x11 + %3:_(s16) = G_TRUNC %2(s64) + %4:_(s64) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s64) + %6:_(s16), %7:_(s1) = G_SADDE %1, %3, %5 + %8:_(s64) = G_ANYEXT %6(s16) + %9:_(s64) = G_ANYEXT %7(s1) + $x10 = COPY %8(s64) + $x11 = COPY %9(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sadde_i32 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: sadde_i32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[AND]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[ADD1]](s64) + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY3]](s64), [[SEXT_INREG2]] + ; CHECK-NEXT: $x10 = COPY [[COPY3]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s32) = G_TRUNC %0(s64) + %2:_(s64) = COPY $x11 + %3:_(s32) = G_TRUNC %2(s64) + %4:_(s64) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s64) + %6:_(s32), %7:_(s1) = G_SADDE %1, %3, %5 + %8:_(s64) = G_ANYEXT %6(s32) + %9:_(s64) = G_ANYEXT %7(s1) + $x10 = COPY %8(s64) + $x11 = COPY %9(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sadde_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: sadde_i64 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[AND]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[ADD1]](s64) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD1]], [[COPY]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[ADD1]], [[COPY1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[AND1]](s64), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[COPY3]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + %3:_(s1) = G_TRUNC %2(s64) + %4:_(s64), %5:_(s1) = G_SADDE %0, %1, %3 + %6:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %4(s64) + $x11 = COPY %6(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sadde_i128 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: sadde_i128 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), [[COPY2]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY [[ADD]](s64) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY [[ADD2]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY4]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]] + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s64) = G_ADD [[COPY5]], [[AND]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD3]](s64), [[AND]] + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY [[ADD3]](s64) + ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s64) = G_ADD [[COPY6]], [[AND1]] + ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s64) = G_ADD [[ADD4]], [[ICMP1]] + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY [[ADD5]](s64) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY7]], [[COPY]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[COPY8]], [[COPY1]] + ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[COPY7]], [[COPY2]] + ; CHECK-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[COPY8]], [[COPY3]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[XOR2]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[XOR1]], [[XOR3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND2]](s64), [[C]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[AND3]](s64), [[C]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND3]](s64), [[C]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP3]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[COPY7]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY8]](s64) + ; CHECK-NEXT: $x12 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s128) = G_MERGE_VALUES %0(s64), %1(s64) + %3:_(s64) = COPY $x12 + %4:_(s64) = COPY $x13 + %5:_(s128) = G_MERGE_VALUES %3(s64), %4(s64) + %6:_(s64) = COPY $x14 + %7:_(s1) = G_TRUNC %6(s64) + %8:_(s128), %9:_(s1) = G_SADDE %2, %5, %7 + %10:_(s64), %11:_(s64) = G_UNMERGE_VALUES %8(s128) + %12:_(s64) = G_ANYEXT %9(s1) + $x10 = COPY %10(s64) + $x11 = COPY %11(s64) + $x12 = COPY %12(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir new file mode 100644 index 0000000..d7b1fac --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir @@ -0,0 +1,573 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32I +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB + +--- +name: uaddsat_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: uaddsat_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]] + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C]], [[COPY2]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: uaddsat_i32 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32ZBB-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[COPY1]] + ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[UMIN]] + ; RV32ZBB-NEXT: $x10 = COPY [[ADD]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_UADDSAT %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: uaddsat_i64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: uaddsat_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY2]] + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32) + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[COPY2]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY5]](s32), [[COPY3]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY5]](s32), [[COPY3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[C]], [[COPY4]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[C]], [[COPY5]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64) = G_UADDSAT %0, %1(s64) + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $x10 = COPY %7(s32) + $x11 = COPY %8(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: saddsat_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: saddsat_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ADD]](s32), [[COPY]] + ; RV32I-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[C]] + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP1]], [[ICMP]] + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY2]], [[C1]](s32) + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 + ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s32), [[ADD1]], [[COPY2]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: saddsat_i32 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 + ; RV32ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[C2]] + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SMAX]] + ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[C2]] + ; RV32ZBB-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMIN]] + ; RV32ZBB-NEXT: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[COPY1]] + ; RV32ZBB-NEXT: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]] + ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[SMIN1]] + ; RV32ZBB-NEXT: $x10 = COPY [[ADD]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SADDSAT %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: saddsat_i64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: saddsat_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY2]] + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32) + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[COPY]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY5]](s32), [[COPY1]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY5]](s32), [[COPY1]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY3]](s32), [[C]] + ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[ICMP4]], [[ICMP5]] + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[SELECT]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY5]], [[C1]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C]] + ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C]] + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD3]](s32) + ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]] + ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ICMP7]] + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD5]](s32) + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s32), [[COPY6]], [[COPY4]] + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s32), [[COPY7]], [[COPY5]] + ; CHECK-NEXT: $x10 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT3]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64) = G_SADDSAT %0, %1(s64) + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $x10 = COPY %7(s32) + $x11 = COPY %8(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: usubsat_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: usubsat_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]] + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C]], [[SUB]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: usubsat_i32 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]] + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[UMIN]] + ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_USUBSAT %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: usubsat_i64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: usubsat_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[C]], [[SUB]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[C]], [[SUB2]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64) = G_USUBSAT %0, %1(s64) + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $x10 = COPY %7(s32) + $x11 = COPY %8(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssubsat_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: ssubsat_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]] + ; RV32I-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB]](s32), [[C]] + ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP]], [[ICMP1]] + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY2]], [[C1]](s32) + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s32), [[ADD]], [[COPY2]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: ssubsat_i32 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 + ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 + ; RV32ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[C2]] + ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[C]] + ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[C2]] + ; RV32ZBB-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C1]] + ; RV32ZBB-NEXT: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[COPY1]] + ; RV32ZBB-NEXT: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]] + ; RV32ZBB-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[SMIN1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SUB2]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SSUBSAT %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: ssubsat_i64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: ssubsat_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB2]](s32), [[C]] + ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB2]](s32), [[C]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[ICMP4]], [[ICMP5]] + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SELECT]], [[SELECT1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C1]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C]] + ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[C]] + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP7]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32) + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s32), [[COPY4]], [[SUB]] + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s32), [[COPY5]], [[SUB2]] + ; CHECK-NEXT: $x10 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT3]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64) = G_SSUBSAT %0, %1(s64) + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $x10 = COPY %7(s32) + $x11 = COPY %8(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uaddsat_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: uaddsat_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C1]], [[ADD]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8) = G_UADDSAT %0, %1(s8) + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: sshlsat_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: sshlsat_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY1]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[C2]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C]], [[C1]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[ASHR]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[SELECT]], [[SHL]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SSHLSAT %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: sshlsat_i64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: sshlsat_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY2]](s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[SUB1]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY2]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SHL]], [[C1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY1]], [[SELECT1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]] + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SELECT2]], [[COPY2]](s32) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[COPY2]](s32) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SELECT2]], [[SUB1]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL3]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT2]], [[C2]](s32) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SELECT2]], [[SUB]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR1]], [[ASHR2]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[SELECT]], [[SELECT3]] + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[C1]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] + ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]] + ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[ICMP4]], [[ICMP5]] + ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[SELECT6]](s32), [[C1]], [[C4]] + ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[SELECT6]](s32), [[C3]], [[C5]] + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[SELECT4]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[SELECT5]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR2]](s32), [[C1]] + ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s32), [[SELECT7]], [[SELECT]] + ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s32), [[SELECT8]], [[SELECT2]] + ; CHECK-NEXT: $x10 = COPY [[SELECT9]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT10]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64) = G_SSHLSAT %0, %1(s64) + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $x10 = COPY %7(s32) + $x11 = COPY %8(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ushlsat_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ushlsat_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SHL]], [[COPY1]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[LSHR]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C]], [[SHL]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_USHLSAT %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: ushlsat_i64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: ushlsat_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY2]](s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[SUB1]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY2]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SHL]], [[C1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY1]], [[SELECT1]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SELECT2]], [[COPY2]](s32) + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[COPY2]](s32) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SELECT2]], [[SUB1]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL3]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SELECT2]], [[SUB]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR1]], [[LSHR3]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[SELECT]], [[SELECT3]] + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[LSHR1]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[SELECT4]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[SELECT5]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR2]](s32), [[C1]] + ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[C2]], [[SELECT]] + ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[C2]], [[SELECT2]] + ; CHECK-NEXT: $x10 = COPY [[SELECT6]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT7]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $x12 + %5:_(s32) = COPY $x13 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64) = G_USHLSAT %0, %1(s64) + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $x10 = COPY %7(s32) + $x11 = COPY %8(s32) + PseudoRET implicit $x10, implicit $x11 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir new file mode 100644 index 0000000..bd891cc --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir @@ -0,0 +1,475 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV64I +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB + +--- +name: uaddsat_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: uaddsat_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG]](s64) + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[COPY2]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32) = G_UADDSAT %0, %1(s32) + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: uaddsat_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: uaddsat_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), [[COPY1]] + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ADD]](s64) + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[C]], [[COPY2]] + ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: uaddsat_i64 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64ZBB-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[XOR]], [[COPY1]] + ; RV64ZBB-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[UMIN]] + ; RV64ZBB-NEXT: $x10 = COPY [[ADD]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_UADDSAT %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: saddsat_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: saddsat_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[ADD]](s64), [[SEXT_INREG2]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[SEXT_INREG2]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY3]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2147483648 + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]] + ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG3]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[COPY2]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32) = G_SADDSAT %0, %1(s32) + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: saddsat_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: saddsat_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[ADD]](s64), [[COPY]] + ; RV64I-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[COPY1]](s64), [[C]] + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ICMP1]], [[ICMP]] + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ADD]](s64) + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY2]], [[C1]](s64) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808 + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C2]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[XOR]](s64), [[ADD1]], [[COPY2]] + ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: saddsat_i64 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807 + ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808 + ; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[COPY]], [[C2]] + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[SMAX]] + ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[COPY]], [[C2]] + ; RV64ZBB-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C1]], [[SMIN]] + ; RV64ZBB-NEXT: [[SMAX1:%[0-9]+]]:_(s64) = G_SMAX [[SUB1]], [[COPY1]] + ; RV64ZBB-NEXT: [[SMIN1:%[0-9]+]]:_(s64) = G_SMIN [[SMAX1]], [[SUB]] + ; RV64ZBB-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[SMIN1]] + ; RV64ZBB-NEXT: $x10 = COPY [[ADD]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SADDSAT %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: usubsat_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: usubsat_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG]](s64) + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG1]](s64), [[SEXT_INREG2]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[TRUNC]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32) = G_USUBSAT %0, %1(s32) + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: usubsat_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: usubsat_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]] + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[C]], [[SUB]] + ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: usubsat_i64 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[COPY]], [[COPY1]] + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[UMIN]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_USUBSAT %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: ssubsat_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ssubsat_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64) + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[SUB]](s64), [[SEXT_INREG2]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[SEXT_INREG2]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY3]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2147483648 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]] + ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG3]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[COPY2]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32) = G_SSUBSAT %0, %1(s32) + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: ssubsat_i64 +body: | + bb.1: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: ssubsat_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]] + ; RV64I-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SUB]](s64), [[C]] + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ICMP]], [[ICMP1]] + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SUB]](s64) + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY2]], [[C1]](s64) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808 + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C2]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[XOR]](s64), [[ADD]], [[COPY2]] + ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: ssubsat_i64 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807 + ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808 + ; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[COPY]], [[C2]] + ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SMAX]], [[C]] + ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[COPY]], [[C2]] + ; RV64ZBB-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[SMIN]], [[C1]] + ; RV64ZBB-NEXT: [[SMAX1:%[0-9]+]]:_(s64) = G_SMAX [[SUB]], [[COPY1]] + ; RV64ZBB-NEXT: [[SMIN1:%[0-9]+]]:_(s64) = G_SMIN [[SMAX1]], [[SUB1]] + ; RV64ZBB-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[SMIN1]] + ; RV64ZBB-NEXT: $x10 = COPY [[SUB2]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SSUBSAT %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: uaddsat_i8 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: uaddsat_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C1]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s8) = G_TRUNC %3(s64) + %4:_(s8) = G_UADDSAT %0, %1(s8) + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: sshlsat_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: sshlsat_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SLLW]](s64) + ; CHECK-NEXT: [[SRAW:%[0-9]+]]:_(s64) = G_SRAW [[SLLW]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2147483648 + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2147483647 + ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[C1]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SEXT_INREG]](s64), [[C2]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[TRUNC2]] + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SRAW]], 32 + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[SELECT]], [[TRUNC]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT1]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s32) = G_TRUNC %0(s64) + %2:_(s64) = COPY $x11 + %3:_(s32) = G_TRUNC %2(s64) + %4:_(s32) = G_SSHLSAT %1, %3(s32) + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: sshlsat_i64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: sshlsat_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[COPY]](s64), [[C2]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[C]], [[C1]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY]](s64), [[ASHR]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[SELECT]], [[SHL]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SSHLSAT %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: ushlsat_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: ushlsat_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SLLW]](s64) + ; CHECK-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[SLLW]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SRLW]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[TRUNC]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s32) = G_TRUNC %0(s64) + %2:_(s64) = COPY $x11 + %3:_(s32) = G_TRUNC %2(s64) + %4:_(s32) = G_USHLSAT %1, %3(s32) + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: ushlsat_i64 +body: | + bb.1: + liveins: $x10, $x11 + ; CHECK-LABEL: name: ushlsat_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[SHL]], [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[COPY]](s64), [[LSHR]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[C]], [[SHL]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_USHLSAT %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-select-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-select-rv32.mir new file mode 100644 index 0000000..9498c92 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-select-rv32.mir @@ -0,0 +1,219 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: select_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s7) = G_TRUNC %0(s32) + %4:_(s7) = G_TRUNC %1(s32) + %5:_(s1) = G_TRUNC %2(s32) + %6:_(s7) = G_SELECT %5(s1), %3(s7), %4 + %7:_(s32) = G_ANYEXT %6(s7) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 + +... +--- +name: select_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s8) = G_TRUNC %0(s32) + %4:_(s8) = G_TRUNC %1(s32) + %5:_(s1) = G_TRUNC %2(s32) + %6:_(s8) = G_SELECT %5(s1), %3(s8), %4 + %7:_(s32) = G_ANYEXT %6(s8) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 + +... +--- +name: select_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s16) = G_TRUNC %0(s32) + %4:_(s16) = G_TRUNC %1(s32) + %5:_(s1) = G_TRUNC %2(s32) + %6:_(s16) = G_SELECT %5(s1), %3(s16), %4 + %7:_(s32) = G_ANYEXT %6(s16) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 + +... +--- +name: select_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s1) = G_TRUNC %2(s32) + %4:_(s32) = G_SELECT %3(s1), %0(s32), %1(s32) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: select_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i48 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: %c0:_(s32) = COPY $x14 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %c0, [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), %xhi, %yhi + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), %xlo, %ylo + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %c0:_(s32) = COPY $x14 + %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y0:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %c:_(s1) = G_TRUNC %c0(s32) + %z:_(s48) = G_SELECT %c(s1), %x(s48), %y + %z0:_(s64) = G_ANYEXT %z(s48) + %zhi:_(s32), %zlo:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zhi(s32) + $x11 = COPY %zlo(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: select_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i64 + ; CHECK: %xhi:_(s32) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s32) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x13 + ; CHECK-NEXT: %c0:_(s32) = COPY $x14 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %c0, [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), %xhi, %yhi + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), %xlo, %ylo + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xhi:_(s32) = COPY $x10 + %xlo:_(s32) = COPY $x11 + %yhi:_(s32) = COPY $x12 + %ylo:_(s32) = COPY $x13 + %c0:_(s32) = COPY $x14 + %x:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) + %y:_(s64) = G_MERGE_VALUES %yhi(s32), %ylo(s32) + %c:_(s1) = G_TRUNC %c0(s32) + %z:_(s64) = G_SELECT %c(s1), %x(s64), %y + %zhi:_(s32), %zlo:_(s32) = G_UNMERGE_VALUES %z(s64) + $x10 = COPY %zhi(s32) + $x11 = COPY %zlo(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: select_i96 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i96 + ; CHECK: %yhi:_(s32) = COPY $x13 + ; CHECK-NEXT: %ymid:_(s32) = COPY $x14 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x15 + ; CHECK-NEXT: $x10 = COPY %yhi(s32) + ; CHECK-NEXT: $x11 = COPY %ymid(s32) + ; CHECK-NEXT: $x12 = COPY %ylo(s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %xhi:_(s32) = COPY $x10 + %xmid:_(s32) = COPY $x11 + %xlo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %ymid:_(s32) = COPY $x14 + %ylo:_(s32) = COPY $x15 + %c0:_(s32) = COPY $x16 + %x:_(s96) = G_MERGE_VALUES %xhi(s32), %xmid(s32), %xlo(s32) + %y:_(s96) = G_MERGE_VALUES %yhi(s32), %ymid(s32), %ylo(s32) + %c:_(s1) = G_TRUNC %c0(s32) + %z:_(s96) = G_SELECT %c(s1), %x(s96), %y + %zhi:_(s32), %zmid:_(s32), %zlo:_(s32) = G_UNMERGE_VALUES %y(s96) + $x10 = COPY %zhi(s32) + $x11 = COPY %zmid(s32) + $x12 = COPY %zlo(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... +--- +name: select_ptr +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_ptr + ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s1) = G_TRUNC %2(s32) + %4:_(p0) = G_SELECT %3(s1), %0(p0), %1(p0) + $x10 = COPY %4(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-select-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-select-rv64.mir new file mode 100644 index 0000000..7ecb79d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-select-rv64.mir @@ -0,0 +1,256 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: select_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + %3:_(s8) = G_TRUNC %0(s64) + %4:_(s8) = G_TRUNC %1(s64) + %5:_(s1) = G_TRUNC %2(s64) + %6:_(s8) = G_SELECT %5(s1), %3(s8), %4 + %7:_(s64) = G_ANYEXT %6(s8) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: select_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + %3:_(s15) = G_TRUNC %0(s64) + %4:_(s15) = G_TRUNC %1(s64) + %5:_(s1) = G_TRUNC %2(s64) + %6:_(s15) = G_SELECT %5(s1), %3(s15), %4 + %7:_(s64) = G_ANYEXT %6(s15) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: select_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + %3:_(s16) = G_TRUNC %0(s64) + %4:_(s16) = G_TRUNC %1(s64) + %5:_(s1) = G_TRUNC %2(s64) + %6:_(s16) = G_SELECT %5(s1), %3(s16), %4 + %7:_(s64) = G_ANYEXT %6(s16) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: select_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + %3:_(s32) = G_TRUNC %0(s64) + %4:_(s32) = G_TRUNC %1(s64) + %5:_(s1) = G_TRUNC %2(s64) + %6:_(s32) = G_SELECT %5(s1), %3(s32), %4 + %7:_(s64) = G_ANYEXT %6(s32) + $x10 = COPY %7(s64) + PseudoRET implicit $x10 + +... +--- +name: select_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + %3:_(s1) = G_TRUNC %2(s64) + %4:_(s64) = G_SELECT %3(s1), %0(s64), %1(s64) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: select_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i72 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: %c0:_(s64) = COPY $x14 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %c0, [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), %xhi, %yhi + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), %xlo, %ylo + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s64) + ; CHECK-NEXT: $x11 = COPY [[SELECT1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %c0:_(s64) = COPY $x14 + %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y0:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %c:_(s1) = G_TRUNC %c0(s64) + %z:_(s72) = G_SELECT %c(s1), %x(s72), %y + %z0:_(s128) = G_ANYEXT %z(s72) + %zhi:_(s64), %zlo:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %zhi(s64) + $x11 = COPY %zlo(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: select_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i128 + ; CHECK: %xhi:_(s64) = COPY $x10 + ; CHECK-NEXT: %xlo:_(s64) = COPY $x11 + ; CHECK-NEXT: %yhi:_(s64) = COPY $x12 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x13 + ; CHECK-NEXT: %c0:_(s64) = COPY $x14 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %c0, [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), %xhi, %yhi + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), %xlo, %ylo + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s64) + ; CHECK-NEXT: $x11 = COPY [[SELECT1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xhi:_(s64) = COPY $x10 + %xlo:_(s64) = COPY $x11 + %yhi:_(s64) = COPY $x12 + %ylo:_(s64) = COPY $x13 + %c0:_(s64) = COPY $x14 + %x:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) + %y:_(s128) = G_MERGE_VALUES %yhi(s64), %ylo(s64) + %c:_(s1) = G_TRUNC %c0(s64) + %z:_(s128) = G_SELECT %c(s1), %x(s128), %y + %zhi:_(s64), %zlo:_(s64) = G_UNMERGE_VALUES %z(s128) + $x10 = COPY %zhi(s64) + $x11 = COPY %zlo(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: select_i192 +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_i192 + ; CHECK: %yhi:_(s64) = COPY $x13 + ; CHECK-NEXT: %ymid:_(s64) = COPY $x14 + ; CHECK-NEXT: %ylo:_(s64) = COPY $x15 + ; CHECK-NEXT: $x10 = COPY %yhi(s64) + ; CHECK-NEXT: $x11 = COPY %ymid(s64) + ; CHECK-NEXT: $x12 = COPY %ylo(s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %xhi:_(s64) = COPY $x10 + %xmid:_(s64) = COPY $x11 + %xlo:_(s64) = COPY $x12 + %yhi:_(s64) = COPY $x13 + %ymid:_(s64) = COPY $x14 + %ylo:_(s64) = COPY $x15 + %c0:_(s64) = COPY $x16 + %x:_(s192) = G_MERGE_VALUES %xhi(s64), %xmid(s64), %xlo(s64) + %y:_(s192) = G_MERGE_VALUES %yhi(s64), %ymid(s64), %ylo(s64) + %c:_(s1) = G_TRUNC %c0(s64) + %z:_(s192) = G_SELECT %c(s1), %x(s192), %y + %zhi:_(s64), %zmid:_(s64), %zlo:_(s64) = G_UNMERGE_VALUES %y(s192) + $x10 = COPY %zhi(s64) + $x11 = COPY %zmid(s64) + $x12 = COPY %zlo(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... +--- +name: select_ptr +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_ptr + ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s64), [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + %2:_(s64) = COPY $x12 + %3:_(s1) = G_TRUNC %2(s64) + %4:_(p0) = G_SELECT %3(s1), %0(p0), %1(p0) + $x10 = COPY %4(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv32.mir new file mode 100644 index 0000000..8b0728b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv32.mir @@ -0,0 +1,234 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: shl_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_SHL %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: shl_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_SHL %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: shl_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_SHL %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: shl_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SHL %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: shl_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i48 + ; CHECK: %xlo:_(s32) = COPY $x10 + ; CHECK-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %ylo, [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], %ylo + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %ylo(s32), [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %ylo(s32), [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xlo, %ylo(s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %xlo, [[SUB1]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %xhi, %ylo(s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL %xlo, [[SUB]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SHL]], [[C1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %xhi, [[SELECT1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s48) = G_SHL %x, %y + %z0:_(s64) = G_ANYEXT %z(s48) + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: shl_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i64 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], %lo2 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %lo1, %lo2(s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %lo1, [[SUB1]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %hi1, %lo2(s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL %lo1, [[SUB]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SHL]], [[C1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %hi1, [[SELECT1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_SHL %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: shl_i96 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i96 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s32) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], %lo2 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C2]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], %lo2 + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C2]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %lo1, %lo2(s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %lo1, [[SUB3]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %mid1, %lo2(s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL %lo1, [[SUB2]](s32) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[SHL]], [[C1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR]], [[SHL2]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), %mid1, [[SELECT1]] + ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]] + ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR %lo1, [[SUB1]](s32) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL %mid1, [[SUB5]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL3]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %mid1, [[SUB4]](s32) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[OR1]], [[LSHR2]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), %lo1, [[SELECT3]] + ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C2]] + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %hi1, %lo2(s32) + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[SHL4]], [[C1]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT4]], [[SELECT5]] + ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]] + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL %lo1, [[SUB]](s32) + ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s32), [[SHL5]], [[C1]] + ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SELECT]], [[C1]] + ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SELECT2]], [[C1]] + ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR2]], [[SELECT6]] + ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %hi1, [[SELECT9]] + ; CHECK-NEXT: $x10 = COPY [[SELECT7]](s32) + ; CHECK-NEXT: $x11 = COPY [[SELECT8]](s32) + ; CHECK-NEXT: $x12 = COPY [[SELECT10]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s32) = COPY $x10 + %mid1:_(s32) = COPY $x11 + %hi1:_(s32) = COPY $x12 + %lo2:_(s32) = COPY $x13 + %mid2:_(s32) = COPY $x14 + %hi2:_(s32) = COPY $x15 + %x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32) + %x2:_(s96) = G_MERGE_VALUES %lo2(s32), %mid2(s32), %hi2(s32) + %y:_(s96) = G_SHL %x1, %x2 + %lo:_(s32), %mid:_(s32), %hi:_(s32) = G_UNMERGE_VALUES %y(s96) + $x10 = COPY %lo(s32) + $x11 = COPY %mid(s32) + $x12 = COPY %hi(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir new file mode 100644 index 0000000..2ee4520 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir @@ -0,0 +1,280 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: shl_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_SHL %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: shl_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_SHL %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: shl_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_SHL %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: shl_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLLW]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_SHL %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: shl_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SHL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: shl_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i72 + ; CHECK: %x00:_(s64) = COPY $x10 + ; CHECK-NEXT: %x01:_(s64) = COPY $x11 + ; CHECK-NEXT: %y00:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %y00, [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C]], %y00 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %y00(s64), [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %y00(s64), [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %x00, %y00(s64) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR %x00, [[SUB1]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %x01, %y00(s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL %x00, [[SUB]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SHL]], [[C1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR]], [[SHL2]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %x01, [[SELECT1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s64) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %x00:_(s64) = COPY $x10 + %x01:_(s64) = COPY $x11 + %y00:_(s64) = COPY $x12 + %y01:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %x00(s64), %x01 + %y0:_(s128) = G_MERGE_VALUES %y00(s64), %y01 + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s72) = G_SHL %x, %y + %z0:_(s128) = G_ANYEXT %z(s72) + %z00:_(s64), %z01:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %z00(s64) + $x11 = COPY %z01(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: shl_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i128 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C]], %lo2 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %lo1, %lo2(s64) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR %lo1, [[SUB1]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %hi1, %lo2(s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL %lo1, [[SUB]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SHL]], [[C1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR]], [[SHL2]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %hi1, [[SELECT1]] + ; CHECK-NEXT: $x10 = COPY [[SELECT]](s64) + ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_SHL %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: shl_i192 +body: | + bb.0.entry: + ; CHECK-LABEL: name: shl_i192 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s64) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x13 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 128 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C]], %lo2 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C2]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s64) = G_SUB [[C2]], %lo2 + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C2]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %lo1, %lo2(s64) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR %lo1, [[SUB3]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %mid1, %lo2(s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL %lo1, [[SUB2]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s64), [[SHL]], [[C1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s64), [[OR]], [[SHL2]] + ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s64), %mid1, [[SELECT1]] + ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C2]] + ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s64) = G_SUB [[C2]], [[SUB1]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB1]](s64), [[C2]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR %lo1, [[SUB1]](s64) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL %mid1, [[SUB5]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL3]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR %mid1, [[SUB4]](s64) + ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s64), [[OR1]], [[LSHR2]] + ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s64), %lo1, [[SELECT3]] + ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C2]] + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL %hi1, %lo2(s64) + ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s64), [[SHL4]], [[C1]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT5]] + ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB]](s64), [[C2]] + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL %lo1, [[SUB]](s64) + ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s64), [[SHL5]], [[C1]] + ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SELECT]], [[C1]] + ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SELECT2]], [[C1]] + ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR2]], [[SELECT6]] + ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %hi1, [[SELECT9]] + ; CHECK-NEXT: $x10 = COPY [[SELECT7]](s64) + ; CHECK-NEXT: $x11 = COPY [[SELECT8]](s64) + ; CHECK-NEXT: $x12 = COPY [[SELECT10]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s64) = COPY $x10 + %mid1:_(s64) = COPY $x11 + %hi1:_(s64) = COPY $x12 + %lo2:_(s64) = COPY $x13 + %mid2:_(s64) = COPY $x14 + %hi2:_(s64) = COPY $x15 + %x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64) + %x2:_(s192) = G_MERGE_VALUES %lo2(s64), %mid2(s64), %hi2(s64) + %y:_(s192) = G_SHL %x1, %x2 + %lo:_(s64), %mid:_(s64), %hi:_(s64) = G_UNMERGE_VALUES %y(s192) + $x10 = COPY %lo(s64) + $x11 = COPY %mid(s64) + $x12 = COPY %hi(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... +--- +name: shl_i48 +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: shl_i48 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s48) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s48) = G_TRUNC %3(s64) + %4:_(s48) = G_SHL %0, %1(s48) + %5:_(s64) = G_ANYEXT %4(s48) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir new file mode 100644 index 0000000..038d8e4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir @@ -0,0 +1,131 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,RV32I +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB + +--- +name: smax_i8 +body: | + bb.0.entry: + ; RV32I-LABEL: name: smax_i8 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SELECT]], [[C]](s32) + ; RV32I-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; RV32I-NEXT: $x10 = COPY [[ASHR2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: smax_i8 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8 + ; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8 + ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SMAX]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_SMAX %2, %3 + %5:_(s32) = G_SEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 +... + +--- +name: smax_i16 +body: | + bb.0.entry: + ; RV32I-LABEL: name: smax_i16 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SELECT]], [[C]](s32) + ; RV32I-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; RV32I-NEXT: $x10 = COPY [[ASHR2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: smax_i16 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16 + ; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16 + ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SMAX]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_SMAX %2, %3 + %5:_(s32) = G_SEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 +... + +--- +name: smax_i32 +body: | + bb.0.entry: + ; RV32I-LABEL: name: smax_i32 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: smax_i32 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[COPY1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SMAX]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SMAX %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 +... + +--- +name: smax_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: smax_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = COPY $x13 + %4:_(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %5:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %6:_(s64) = G_SMAX %4, %5 + %7:_(s32) = G_TRUNC %6(s64) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv64.mir new file mode 100644 index 0000000..239f7c5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv64.mir @@ -0,0 +1,144 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=RV64I +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=RV64ZBB + +--- +name: smax_i8 +body: | + bb.0.entry: + ; RV64I-LABEL: name: smax_i8 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASHR]](s64), [[ASHR1]] + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s64) + ; RV64I-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; RV64I-NEXT: $x10 = COPY [[ASHR2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: smax_i8 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8 + ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 8 + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]] + ; RV64ZBB-NEXT: $x10 = COPY [[SMAX]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_SMAX %2, %3 + %5:_(s64) = G_SEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: smax_i16 +body: | + bb.0.entry: + ; RV64I-LABEL: name: smax_i16 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASHR]](s64), [[ASHR1]] + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s64) + ; RV64I-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; RV64I-NEXT: $x10 = COPY [[ASHR2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: smax_i16 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 16 + ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 16 + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]] + ; RV64ZBB-NEXT: $x10 = COPY [[SMAX]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_SMAX %2, %3 + %5:_(s64) = G_SEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: smax_i32 +body: | + bb.0.entry: + ; RV64I-LABEL: name: smax_i32 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SELECT]](s32) + ; RV64I-NEXT: $x10 = COPY [[SEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: smax_i32 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]] + ; RV64ZBB-NEXT: $x10 = COPY [[SMAX]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_SMAX %2, %3 + %5:_(s64) = G_SEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: smax_i64 +body: | + bb.0.entry: + ; RV64I-LABEL: name: smax_i64 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: smax_i64 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[COPY]], [[COPY1]] + ; RV64ZBB-NEXT: $x10 = COPY [[SMAX]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SMAX %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir new file mode 100644 index 0000000..631b6eb --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir @@ -0,0 +1,131 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,RV32I +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB + +--- +name: smin_i8 +body: | + bb.0.entry: + ; RV32I-LABEL: name: smin_i8 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SELECT]], [[C]](s32) + ; RV32I-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; RV32I-NEXT: $x10 = COPY [[ASHR2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: smin_i8 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8 + ; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8 + ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SMIN]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_SMIN %2, %3 + %5:_(s32) = G_SEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 +... + +--- +name: smin_i16 +body: | + bb.0.entry: + ; RV32I-LABEL: name: smin_i16 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SELECT]], [[C]](s32) + ; RV32I-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; RV32I-NEXT: $x10 = COPY [[ASHR2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: smin_i16 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16 + ; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16 + ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SMIN]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_SMIN %2, %3 + %5:_(s32) = G_SEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 +... + +--- +name: smin_i32 +body: | + bb.0.entry: + ; RV32I-LABEL: name: smin_i32 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: smin_i32 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[COPY1]] + ; RV32ZBB-NEXT: $x10 = COPY [[SMIN]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SMIN %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 +... + +--- +name: smin_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: smin_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = COPY $x13 + %4:_(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %5:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %6:_(s64) = G_SMIN %4, %5 + %7:_(s32) = G_TRUNC %6(s64) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv64.mir new file mode 100644 index 0000000..ba45113 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv64.mir @@ -0,0 +1,144 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=RV64I +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=RV64ZBB + +--- +name: smin_i8 +body: | + bb.0.entry: + ; RV64I-LABEL: name: smin_i8 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[ASHR]](s64), [[ASHR1]] + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s64) + ; RV64I-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; RV64I-NEXT: $x10 = COPY [[ASHR2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: smin_i8 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8 + ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 8 + ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]] + ; RV64ZBB-NEXT: $x10 = COPY [[SMIN]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_SMIN %2, %3 + %5:_(s64) = G_SEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: smin_i16 +body: | + bb.0.entry: + ; RV64I-LABEL: name: smin_i16 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[ASHR]](s64), [[ASHR1]] + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s64) + ; RV64I-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; RV64I-NEXT: $x10 = COPY [[ASHR2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: smin_i16 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 16 + ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 16 + ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]] + ; RV64ZBB-NEXT: $x10 = COPY [[SMIN]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_SMIN %2, %3 + %5:_(s64) = G_SEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: smin_i32 +body: | + bb.0.entry: + ; RV64I-LABEL: name: smin_i32 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SELECT]](s32) + ; RV64I-NEXT: $x10 = COPY [[SEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: smin_i32 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]] + ; RV64ZBB-NEXT: $x10 = COPY [[SMIN]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_SMIN %2, %3 + %5:_(s64) = G_SEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: smin_i64 +body: | + bb.0.entry: + ; RV64I-LABEL: name: smin_i64 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: smin_i64 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[COPY]], [[COPY1]] + ; RV64ZBB-NEXT: $x10 = COPY [[SMIN]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SMIN %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ssube-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ssube-rv32.mir new file mode 100644 index 0000000..2bad70a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ssube-rv32.mir @@ -0,0 +1,180 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: ssube_i8 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: ssube_i8 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[AND]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SUB1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB1]](s32), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[SUB1]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s8) = G_TRUNC %0(s32) + %2:_(s32) = COPY $x11 + %3:_(s8) = G_TRUNC %2(s32) + %4:_(s32) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s32) + %6:_(s8), %7:_(s1) = G_SSUBE %1, %3, %5 + %8:_(s32) = G_ANYEXT %6(s8) + %9:_(s32) = G_ANYEXT %7(s1) + $x10 = COPY %8(s32) + $x11 = COPY %9(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssube_i16 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: ssube_i16 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[AND]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SUB1]], [[C]](s32) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB1]](s32), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[SUB1]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s16) = G_TRUNC %0(s32) + %2:_(s32) = COPY $x11 + %3:_(s16) = G_TRUNC %2(s32) + %4:_(s32) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s32) + %6:_(s16), %7:_(s1) = G_SSUBE %1, %3, %5 + %8:_(s32) = G_ANYEXT %6(s16) + %9:_(s32) = G_ANYEXT %7(s1) + $x10 = COPY %8(s32) + $x11 = COPY %9(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssube_i32 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: ssube_i32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[AND]] + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[ADD]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[SUB]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[AND1]](s32), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[COPY3]](s32) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s1) = G_TRUNC %2(s32) + %4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3 + %6:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %4(s32) + $x11 = COPY %6(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssube_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: ssube_i64 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C1]] + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[AND]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[AND]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[AND1]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32) + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY5]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY5]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY6]] + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP1]] + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[SUB]] + ; CHECK-NEXT: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[SUB2]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[XOR2]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[XOR3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND2]](s32), [[C1]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[AND3]](s32), [[C1]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND3]](s32), [[C1]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[ICMP2]], [[ICMP3]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: $x11 = COPY [[SUB2]](s32) + ; CHECK-NEXT: $x12 = COPY [[SELECT]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $x12 + %4:_(s32) = COPY $x13 + %5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32) + %6:_(s32) = COPY $x14 + %7:_(s1) = G_TRUNC %6(s32) + %8:_(s64), %9:_(s1) = G_SSUBE %2, %5, %7 + %10:_(s32), %11:_(s32) = G_UNMERGE_VALUES %8(s64) + %12:_(s32) = G_ANYEXT %9(s1) + $x10 = COPY %10(s32) + $x11 = COPY %11(s32) + $x12 = COPY %12(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ssube-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ssube-rv64.mir new file mode 100644 index 0000000..ebde56d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ssube-rv64.mir @@ -0,0 +1,220 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: ssube_i8 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: ssube_i8 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[SUB]], [[AND]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SUB1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[SUB1]](s64), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[SUB1]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s8) = G_TRUNC %0(s64) + %2:_(s64) = COPY $x11 + %3:_(s8) = G_TRUNC %2(s64) + %4:_(s64) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s64) + %6:_(s8), %7:_(s1) = G_SSUBE %1, %3, %5 + %8:_(s64) = G_ANYEXT %6(s8) + %9:_(s64) = G_ANYEXT %7(s1) + $x10 = COPY %8(s64) + $x11 = COPY %9(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssube_i16 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: ssube_i16 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C]](s64) + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASHR]], [[ASHR1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[SUB]], [[AND]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SUB1]], [[C]](s64) + ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[SUB1]](s64), [[ASHR2]] + ; CHECK-NEXT: $x10 = COPY [[SUB1]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s16) = G_TRUNC %0(s64) + %2:_(s64) = COPY $x11 + %3:_(s16) = G_TRUNC %2(s64) + %4:_(s64) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s64) + %6:_(s16), %7:_(s1) = G_SSUBE %1, %3, %5 + %8:_(s64) = G_ANYEXT %6(s16) + %9:_(s64) = G_ANYEXT %7(s1) + $x10 = COPY %8(s64) + $x11 = COPY %9(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssube_i32 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: ssube_i32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[SUB]], [[AND]] + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[SUB1]](s64), [[SEXT_INREG2]] + ; CHECK-NEXT: $x10 = COPY [[SUB1]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s32) = G_TRUNC %0(s64) + %2:_(s64) = COPY $x11 + %3:_(s32) = G_TRUNC %2(s64) + %4:_(s64) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s64) + %6:_(s32), %7:_(s1) = G_SSUBE %1, %3, %5 + %8:_(s64) = G_ANYEXT %6(s32) + %9:_(s64) = G_ANYEXT %7(s1) + $x10 = COPY %8(s64) + $x11 = COPY %9(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssube_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: ssube_i64 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[AND]] + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[ADD]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[SUB]](s64) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[SUB]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[AND1]](s64), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[COPY3]](s64) + ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + %3:_(s1) = G_TRUNC %2(s64) + %4:_(s64), %5:_(s1) = G_SSUBE %0, %1, %3 + %6:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %4(s64) + $x11 = COPY %6(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: ssube_i128 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: ssube_i128 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY4]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]] + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY2]], [[AND]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), [[AND]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY [[ADD]](s64) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[COPY3]], [[AND1]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY [[ADD2]](s64) + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY5]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY5]] + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[COPY1]], [[COPY6]] + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[ICMP1]] + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[SUB]] + ; CHECK-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[COPY1]], [[SUB2]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[XOR2]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[XOR1]], [[XOR3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND2]](s64), [[C1]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[AND3]](s64), [[C1]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND3]](s64), [[C1]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP3]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: $x11 = COPY [[SUB2]](s64) + ; CHECK-NEXT: $x12 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s128) = G_MERGE_VALUES %0(s64), %1(s64) + %3:_(s64) = COPY $x12 + %4:_(s64) = COPY $x13 + %5:_(s128) = G_MERGE_VALUES %3(s64), %4(s64) + %6:_(s64) = COPY $x14 + %7:_(s1) = G_TRUNC %6(s64) + %8:_(s128), %9:_(s1) = G_SSUBE %2, %5, %7 + %10:_(s64), %11:_(s64) = G_UNMERGE_VALUES %8(s128) + %12:_(s64) = G_ANYEXT %9(s1) + $x10 = COPY %10(s64) + $x11 = COPY %11(s64) + $x12 = COPY %12(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir new file mode 100644 index 0000000..cb5db22 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir @@ -0,0 +1,362 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=UNALIGNED + +--- +name: store_i8 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8)) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i8 + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8)) + ; UNALIGNED-NEXT: PseudoRET + %2:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s32) + %1:_(p0) = COPY $x11 + G_STORE %0(s8), %1(p0) :: (store (s8)) + PseudoRET + +... +--- +name: store_i16 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16)) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i16 + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16)) + ; UNALIGNED-NEXT: PseudoRET + %2:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s32) + %1:_(p0) = COPY $x11 + G_STORE %0(s16), %1(p0) :: (store (s16)) + PseudoRET + +... +--- +name: store_i32 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32)) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i32 + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32)) + ; UNALIGNED-NEXT: PseudoRET + %0:_(s32) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %0(s32), %1(p0) :: (store (s32)) + PseudoRET + +... +--- +name: store_i64 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: store_i64 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; CHECK-NEXT: G_STORE [[COPY]](s32), [[COPY2]](p0) :: (store (s32), align 8) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY2]], [[C]](s32) + ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 4) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i64 + ; UNALIGNED: liveins: $x10, $x11, $x12 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; UNALIGNED-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; UNALIGNED-NEXT: G_STORE [[COPY]](s32), [[COPY2]](p0) :: (store (s32), align 8) + ; UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY2]], [[C]](s32) + ; UNALIGNED-NEXT: G_STORE [[COPY1]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 4) + ; UNALIGNED-NEXT: PseudoRET + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %1:_(p0) = COPY $x12 + G_STORE %0(s64), %1(p0) :: (store (s64)) + PseudoRET + +... +--- +name: store_ptr +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_ptr + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: G_STORE [[COPY]](p0), [[COPY1]](p0) :: (store (p0), align 8) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_ptr + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[COPY]](p0), [[COPY1]](p0) :: (store (p0), align 8) + ; UNALIGNED-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %0(p0), %1(p0) :: (store (p0), align 8) + PseudoRET + +... +--- +name: store_i16_unaligned +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i16_unaligned + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s32) + ; CHECK-NEXT: G_STORE [[COPY2]](s16), [[COPY1]](p0) :: (store (s8)) + ; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 1) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i16_unaligned + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16), align 1) + ; UNALIGNED-NEXT: PseudoRET + %2:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s32) + %1:_(p0) = COPY $x11 + G_STORE %0(s16), %1(p0) :: (store (s16), align 1) + PseudoRET + +... +--- +name: store_i32_unaligned +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i32_unaligned + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s32) + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s32) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](s32) + ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8)) + ; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1) + ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[C5]](s32) + ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C4]](s32) + ; CHECK-NEXT: G_STORE [[TRUNC2]](s16), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 2) + ; CHECK-NEXT: G_STORE [[TRUNC3]](s16), [[PTR_ADD2]](p0) :: (store (s8) into unknown-address + 3) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i32_unaligned + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32), align 1) + ; UNALIGNED-NEXT: PseudoRET + %0:_(s32) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %0(s32), %1(p0) :: (store (s32), align 1) + PseudoRET + +... +--- +name: store_i32_align2 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i32_align2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s32) + ; CHECK-NEXT: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store (s16)) + ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 2) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i32_align2 + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32), align 2) + ; UNALIGNED-NEXT: PseudoRET + %0:_(s32) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %0(s32), %1(p0) :: (store (s32), align 2) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir new file mode 100644 index 0000000..7c1ede0 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir @@ -0,0 +1,461 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+unaligned-scalar-mem -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=UNALIGNED + +--- +name: store_i8 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i8 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8)) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i8 + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8)) + ; UNALIGNED-NEXT: PseudoRET + %2:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s64) + %1:_(p0) = COPY $x11 + G_STORE %0(s8), %1(p0) :: (store (s8)) + PseudoRET + +... +--- +name: store_i16 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i16 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16)) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i16 + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16)) + ; UNALIGNED-NEXT: PseudoRET + %2:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s64) + %1:_(p0) = COPY $x11 + G_STORE %0(s16), %1(p0) :: (store (s16)) + PseudoRET + +... +--- +name: store_i32 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s32)) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i32 + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s32)) + ; UNALIGNED-NEXT: PseudoRET + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %1:_(p0) = COPY $x11 + G_STORE %0(s32), %1(p0) :: (store (s32)) + PseudoRET + +... +--- +name: store_i64 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store (s64)) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i64 + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store (s64)) + ; UNALIGNED-NEXT: PseudoRET + %0:_(s64) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %0(s64), %1(p0) :: (store (s64)) + PseudoRET + +... +--- +name: store_i128 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i128 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store (s64)) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i128 + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store (s64)) + ; UNALIGNED-NEXT: PseudoRET + %0:_(s64) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %0(s64), %1(p0) :: (store (s64)) + PseudoRET + +... +--- +name: store_ptr +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_ptr + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: G_STORE [[COPY]](p0), [[COPY1]](p0) :: (store (p0)) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_ptr + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[COPY]](p0), [[COPY1]](p0) :: (store (p0)) + ; UNALIGNED-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %0(p0), %1(p0) :: (store (p0)) + PseudoRET + +... +--- +name: store_i16_unaligned +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i16_unaligned + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64) + ; CHECK-NEXT: G_STORE [[COPY2]](s16), [[COPY1]](p0) :: (store (s8)) + ; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 1) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i16_unaligned + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16), align 1) + ; UNALIGNED-NEXT: PseudoRET + %2:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %2(s64) + %1:_(p0) = COPY $x11 + G_STORE %0(s16), %1(p0) :: (store (s16), align 1) + PseudoRET + +... +--- +name: store_i32_unaligned +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i32_unaligned + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64) + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C4]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C3]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s64) + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C5]](s64) + ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8)) + ; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1) + ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64) + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C4]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C6]](s64) + ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s64) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C5]](s64) + ; CHECK-NEXT: G_STORE [[TRUNC2]](s16), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 2) + ; CHECK-NEXT: G_STORE [[TRUNC3]](s16), [[PTR_ADD2]](p0) :: (store (s8) into unknown-address + 3) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i32_unaligned + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s32), align 1) + ; UNALIGNED-NEXT: PseudoRET + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %1:_(p0) = COPY $x11 + G_STORE %0(s32), %1(p0) :: (store (s32), align 1) + PseudoRET + +... +--- +name: store_i32_align2 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i32_align2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64) + ; CHECK-NEXT: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store (s16)) + ; CHECK-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 2) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i32_align2 + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s32), align 2) + ; UNALIGNED-NEXT: PseudoRET + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %1:_(p0) = COPY $x11 + G_STORE %0(s32), %1(p0) :: (store (s32), align 2) + PseudoRET + +... +--- +name: store_i64_align2 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_i64_align2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY2]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64) + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C3]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C2]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](s64) + ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s16)) + ; CHECK-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD1]](p0) :: (store (s16) into unknown-address + 2) + ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64) + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[C5]](s64) + ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR2]](s64) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C4]](s64) + ; CHECK-NEXT: G_STORE [[TRUNC2]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 4) + ; CHECK-NEXT: G_STORE [[TRUNC3]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 6) + ; CHECK-NEXT: PseudoRET + ; + ; UNALIGNED-LABEL: name: store_i64_align2 + ; UNALIGNED: liveins: $x10, $x11 + ; UNALIGNED-NEXT: {{ $}} + ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; UNALIGNED-NEXT: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store (s64), align 2) + ; UNALIGNED-NEXT: PseudoRET + %0:_(s64) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %0(s64), %1(p0) :: (store (s64), align 2) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv32.mir new file mode 100644 index 0000000..258d026 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv32.mir @@ -0,0 +1,183 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: sub_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_SUB %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: sub_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_SUB %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: sub_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_SUB %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: sub_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SUB %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: sub_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i48 + ; CHECK: %xlo:_(s32) = COPY $x10 + ; CHECK-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %xlo, %ylo + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xlo(s32), %ylo + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB %xhi, %yhi + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: $x11 = COPY [[SUB2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s48) = G_SUB %x, %y + %z0:_(s64) = G_ANYEXT %z(s48) + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sub_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i64 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %lo1, %lo2 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo1(s32), %lo2 + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB %hi1, %hi2 + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: $x11 = COPY [[SUB2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_SUB %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sub_i96 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i96 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s32) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x13 + ; CHECK-NEXT: %mid2:_(s32) = COPY $x14 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x15 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %lo1, %lo2 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo1(s32), %lo2 + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB %mid1, %mid2 + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[SUB1]](s32), %mid1 + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB %hi1, %hi2 + ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[OR]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: $x11 = COPY [[SUB2]](s32) + ; CHECK-NEXT: $x12 = COPY [[SUB4]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s32) = COPY $x10 + %mid1:_(s32) = COPY $x11 + %hi1:_(s32) = COPY $x12 + %lo2:_(s32) = COPY $x13 + %mid2:_(s32) = COPY $x14 + %hi2:_(s32) = COPY $x15 + %x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32) + %x2:_(s96) = G_MERGE_VALUES %lo2(s32), %mid2(s32), %hi2(s32) + %y:_(s96) = G_SUB %x1, %x2 + %lo:_(s32), %mid:_(s32), %hi:_(s32) = G_UNMERGE_VALUES %y(s96) + $x10 = COPY %lo(s32) + $x11 = COPY %mid(s32) + $x12 = COPY %hi(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir new file mode 100644 index 0000000..7ab07ee --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir @@ -0,0 +1,204 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: sub_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_SUB %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: sub_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_SUB %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: sub_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_SUB %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: sub_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_SUB %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: sub_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SUB %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sub_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i72 + ; CHECK: %x00:_(s64) = COPY $x10 + ; CHECK-NEXT: %x01:_(s64) = COPY $x11 + ; CHECK-NEXT: %y00:_(s64) = COPY $x12 + ; CHECK-NEXT: %y01:_(s64) = COPY $x13 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %x00, %y00 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %x00(s64), %y00 + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB %x01, %y01 + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[ICMP]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: $x11 = COPY [[SUB2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %x00:_(s64) = COPY $x10 + %x01:_(s64) = COPY $x11 + %y00:_(s64) = COPY $x12 + %y01:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %x00(s64), %x01 + %y0:_(s128) = G_MERGE_VALUES %y00(s64), %y01 + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s72) = G_SUB %x, %y + %z0:_(s128) = G_ANYEXT %z(s72) + %z00:_(s64), %z01:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %z00(s64) + $x11 = COPY %z01(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sub_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i128 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %lo1, %lo2 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo1(s64), %lo2 + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB %hi1, %hi2 + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[ICMP]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: $x11 = COPY [[SUB2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_SUB %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: sub_i192 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sub_i192 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s64) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x13 + ; CHECK-NEXT: %mid2:_(s64) = COPY $x14 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x15 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %lo1, %lo2 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo1(s64), %lo2 + ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB %mid1, %mid2 + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SUB1]](s64), %mid1 + ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP2]], [[ICMP]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ICMP1]], [[AND]] + ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s64) = G_SUB %hi1, %hi2 + ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB [[SUB3]], [[OR]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: $x11 = COPY [[SUB2]](s64) + ; CHECK-NEXT: $x12 = COPY [[SUB4]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s64) = COPY $x10 + %mid1:_(s64) = COPY $x11 + %hi1:_(s64) = COPY $x12 + %lo2:_(s64) = COPY $x13 + %mid2:_(s64) = COPY $x14 + %hi2:_(s64) = COPY $x15 + %x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64) + %x2:_(s192) = G_MERGE_VALUES %lo2(s64), %mid2(s64), %hi2(s64) + %y:_(s192) = G_SUB %x1, %x2 + %lo:_(s64), %mid:_(s64), %hi:_(s64) = G_UNMERGE_VALUES %y(s192) + $x10 = COPY %lo(s64) + $x11 = COPY %mid(s64) + $x12 = COPY %hi(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv32.mir new file mode 100644 index 0000000..4ffca79 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv32.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: test_ucmp_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: test_ucmp_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SCMP %0(s32), %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: test_scmp_i32 +alignment: 4 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: test_scmp_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: $x10 = COPY [[SUB]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SCMP %0(s32), %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv64.mir new file mode 100644 index 0000000..9e60a76 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv64.mir @@ -0,0 +1,61 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: test_ucmp_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: test_ucmp_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32) = G_SCMP %0(s32), %1 + %5:_(s64) = G_SEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: test_scmp_i32 +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: test_scmp_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %4:_(s32) = G_SCMP %0(s32), %1 + %5:_(s64) = G_SEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-uadde-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-uadde-rv32.mir new file mode 100644 index 0000000..6e978ce --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-uadde-rv32.mir @@ -0,0 +1,184 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: uadde_i8 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: uadde_i8 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND2]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND3]](s32), [[C2]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[COPY2]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP]], [[AND4]] + ; CHECK-NEXT: $x10 = COPY [[ADD1]](s32) + ; CHECK-NEXT: $x11 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s8) = G_TRUNC %0(s32) + %2:_(s32) = COPY $x11 + %3:_(s8) = G_TRUNC %2(s32) + %4:_(s32) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s32) + %6:_(s8), %7:_(s1) = G_UADDE %1, %3, %5 + %8:_(s32) = G_ANYEXT %6(s8) + %9:_(s32) = G_ANYEXT %7(s1) + $x10 = COPY %8(s32) + $x11 = COPY %9(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uadde_i16 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: uadde_i16 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND2]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND3]](s32), [[C2]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[COPY2]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP]], [[AND4]] + ; CHECK-NEXT: $x10 = COPY [[ADD1]](s32) + ; CHECK-NEXT: $x11 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s16) = G_TRUNC %0(s32) + %2:_(s32) = COPY $x11 + %3:_(s16) = G_TRUNC %2(s32) + %4:_(s32) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s32) + %6:_(s16), %7:_(s1) = G_UADDE %1, %3, %5 + %8:_(s32) = G_ANYEXT %6(s16) + %9:_(s32) = G_ANYEXT %7(s1) + $x10 = COPY %8(s32) + $x11 = COPY %9(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uadde_i32 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: uadde_i32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD1]](s32), [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[COPY2]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP]], [[AND1]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32) + ; CHECK-NEXT: $x10 = COPY [[COPY3]](s32) + ; CHECK-NEXT: $x11 = COPY [[OR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s1) = G_TRUNC %2(s32) + %4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3 + %6:_(s32) = G_ANYEXT %5(s1) + $x10 = COPY %4(s32) + $x11 = COPY %6(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uadde_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: uadde_i64 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY2]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32) + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY5]](s32), [[COPY]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY6]](s32), [[COPY1]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY6]](s32), [[COPY1]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]] + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]] + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[COPY5]], [[AND]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[AND]] + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD3]](s32) + ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[AND1]] + ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ICMP4]] + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD5]](s32) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY7]], [[C]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY8]], [[C]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP5]], [[COPY4]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[AND2]] + ; CHECK-NEXT: $x10 = COPY [[COPY7]](s32) + ; CHECK-NEXT: $x11 = COPY [[COPY8]](s32) + ; CHECK-NEXT: $x12 = COPY [[OR1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = COPY $x13 + %4:_(s32) = COPY $x14 + %5:_(s64) = G_MERGE_VALUES %0, %1 + %6:_(s64) = G_MERGE_VALUES %2, %3 + %7:_(s1) = G_TRUNC %4(s32) + %8:_(s64), %9:_(s1) = G_UADDE %5, %6, %7 + %10:_(s32), %11:_(s32) = G_UNMERGE_VALUES %8 + %12:_(s32) = G_ANYEXT %9(s1) + $x10 = COPY %10(s32) + $x11 = COPY %11(s32) + $x12 = COPY %12(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-uadde-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-uadde-rv64.mir new file mode 100644 index 0000000..1d5ab4e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-uadde-rv64.mir @@ -0,0 +1,228 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: uadde_i8 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: uadde_i8 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[AND2]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND3]](s64), [[C2]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[COPY2]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ICMP]], [[AND4]] + ; CHECK-NEXT: $x10 = COPY [[ADD1]](s64) + ; CHECK-NEXT: $x11 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s8) = G_TRUNC %0(s64) + %2:_(s64) = COPY $x11 + %3:_(s8) = G_TRUNC %2(s64) + %4:_(s64) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s64) + %6:_(s8), %7:_(s1) = G_UADDE %1, %3, %5 + %8:_(s64) = G_ANYEXT %6(s8) + %9:_(s64) = G_ANYEXT %7(s1) + $x10 = COPY %8(s64) + $x11 = COPY %9(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uadde_i16 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: uadde_i16 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND1]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[AND2]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND3]](s64), [[C2]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[COPY2]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ICMP]], [[AND4]] + ; CHECK-NEXT: $x10 = COPY [[ADD1]](s64) + ; CHECK-NEXT: $x11 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s16) = G_TRUNC %0(s64) + %2:_(s64) = COPY $x11 + %3:_(s16) = G_TRUNC %2(s64) + %4:_(s64) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s64) + %6:_(s16), %7:_(s1) = G_UADDE %1, %3, %5 + %8:_(s64) = G_ANYEXT %6(s16) + %9:_(s64) = G_ANYEXT %7(s1) + $x10 = COPY %8(s64) + $x11 = COPY %9(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uadde_i32 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: uadde_i32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[SEXT_INREG]], [[AND]] + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SEXT_INREG2]](s64), [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[COPY2]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ICMP]], [[AND1]] + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG2]](s64) + ; CHECK-NEXT: $x11 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s32) = G_TRUNC %0(s64) + %2:_(s64) = COPY $x11 + %3:_(s32) = G_TRUNC %2(s64) + %4:_(s64) = COPY $x12 + %5:_(s1) = G_TRUNC %4(s64) + %6:_(s32), %7:_(s1) = G_UADDE %1, %3, %5 + %8:_(s64) = G_ANYEXT %6(s32) + %9:_(s64) = G_ANYEXT %7(s1) + $x10 = COPY %8(s64) + $x11 = COPY %9(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uadde_i64 +body: | + bb.1: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: uadde_i64 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), [[COPY]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[AND]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ADD1]](s64), [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[COPY2]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ICMP]], [[AND1]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[ADD1]](s64) + ; CHECK-NEXT: $x10 = COPY [[COPY3]](s64) + ; CHECK-NEXT: $x11 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + %3:_(s1) = G_TRUNC %2(s64) + %4:_(s64), %5:_(s1) = G_UADDE %0, %1, %3 + %6:_(s64) = G_ANYEXT %5(s1) + $x10 = COPY %4(s64) + $x11 = COPY %6(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: uadde_i128 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; CHECK-LABEL: name: uadde_i128 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), [[COPY2]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY [[ADD]](s64) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[COPY3]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[ICMP]] + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY [[ADD2]](s64) + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[COPY5]](s64), [[COPY]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[COPY6]](s64), [[COPY1]] + ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[COPY6]](s64), [[COPY1]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP1]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ICMP2]](s64) + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s64), [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY4]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]] + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s64) = G_ADD [[COPY5]], [[AND]] + ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD3]](s64), [[AND]] + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY [[ADD3]](s64) + ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s64) = G_ADD [[COPY6]], [[AND1]] + ; CHECK-NEXT: [[ADD5:%[0-9]+]]:_(s64) = G_ADD [[ADD4]], [[ICMP4]] + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY [[ADD5]](s64) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY7]], [[C]] + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[COPY8]], [[C]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]] + ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[OR]](s64), [[C]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ICMP5]], [[COPY4]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[ANYEXT]], [[AND2]] + ; CHECK-NEXT: $x10 = COPY [[COPY7]](s64) + ; CHECK-NEXT: $x11 = COPY [[COPY8]](s64) + ; CHECK-NEXT: $x12 = COPY [[OR1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + %3:_(s64) = COPY $x13 + %4:_(s64) = COPY $x14 + %5:_(s128) = G_MERGE_VALUES %0, %1 + %6:_(s128) = G_MERGE_VALUES %2, %3 + %7:_(s1) = G_TRUNC %4(s64) + %8:_(s128), %9:_(s1) = G_UADDE %5, %6, %7 + %10:_(s64), %11:_(s64) = G_UNMERGE_VALUES %8 + %12:_(s64) = G_ANYEXT %9(s1) + $x10 = COPY %10(s64) + $x11 = COPY %11(s64) + $x12 = COPY %12(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv32.mir new file mode 100644 index 0000000..83ba02b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv32.mir @@ -0,0 +1,127 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,RV32I +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB + +--- +name: umax_i8 +body: | + bb.0.entry: + ; RV32I-LABEL: name: umax_i8 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[AND1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C]] + ; RV32I-NEXT: $x10 = COPY [[AND2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: umax_i8 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]] + ; RV32ZBB-NEXT: $x10 = COPY [[UMAX]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_UMAX %2, %3 + %5:_(s32) = G_ZEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 +... + +--- +name: umax_i16 +body: | + bb.0.entry: + ; RV32I-LABEL: name: umax_i16 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[AND1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C]] + ; RV32I-NEXT: $x10 = COPY [[AND2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: umax_i16 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]] + ; RV32ZBB-NEXT: $x10 = COPY [[UMAX]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_UMAX %2, %3 + %5:_(s32) = G_ZEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 +... + +--- +name: umax_i32 +body: | + bb.0.entry: + ; RV32I-LABEL: name: umax_i32 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: umax_i32 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]] + ; RV32ZBB-NEXT: $x10 = COPY [[UMAX]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_UMAX %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 +... + +--- +name: umax_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: umax_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = COPY $x13 + %4:_(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %5:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %6:_(s64) = G_UMAX %4, %5 + %7:_(s32) = G_TRUNC %6(s64) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir new file mode 100644 index 0000000..afef788 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir @@ -0,0 +1,142 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=RV64I +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=RV64ZBB + +--- +name: umax_i8 +body: | + bb.0.entry: + ; RV64I-LABEL: name: umax_i8 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND]](s64), [[AND1]] + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]] + ; RV64I-NEXT: $x10 = COPY [[AND2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: umax_i8 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[AND]], [[AND1]] + ; RV64ZBB-NEXT: $x10 = COPY [[UMAX]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_UMAX %2, %3 + %5:_(s64) = G_ZEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: umax_i16 +body: | + bb.0.entry: + ; RV64I-LABEL: name: umax_i16 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND]](s64), [[AND1]] + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]] + ; RV64I-NEXT: $x10 = COPY [[AND2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: umax_i16 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[AND]], [[AND1]] + ; RV64ZBB-NEXT: $x10 = COPY [[UMAX]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_UMAX %2, %3 + %5:_(s64) = G_ZEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: umax_i32 +body: | + bb.0.entry: + ; RV64I-LABEL: name: umax_i32 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SELECT]](s32) + ; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: umax_i32 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[SEXT_INREG]], [[SEXT_INREG1]] + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UMAX]], [[C]] + ; RV64ZBB-NEXT: $x10 = COPY [[AND]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_UMAX %2, %3 + %5:_(s64) = G_ZEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: umax_i64 +body: | + bb.0.entry: + ; RV64I-LABEL: name: umax_i64 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: umax_i64 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[COPY]], [[COPY1]] + ; RV64ZBB-NEXT: $x10 = COPY [[UMAX]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_UMAX %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv32.mir new file mode 100644 index 0000000..1c92dcf --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv32.mir @@ -0,0 +1,127 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,RV32I +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB + +--- +name: umin_i8 +body: | + bb.0.entry: + ; RV32I-LABEL: name: umin_i8 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C]] + ; RV32I-NEXT: $x10 = COPY [[AND2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: umin_i8 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]] + ; RV32ZBB-NEXT: $x10 = COPY [[UMIN]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_UMIN %2, %3 + %5:_(s32) = G_ZEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 +... + +--- +name: umin_i16 +body: | + bb.0.entry: + ; RV32I-LABEL: name: umin_i16 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C]] + ; RV32I-NEXT: $x10 = COPY [[AND2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: umin_i16 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32ZBB-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]] + ; RV32ZBB-NEXT: $x10 = COPY [[UMIN]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_UMIN %2, %3 + %5:_(s32) = G_ZEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 +... + +--- +name: umin_i32 +body: | + bb.0.entry: + ; RV32I-LABEL: name: umin_i32 + ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: umin_i32 + ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]] + ; RV32ZBB-NEXT: $x10 = COPY [[UMIN]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_UMIN %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 +... + +--- +name: umin_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: umin_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]] + ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = COPY $x13 + %4:_(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %5:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %6:_(s64) = G_UMIN %4, %5 + %7:_(s32) = G_TRUNC %6(s64) + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir new file mode 100644 index 0000000..36a8ccb --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir @@ -0,0 +1,142 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=RV64I +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=RV64ZBB + +--- +name: umin_i8 +body: | + bb.0.entry: + ; RV64I-LABEL: name: umin_i8 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND1]] + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]] + ; RV64I-NEXT: $x10 = COPY [[AND2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: umin_i8 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[AND]], [[AND1]] + ; RV64ZBB-NEXT: $x10 = COPY [[UMIN]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_UMIN %2, %3 + %5:_(s64) = G_ZEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: umin_i16 +body: | + bb.0.entry: + ; RV64I-LABEL: name: umin_i16 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND1]] + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]] + ; RV64I-NEXT: $x10 = COPY [[AND2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: umin_i16 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; RV64ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[AND]], [[AND1]] + ; RV64ZBB-NEXT: $x10 = COPY [[UMIN]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_UMIN %2, %3 + %5:_(s64) = G_ZEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: umin_i32 +body: | + bb.0.entry: + ; RV64I-LABEL: name: umin_i32 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]] + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SELECT]](s32) + ; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: umin_i32 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[SEXT_INREG]], [[SEXT_INREG1]] + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UMIN]], [[C]] + ; RV64ZBB-NEXT: $x10 = COPY [[AND]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_UMIN %2, %3 + %5:_(s64) = G_ZEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 +... + +--- +name: umin_i64 +body: | + bb.0.entry: + ; RV64I-LABEL: name: umin_i64 + ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: umin_i64 + ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[COPY]], [[COPY1]] + ; RV64ZBB-NEXT: $x10 = COPY [[UMIN]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_UMIN %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vaarg-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vaarg-rv32.mir new file mode 100644 index 0000000..b67691d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vaarg-rv32.mir @@ -0,0 +1,70 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s + +# On RISC-V, the MinStackArgumentAlignment is 1 and the ABI Alignment for p0 is +# greater than 1, so we will always generate code to adjust for this alignment. + +--- +name: va_arg_i32 +legalized: false +tracksRegLiveness: true +fixedStack: + - { id: 0, type: default, offset: 0, size: 4, alignment: 16, + isImmutable: true, isAliased: false } +stack: + - { id: 0, type: default, offset: 0, size: 4, alignment: 4 } +machineFunctionInfo: + varArgsFrameIndex: -1 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; CHECK-LABEL: name: va_arg_i32 + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4 + ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD]], [[C1]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C2]](s32) + ; CHECK-NEXT: G_STORE [[PTR_ADD1]](p0), [[FRAME_INDEX]](p0) :: (store (p0)) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = G_FRAME_INDEX %stack.0 + %1:_(s32) = G_VAARG %0(p0), 4 + PseudoRET +... +--- +name: va_arg_ptr +legalized: false +tracksRegLiveness: true +fixedStack: + - { id: 0, type: default, offset: 0, size: 4, alignment: 16, + isImmutable: true, isAliased: false } +stack: + - { id: 0, type: default, offset: 0, size: 4, alignment: 4 } +machineFunctionInfo: + varArgsFrameIndex: -1 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; CHECK-LABEL: name: va_arg_ptr + ; CHECK: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4 + ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD]], [[C1]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C2]](s32) + ; CHECK-NEXT: G_STORE [[PTR_ADD1]](p0), [[FRAME_INDEX]](p0) :: (store (p0)) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = G_FRAME_INDEX %stack.0 + %1:_(p0) = G_VAARG %0(p0), 4 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vaarg-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vaarg-rv64.mir new file mode 100644 index 0000000..8b0f091 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vaarg-rv64.mir @@ -0,0 +1,64 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s + +# On RISC-V, the MinStackArgumentAlignment is 1 and the ABI Alignment for p0 is +# greater than 1, so we will always generate code to adjust for this alignment. + +--- +name: va_arg_i64 +legalized: false +tracksRegLiveness: true +fixedStack: + - { id: 0, type: default, offset: 0, size: 8, alignment: 16, + isImmutable: true, isAliased: false } +stack: + - { id: 0, type: default, offset: 0, size: 8, alignment: 8 } +machineFunctionInfo: + varArgsFrameIndex: -1 + varArgsSaveSize: 0 +body: | + bb.1: + ; CHECK-LABEL: name: va_arg_i64 + ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4 + ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD]], [[C1]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C2]](s64) + ; CHECK-NEXT: G_STORE [[PTR_ADD1]](p0), [[FRAME_INDEX]](p0) :: (store (p0)) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = G_FRAME_INDEX %stack.0 + %1:_(s64) = G_VAARG %0(p0), 4 + PseudoRET +... +--- +name: va_arg_ptr +legalized: false +tracksRegLiveness: true +fixedStack: + - { id: 0, type: default, offset: 0, size: 8, alignment: 16, + isImmutable: true, isAliased: false } +stack: + - { id: 0, type: default, offset: 0, size: 8, alignment: 8 } +machineFunctionInfo: + varArgsFrameIndex: -1 + varArgsSaveSize: 0 +body: | + bb.1: + ; CHECK-LABEL: name: va_arg_ptr + ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0)) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4 + ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD]], [[C1]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C2]](s64) + ; CHECK-NEXT: G_STORE [[PTR_ADD1]](p0), [[FRAME_INDEX]](p0) :: (store (p0)) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = G_FRAME_INDEX %stack.0 + %1:_(s64) = G_VAARG %0(p0), 4 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vacopy.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vacopy.mir new file mode 100644 index 0000000..16542f5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vacopy.mir @@ -0,0 +1,23 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: test_va_copy +body: | + bb.1: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: test_va_copy + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY1]](p0) :: (load (p0)) + ; CHECK-NEXT: G_STORE [[LOAD]](p0), [[COPY]](p0) :: (store (p0)) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), %0(p0), %1(p0) + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vastart-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vastart-rv32.mir new file mode 100644 index 0000000..181aa9c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vastart-rv32.mir @@ -0,0 +1,29 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV32 %s + +--- +name: test_va_start +tracksRegLiveness: true +fixedStack: + - { id: 0, size: 4, alignment: 16, isImmutable: true } +stack: + - { id: 0, size: 4, alignment: 4 } +machineFunctionInfo: + varArgsFrameIndex: -1 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + + ; RV32-LABEL: name: test_va_start + ; RV32: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 + ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32-NEXT: G_STORE [[FRAME_INDEX1]](p0), [[FRAME_INDEX]](p0) :: (store (s32)) + ; RV32-NEXT: PseudoRET + %8:_(p0) = G_FRAME_INDEX %stack.0 + G_VASTART %8(p0) :: (store (s32)) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vastart-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vastart-rv64.mir new file mode 100644 index 0000000..60babc8 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-vastart-rv64.mir @@ -0,0 +1,29 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV64 %s + +--- +name: test_va_start +tracksRegLiveness: true +fixedStack: + - { id: 0, size: 8, alignment: 16, isImmutable: true } +stack: + - { id: 0, size: 8, alignment: 8 } +machineFunctionInfo: + varArgsFrameIndex: -1 + varArgsSaveSize: 0 +body: | + bb.1: + liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + + ; RV64-LABEL: name: test_va_start + ; RV64: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 + ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV64-NEXT: G_STORE [[FRAME_INDEX1]](p0), [[FRAME_INDEX]](p0) :: (store (s64)) + ; RV64-NEXT: PseudoRET + %8:_(p0) = G_FRAME_INDEX %stack.0 + G_VASTART %8(p0) :: (store (s64)) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-xor-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-xor-rv32.mir new file mode 100644 index 0000000..c0ba3e9 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-xor-rv32.mir @@ -0,0 +1,171 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: xor_i7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i7 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[XOR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s7) = G_TRUNC %0(s32) + %3:_(s7) = G_TRUNC %1(s32) + %4:_(s7) = G_XOR %2, %3 + %5:_(s32) = G_ANYEXT %4(s7) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: xor_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[XOR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s32) + %3:_(s8) = G_TRUNC %1(s32) + %4:_(s8) = G_XOR %2, %3 + %5:_(s32) = G_ANYEXT %4(s8) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: xor_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[XOR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s32) + %3:_(s16) = G_TRUNC %1(s32) + %4:_(s16) = G_XOR %2, %3 + %5:_(s32) = G_ANYEXT %4(s16) + $x10 = COPY %5(s32) + PseudoRET implicit $x10 + +... +--- +name: xor_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[XOR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_XOR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: xor_i48 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i48 + ; CHECK: %xlo:_(s32) = COPY $x10 + ; CHECK-NEXT: %xhi:_(s32) = COPY $x11 + ; CHECK-NEXT: %ylo:_(s32) = COPY $x12 + ; CHECK-NEXT: %yhi:_(s32) = COPY $x13 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR %xlo, %ylo + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR %xhi, %yhi + ; CHECK-NEXT: $x10 = COPY [[XOR]](s32) + ; CHECK-NEXT: $x11 = COPY [[XOR1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %xlo:_(s32) = COPY $x10 + %xhi:_(s32) = COPY $x11 + %ylo:_(s32) = COPY $x12 + %yhi:_(s32) = COPY $x13 + %x0:_(s64) = G_MERGE_VALUES %xlo(s32), %xhi(s32) + %y0:_(s64) = G_MERGE_VALUES %ylo(s32), %yhi(s32) + %x:_(s48) = G_TRUNC %x0(s64) + %y:_(s48) = G_TRUNC %y0(s64) + %z:_(s48) = G_XOR %x, %y + %z0:_(s64) = G_ANYEXT %z(s48) + %zlo:_(s32), %zhi:_(s32) = G_UNMERGE_VALUES %z0(s64) + $x10 = COPY %zlo(s32) + $x11 = COPY %zhi(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: xor_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i64 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x13 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR %lo1, %lo2 + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR %hi1, %hi2 + ; CHECK-NEXT: $x10 = COPY [[XOR]](s32) + ; CHECK-NEXT: $x11 = COPY [[XOR1]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s32) = COPY $x10 + %hi1:_(s32) = COPY $x11 + %lo2:_(s32) = COPY $x12 + %hi2:_(s32) = COPY $x13 + %x1:_(s64) = G_MERGE_VALUES %lo1(s32), %hi1(s32) + %x2:_(s64) = G_MERGE_VALUES %lo2(s32), %hi2(s32) + %y:_(s64) = G_XOR %x1, %x2 + %loy:_(s32), %hiy:_(s32) = G_UNMERGE_VALUES %y(s64) + $x10 = COPY %loy(s32) + $x11 = COPY %hiy(s32) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: xor_i96 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i96 + ; CHECK: %lo1:_(s32) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s32) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s32) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s32) = COPY $x13 + ; CHECK-NEXT: %mid2:_(s32) = COPY $x14 + ; CHECK-NEXT: %hi2:_(s32) = COPY $x15 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR %lo1, %lo2 + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR %mid1, %mid2 + ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s32) = G_XOR %hi1, %hi2 + ; CHECK-NEXT: $x10 = COPY [[XOR]](s32) + ; CHECK-NEXT: $x11 = COPY [[XOR1]](s32) + ; CHECK-NEXT: $x12 = COPY [[XOR2]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s32) = COPY $x10 + %mid1:_(s32) = COPY $x11 + %hi1:_(s32) = COPY $x12 + %lo2:_(s32) = COPY $x13 + %mid2:_(s32) = COPY $x14 + %hi2:_(s32) = COPY $x15 + %x1:_(s96) = G_MERGE_VALUES %lo1(s32), %mid1(s32), %hi1(s32) + %x2:_(s96) = G_MERGE_VALUES %lo2(s32), %mid2(s32), %hi2(s32) + %y:_(s96) = G_XOR %x1, %x2 + %lo:_(s32), %mid:_(s32), %hi:_(s32) = G_UNMERGE_VALUES %y(s96) + $x10 = COPY %lo(s32) + $x11 = COPY %mid(s32) + $x12 = COPY %hi(s32) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-xor-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-xor-rv64.mir new file mode 100644 index 0000000..80081bd --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-xor-rv64.mir @@ -0,0 +1,191 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: xor_i8 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i8 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[XOR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s8) = G_TRUNC %0(s64) + %3:_(s8) = G_TRUNC %1(s64) + %4:_(s8) = G_XOR %2, %3 + %5:_(s64) = G_ANYEXT %4(s8) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: xor_i15 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i15 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[XOR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s15) = G_TRUNC %0(s64) + %3:_(s15) = G_TRUNC %1(s64) + %4:_(s15) = G_XOR %2, %3 + %5:_(s64) = G_ANYEXT %4(s15) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: xor_i16 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i16 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[XOR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s16) = G_TRUNC %0(s64) + %3:_(s16) = G_TRUNC %1(s64) + %4:_(s16) = G_XOR %2, %3 + %5:_(s64) = G_ANYEXT %4(s16) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: xor_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[XOR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_XOR %2, %3 + %5:_(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: xor_i64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[XOR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_XOR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: xor_i72 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i72 + ; CHECK: %x00:_(s64) = COPY $x10 + ; CHECK-NEXT: %x01:_(s64) = COPY $x11 + ; CHECK-NEXT: %y00:_(s64) = COPY $x12 + ; CHECK-NEXT: %y01:_(s64) = COPY $x13 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR %x00, %y00 + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR %x01, %y01 + ; CHECK-NEXT: $x10 = COPY [[XOR]](s64) + ; CHECK-NEXT: $x11 = COPY [[XOR1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %x00:_(s64) = COPY $x10 + %x01:_(s64) = COPY $x11 + %y00:_(s64) = COPY $x12 + %y01:_(s64) = COPY $x13 + %x0:_(s128) = G_MERGE_VALUES %x00(s64), %x01 + %y0:_(s128) = G_MERGE_VALUES %y00(s64), %y01 + %x:_(s72) = G_TRUNC %x0(s128) + %y:_(s72) = G_TRUNC %y0(s128) + %z:_(s72) = G_XOR %x, %y + %z0:_(s128) = G_ANYEXT %z(s72) + %z00:_(s64), %z01:_(s64) = G_UNMERGE_VALUES %z0(s128) + $x10 = COPY %z00(s64) + $x11 = COPY %z01(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: xor_i128 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i128 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x11 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x12 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x13 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR %lo1, %lo2 + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR %hi1, %hi2 + ; CHECK-NEXT: $x10 = COPY [[XOR]](s64) + ; CHECK-NEXT: $x11 = COPY [[XOR1]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %lo1:_(s64) = COPY $x10 + %hi1:_(s64) = COPY $x11 + %lo2:_(s64) = COPY $x12 + %hi2:_(s64) = COPY $x13 + %x1:_(s128) = G_MERGE_VALUES %lo1(s64), %hi1(s64) + %x2:_(s128) = G_MERGE_VALUES %lo2(s64), %hi2(s64) + %y:_(s128) = G_XOR %x1, %x2 + %loy:_(s64), %hiy:_(s64) = G_UNMERGE_VALUES %y(s128) + $x10 = COPY %loy(s64) + $x11 = COPY %hiy(s64) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: xor_i192 +body: | + bb.0.entry: + ; CHECK-LABEL: name: xor_i192 + ; CHECK: %lo1:_(s64) = COPY $x10 + ; CHECK-NEXT: %mid1:_(s64) = COPY $x11 + ; CHECK-NEXT: %hi1:_(s64) = COPY $x12 + ; CHECK-NEXT: %lo2:_(s64) = COPY $x13 + ; CHECK-NEXT: %mid2:_(s64) = COPY $x14 + ; CHECK-NEXT: %hi2:_(s64) = COPY $x15 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR %lo1, %lo2 + ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR %mid1, %mid2 + ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR %hi1, %hi2 + ; CHECK-NEXT: $x10 = COPY [[XOR]](s64) + ; CHECK-NEXT: $x11 = COPY [[XOR1]](s64) + ; CHECK-NEXT: $x12 = COPY [[XOR2]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12 + %lo1:_(s64) = COPY $x10 + %mid1:_(s64) = COPY $x11 + %hi1:_(s64) = COPY $x12 + %lo2:_(s64) = COPY $x13 + %mid2:_(s64) = COPY $x14 + %hi2:_(s64) = COPY $x15 + %x1:_(s192) = G_MERGE_VALUES %lo1(s64), %mid1(s64), %hi1(s64) + %x2:_(s192) = G_MERGE_VALUES %lo2(s64), %mid2(s64), %hi2(s64) + %y:_(s192) = G_XOR %x1, %x2 + %lo:_(s64), %mid:_(s64), %hi:_(s64) = G_UNMERGE_VALUES %y(s192) + $x10 = COPY %lo(s64) + $x11 = COPY %mid(s64) + $x12 = COPY %hi(s64) + PseudoRET implicit $x10, implicit $x11, implicit $x12 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/merge-unmerge-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/merge-unmerge-rv32.mir new file mode 100644 index 0000000..46a7df4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/merge-unmerge-rv32.mir @@ -0,0 +1,133 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck --check-prefix=RV32 %s + +--- +name: merge_i32 +body: | + bb.0.entry: + liveins: $x10 + ; RV32-LABEL: name: merge_i32 + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C]](s32) + ; RV32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ASSERT_ZEXT]], [[SHL]] + ; RV32-NEXT: $x10 = COPY [[OR]](s32) + ; RV32-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = G_ASSERT_ZEXT %0, 16 + %2:_(s16) = G_TRUNC %1(s32) + %3:_(s32) = G_MERGE_VALUES %2(s16), %2(s16) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 +... +--- +name: merge_i64 +body: | + bb.0.entry: + liveins: $x10 + ; RV32-LABEL: name: merge_i64 + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32-NEXT: $x10 = COPY [[COPY]](s32) + ; RV32-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s64) = G_MERGE_VALUES %0(s32), %0(s32) + %2:_(s32) = G_TRUNC %1(s64) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 +... +--- +name: merge_i128 +body: | + bb.0.entry: + liveins: $x10 + ; RV32-LABEL: name: merge_i128 + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32-NEXT: $x10 = COPY [[COPY]](s32) + ; RV32-NEXT: PseudoRET implicit $x10 + %1:_(s32) = COPY $x10 + %2:_(s64) = G_ZEXT %1(s32) + %0:_(s128) = G_MERGE_VALUES %2(s64), %2(s64) + %3:_(s32) = G_TRUNC %0(s128) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 +... +--- +name: unmerge_i32 +body: | + bb.0.entry: + liveins: $x10 + ; RV32-LABEL: name: unmerge_i32 + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; RV32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; RV32-NEXT: $x10 = COPY [[AND]](s32) + ; RV32-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0(s32) + %4:_(s32) = G_ZEXT %2(s16) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: unmerge_i64 +body: | + bb.0.entry: + liveins: $x10 + ; RV32-LABEL: name: unmerge_i64 + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32-NEXT: $x10 = COPY [[COPY]](s32) + ; RV32-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s64) = G_ZEXT %0(s32) + %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 +... +--- +name: unmerge_i128 +body: | + bb.0.entry: + liveins: $x10 + ; RV32-LABEL: name: unmerge_i128 + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: $x10 = COPY [[C]](s32) + ; RV32-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s128) = G_ZEXT %0(s32) + %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %1(s128) + %4:_(s32) = G_TRUNC %3(s64) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... +--- +name: unmerge_i256 +body: | + bb.0.entry: + liveins: $x10 + ; RV32-LABEL: name: unmerge_i256 + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32-NEXT: $x10 = COPY [[COPY]](s32) + ; RV32-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s256) = G_ZEXT %0(s32) + %2:_(s128), %3:_(s128) = G_UNMERGE_VALUES %1(s256) + %4:_(s32) = G_TRUNC %2(s128) + $x10 = COPY %4(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/merge-unmerge-rv32d.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/merge-unmerge-rv32d.mir new file mode 100644 index 0000000..10c775c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/merge-unmerge-rv32d.mir @@ -0,0 +1,38 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s + +--- +name: merge_i64 +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: merge_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32) + ; CHECK-NEXT: $f10_d = COPY [[MV]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s32) = COPY $x10 + %1:_(s64) = G_MERGE_VALUES %0(s32), %0(s32) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d +... +--- +name: unmerge_i32 +body: | + bb.0.entry: + liveins: $f10_d + ; CHECK-LABEL: name: unmerge_i32 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d + ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[UV]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/merge-unmerge-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/merge-unmerge-rv64.mir new file mode 100644 index 0000000..3cf3a7c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/merge-unmerge-rv64.mir @@ -0,0 +1,119 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: merge_i32 +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: merge_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[C]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ASSERT_ZEXT]], [[SHL]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_ASSERT_ZEXT %0, 16 + %2:_(s16) = G_TRUNC %1(s64) + %3:_(s32) = G_MERGE_VALUES %2(s16), %2(s16) + %4:_(s64) = G_ZEXT %3(s32) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... +--- +name: merge_i64 +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: merge_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[C]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ASSERT_ZEXT]], [[SHL]] + ; CHECK-NEXT: $x10 = COPY [[OR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_ASSERT_ZEXT %0, 32 + %2:_(s32) = G_TRUNC %1(s64) + %3:_(s64) = G_MERGE_VALUES %2(s32), %2(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... +--- +name: merge_i128 +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: merge_i128 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s128) = G_MERGE_VALUES %0(s64), %0(s64) + %2:_(s64) = G_TRUNC %1(s128) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... +--- +name: unmerge_i32 +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: unmerge_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: $x10 = COPY [[AND]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64) + %3:_(s64) = G_ZEXT %1(s32) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 +... +--- +name: unmerge_i64 +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: unmerge_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s128) = G_ZEXT %0(s64) + %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %1(s128) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 +... +--- +name: unmerge_i128 +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: unmerge_i128 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: $x10 = COPY [[COPY]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s256) = G_ZEXT %0(s64) + %2:_(s128), %3:_(s128) = G_UNMERGE_VALUES %1(s256) + %4:_(s64) = G_TRUNC %2(s128) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add-zve32x.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add-zve32x.mir new file mode 100644 index 0000000..85ad899 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add-zve32x.mir @@ -0,0 +1,274 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zve32x -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+zve32x -run-pass=legalizer %s -o - | FileCheck %s +--- +name: test_nxv2i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv64i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv2i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv2i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add.mir new file mode 100644 index 0000000..aa0ab96 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add.mir @@ -0,0 +1,399 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: test_nxv1i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv64i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv4i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv8i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-and.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-and.mir new file mode 100644 index 0000000..8295e55 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-and.mir @@ -0,0 +1,399 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: test_nxv1i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_AND %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_AND %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv64i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_AND %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_AND %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_AND %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_AND %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_AND %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_AND %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_AND %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_AND %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_AND %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv4i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_AND %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv8i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_() = G_AND [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[AND]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_AND %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-anyext.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-anyext.mir new file mode 100644 index 0000000..d5a81d5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-anyext.mir @@ -0,0 +1,1545 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV32 %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV64 %s + +# Extend from s1 element vectors +--- +name: anyext_nxv1i8_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv1i8_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i8_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv1i16_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv1i16_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i16_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv1i32_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv1i32_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i32_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv1i64_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv1i64_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i64_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i8_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv2i8_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv2i8_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i16_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv2i16_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv2i16_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i32_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv2i32_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv2i32_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i64_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv2i64_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv2i64_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i8_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv4i8_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv4i8_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv4i16_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv4i16_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv4i16_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv4i32_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv4i32_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv4i32_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i64_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv4i64_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv4i64_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i8_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv8i8_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv8i8_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv8i16_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv8i16_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv8i16_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv8i32_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv8i32_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv8i32_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i64_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv8i64_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv8i64_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: anyext_nxv16i8_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv16i8_nxv16i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv16i8_nxv16i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv16i16_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv16i16_nxv16i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv16i16_nxv16i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv16i32_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv16i32_nxv16i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv16i32_nxv16i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: anyext_nxv32i8_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv32i8_nxv32i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv32i8_nxv32i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv32i16_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv32i16_nxv32i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv32i16_nxv32i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: anyext_nxv64i8_nxv64i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv64i8_nxv64i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv64i8_nxv64i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v0 + %0:_() = G_ANYEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... + +# Extend from s8 element vectors +--- +name: anyext_nxv1i16_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv1i16_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i16_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv1i32_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv1i32_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i32_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv1i64_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv1i64_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i64_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i16_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv2i16_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv2i16_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i32_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv2i32_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv2i32_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i64_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv2i64_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv2i64_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i16_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv4i16_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv4i16_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv4i32_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv4i32_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv4i32_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i64_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv4i64_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv4i64_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i16_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv8i16_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv8i16_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv8i32_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv8i32_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv8i32_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i64_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv8i64_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv8i64_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: anyext_nxv16i16_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv16i16_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv16i16_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8m2 + %0:_() = G_ANYEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv16i32_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv16i32_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv16i32_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m4 + %0:_() = G_ANYEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: anyext_nxv32i16_nxv32i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv32i16_nxv32i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv32i16_nxv32i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m4 + %0:_() = G_ANYEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... + +# Extend from s16 element vectors +--- +name: anyext_nxv1i32_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv1i32_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i32_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv1i64_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv1i64_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i64_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i32_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv2i32_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv2i32_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i64_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv2i64_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv2i64_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i32_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv4i32_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv4i32_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i64_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv4i64_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv4i64_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i32_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv8i32_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv8i32_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8m2 + %0:_() = G_ANYEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i64_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv8i64_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv8i64_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m2 + %0:_() = G_ANYEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: anyext_nxv16i32_nxv16i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv16i32_nxv16i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv16i32_nxv16i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m4 + %0:_() = G_ANYEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... + +# Extend from s32 element vectors +--- +name: anyext_nxv1i64_nxv1i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv1i64_nxv1i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i64_nxv1i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i64_nxv2i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv2i64_nxv2i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv2i64_nxv2i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ANYEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i64_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv4i64_nxv4i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv4i64_nxv4i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8m2 + %0:_() = G_ANYEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i64_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv8i64_nxv8i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv8i64_nxv8i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_() = G_ANYEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m4 + %0:_() = G_ANYEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-bitcast.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-bitcast.mir new file mode 100644 index 0000000..7b5d568 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-bitcast.mir @@ -0,0 +1,356 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: bitcast_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv1i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: bitcast_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv2i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: bitcast_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv4i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: bitcast_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv8i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: bitcast_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv16i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8m2 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 +... +--- +name: bitcast_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv32i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8m4 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 +... +--- +name: bitcast_nxv64i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv64i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8m8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 +... +--- +name: bitcast_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv1i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: bitcast_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv2i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: bitcast_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv4i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: bitcast_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv8i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8m2 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 +... +--- +name: bitcast_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv16i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8m4 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 +... +--- +name: bitcast_nxv32i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv32i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8m8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 +... +--- +name: bitcast_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv1i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: bitcast_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv2i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: bitcast_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv4i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8m2 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 +... +--- +name: bitcast_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv8i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8m4 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 +... +--- +name: bitcast_nxv16i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv16i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8m8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 +... +--- +name: bitcast_nxv1i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv1i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: bitcast_nxv2i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv2i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8m2 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 +... +--- +name: bitcast_nxv4i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv4i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8m4 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 +... +--- +name: bitcast_nxv8i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: bitcast_nxv8i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: $v8m8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_BITCAST %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-extract-subvector.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-extract-subvector.mir new file mode 100644 index 0000000..a608187 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-extract-subvector.mir @@ -0,0 +1,484 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV32 +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV64 + +# Special handling for i1-element vectors with non-zero index +--- +name: extract_subvector_nxv2i1_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: extract_subvector_nxv2i1_nxv4i1 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C2]](s32) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C3]](s32) + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF1]], [[SELECT]], [[LSHR]](s32), [[VMSET_VL]](), [[C3]], 3 + ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV32-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C4]](s32) + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[EXTRACT_SUBVECTOR]](), [[SPLAT_VECTOR2]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: extract_subvector_nxv2i1_nxv4i1 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C2]](s64) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C3]](s64) + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF1]], [[SELECT]], [[LSHR]](s64), [[VMSET_VL]](), [[C3]], 3 + ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV64-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C4]](s64) + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[EXTRACT_SUBVECTOR]](), [[SPLAT_VECTOR2]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 2 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_nxv2i1_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: extract_subvector_nxv2i1_nxv8i1 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C2]](s32) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C3]](s32) + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF1]], [[SELECT]], [[LSHR]](s32), [[VMSET_VL]](), [[C3]], 3 + ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV32-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C4]](s32) + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[EXTRACT_SUBVECTOR]](), [[SPLAT_VECTOR2]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: extract_subvector_nxv2i1_nxv8i1 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C2]](s64) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C3]](s64) + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF1]], [[SELECT]], [[LSHR]](s64), [[VMSET_VL]](), [[C3]], 3 + ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV64-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C4]](s64) + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[EXTRACT_SUBVECTOR]](), [[SPLAT_VECTOR2]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 2 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_nxv4i1_nxv64i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: extract_subvector_nxv4i1_nxv64i1 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[SELECT]](), 16 + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C2]](s32) + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[EXTRACT_SUBVECTOR]](), [[SPLAT_VECTOR2]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: extract_subvector_nxv4i1_nxv64i1 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[SELECT]](), 16 + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C2]](s64) + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[EXTRACT_SUBVECTOR]](), [[SPLAT_VECTOR2]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 16 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_nxv32i1_nxv64i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: extract_subvector_nxv32i1_nxv64i1 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C1]](s32) + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF1]], [[BITCAST]], [[LSHR]](s32), [[VMSET_VL]](), [[C1]], 3 + ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV32-NEXT: [[BITCAST1:%[0-9]+]]:_() = G_BITCAST [[EXTRACT_SUBVECTOR]]() + ; RV32-NEXT: $v8 = COPY [[BITCAST1]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: extract_subvector_nxv32i1_nxv64i1 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C1]](s64) + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF1]], [[BITCAST]], [[LSHR]](s64), [[VMSET_VL]](), [[C1]], 3 + ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV64-NEXT: [[BITCAST1:%[0-9]+]]:_() = G_BITCAST [[EXTRACT_SUBVECTOR]]() + ; RV64-NEXT: $v8 = COPY [[BITCAST1]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 32 + $v8 = COPY %1() + PseudoRET implicit $v8 +... + +# i1-element vectors with zero index +--- +name: extract_subvector_nxv1i1_nxv4i1_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: extract_subvector_nxv1i1_nxv4i1_zero + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[DEF]](), 0 + ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_nxv4i1_nxv8i1_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: extract_subvector_nxv4i1_nxv8i1_zero + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[DEF]](), 0 + ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_nxv32i1_nxv64i1_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: extract_subvector_nxv32i1_nxv64i1_zero + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[BITCAST]](), 0 + ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_() = G_BITCAST [[EXTRACT_SUBVECTOR]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST1]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... + +# Extract with zero index +--- +name: extract_subvector_nxv1i8_nxv2i8_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: extract_subvector_nxv1i8_nxv2i8_zero + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[DEF]](), 0 + ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_nxv2i16_nxv4i16_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: extract_subvector_nxv2i16_nxv4i16_zero + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[DEF]](), 0 + ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_nxv4i32_nxv8i32_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: extract_subvector_nxv4i32_nxv8i32_zero + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[DEF]](), 0 + ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_nxv4i8_nxv8i64_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: extract_subvector_nxv4i8_nxv8i64_zero + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[DEF]](), 0 + ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... + +# Extract with non-zero index +--- +name: extract_subvector_nxv1i8_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: extract_subvector_nxv1i8_nxv2i8 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C1]](s32) + ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF]], [[DEF]], [[LSHR]](s32), [[VMSET_VL]](), [[C1]], 3 + ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV32-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: extract_subvector_nxv1i8_nxv2i8 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C1]](s64) + ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF]], [[DEF]], [[LSHR]](s64), [[VMSET_VL]](), [[C1]], 3 + ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV64-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 1 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_nxv1i16_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: extract_subvector_nxv1i16_nxv4i16 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C1]](s32) + ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF]], [[DEF]], [[LSHR]](s32), [[VMSET_VL]](), [[C1]], 3 + ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV32-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: extract_subvector_nxv1i16_nxv4i16 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C1]](s64) + ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF]], [[DEF]], [[LSHR]](s64), [[VMSET_VL]](), [[C1]], 3 + ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV64-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 2 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_nxv4i32_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: extract_subvector_nxv4i32_nxv8i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[DEF]](), 4 + ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 4 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_nxv2i64_nxv8i64 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: extract_subvector_nxv2i64_nxv8i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[DEF]](), 2 + ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 2 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_subregidx_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: extract_subvector_subregidx_zero + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[DEF]](), 0 + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C1]](s32) + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF1]], [[EXTRACT_SUBVECTOR]], [[LSHR]](s32), [[VMSET_VL]](), [[C1]], 3 + ; RV32-NEXT: [[EXTRACT_SUBVECTOR1:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV32-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR1]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: extract_subvector_subregidx_zero + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[DEF]](), 0 + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C1]](s64) + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF1]], [[EXTRACT_SUBVECTOR]], [[LSHR]](s64), [[VMSET_VL]](), [[C1]], 3 + ; RV64-NEXT: [[EXTRACT_SUBVECTOR1:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV64-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR1]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 1 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: extract_subvector_subregidx +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: extract_subvector_subregidx + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[DEF]](), 2 + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C1]](s32) + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF1]], [[EXTRACT_SUBVECTOR]], [[LSHR]](s32), [[VMSET_VL]](), [[C1]], 3 + ; RV32-NEXT: [[EXTRACT_SUBVECTOR1:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV32-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR1]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: extract_subvector_subregidx + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[DEF]](), 2 + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C1]](s64) + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_() = G_VSLIDEDOWN_VL [[DEF1]], [[EXTRACT_SUBVECTOR]], [[LSHR]](s64), [[VMSET_VL]](), [[C1]], 3 + ; RV64-NEXT: [[EXTRACT_SUBVECTOR1:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](), 0 + ; RV64-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR1]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_EXTRACT_SUBVECTOR %0(), 3 + $v8 = COPY %1() + PseudoRET implicit $v8 +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-icmp.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-icmp.mir new file mode 100644 index 0000000..9a92f68 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-icmp.mir @@ -0,0 +1,712 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV32 %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV64 %s + +--- +name: icmp_nxv1i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv1i1 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv1i1 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv2i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv2i1 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv2i1 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv4i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv4i1 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv4i1 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv8i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv8i1 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv8i1 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv16i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv16i1 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv16i1 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv32i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv32i1 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv32i1 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv64i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv64i1 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv64i1 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[SELECT]](), [[SELECT]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv1i8 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv1i8 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv2i8 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv2i8 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv4i8 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv4i8 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv8i8 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv8i8 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv16i8 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv16i8 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv32i8 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv32i8 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv64i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv64i8 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv64i8 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv1i16 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv1i16 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv2i16 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv2i16 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv4i16 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv4i16 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv8i16 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv8i16 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv16i16 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv16i16 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv32i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv32i16 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv32i16 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv1i32 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv1i32 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv2i32 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv2i32 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv4i32 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv4i32 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv8i32 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv8i32 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv16i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv16i32 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv16i32 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv1i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv1i64 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv1i64 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv2i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv2i64 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv2i64 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv4i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv4i64 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv4i64 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: icmp_nxv8i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv8i64 + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv8i64 + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1() + PseudoRET implicit $v8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-implicit-def.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-implicit-def.mir new file mode 100644 index 0000000..8ee4086 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-implicit-def.mir @@ -0,0 +1,410 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: implicitdef_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv1i1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv2i1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv4i1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv8i1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv16i1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv32i1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv64i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv64i1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv1i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv2i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv4i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv8i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv16i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m2 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: implicitdef_nxv32i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv32i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m4 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: implicitdef_nxv64i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv64i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: implicitdef_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv1i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv2i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv4i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv8i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m2 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: implicitdef_nxv16i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv16i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m4 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: implicitdef_nxv32i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv32i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: implicitdef_nxv1i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv1i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv2i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv2i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv4i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m2 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: implicitdef_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv8i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m4 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: implicitdef_nxv16i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv16i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: implicitdef_nxv1i64 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv1i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv2i64 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv2i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m2 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: implicitdef_nxv4i64 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv4i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m4 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: implicitdef_nxv8i64 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv8i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir new file mode 100644 index 0000000..22e8a93 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir @@ -0,0 +1,826 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,RV32 +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,RV64 + + +# BigVec=G_IMPLICIT_DEF when index is non-zero +--- +name: insert_subvector_nxv2i1_nxv4i1_undef_nonzero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: insert_subvector_nxv2i1_nxv4i1_undef_nonzero + ; RV32: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C2]](s64) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C3]](s64) + ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_() = G_SELECT [[DEF1]](), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV32-NEXT: [[DEF2:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF2]], [[SELECT1]](), 0 + ; RV32-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C4]](s64) + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C5]](s64) + ; RV32-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB1]], [[C5]](s64) + ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LSHR1]], [[LSHR]] + ; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_() = G_VSLIDEUP_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR1]](s64), [[VMSET_VL]](), [[ADD]](s64), 1 + ; RV32-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C6]](s64) + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[VSLIDEUP_VL]](), [[SPLAT_VECTOR4]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: insert_subvector_nxv2i1_nxv4i1_undef_nonzero + ; RV64: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C2]](s32) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C3]](s32) + ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_() = G_SELECT [[DEF1]](), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV64-NEXT: [[DEF2:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF2]], [[SELECT1]](), 0 + ; RV64-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C4]](s32) + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C5]](s32) + ; RV64-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB1]], [[C5]](s32) + ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR]] + ; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_() = G_VSLIDEUP_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR1]](s32), [[VMSET_VL]](), [[ADD]](s32), 1 + ; RV64-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C6]](s32) + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[VSLIDEUP_VL]](), [[SPLAT_VECTOR4]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 2 + $v8 = COPY %2() + PseudoRET implicit $v8 +... + +# BigVec=G_IMPLICIT_DEF when index is zero +--- +name: insert_subvector_nxv2i1_nxv4i1_undef_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insert_subvector_nxv2i1_nxv4i1_undef_zero + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF]], [[DEF1]](), 0 + ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 0 + $v8 = COPY %2() + PseudoRET implicit $v8 +... + + +# Special handling for i1-element vectors with non-zero index +--- +name: insert_subvector_nxv2i1_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: insert_subvector_nxv2i1_nxv4i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C2]](s64) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C3]](s64) + ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[SELECT1]](), 0 + ; RV32-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C4]](s64) + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C5]](s64) + ; RV32-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB1]], [[C5]](s64) + ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LSHR1]], [[LSHR]] + ; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_() = G_VSLIDEUP_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR1]](s64), [[VMSET_VL]](), [[ADD]](s64), 1 + ; RV32-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C6]](s64) + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[VSLIDEUP_VL]](), [[SPLAT_VECTOR4]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: insert_subvector_nxv2i1_nxv4i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C2]](s32) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C3]](s32) + ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[SELECT1]](), 0 + ; RV64-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C4]](s32) + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C5]](s32) + ; RV64-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB1]], [[C5]](s32) + ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR]] + ; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_() = G_VSLIDEUP_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR1]](s32), [[VMSET_VL]](), [[ADD]](s32), 1 + ; RV64-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C6]](s32) + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[VSLIDEUP_VL]](), [[SPLAT_VECTOR4]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 2 + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insert_subvector_nxv4i1_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: insert_subvector_nxv4i1_nxv8i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C2]](s64) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C3]](s64) + ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[SELECT1]](), 0 + ; RV32-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C4]](s64) + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C5]](s64) + ; RV32-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB1]], [[C6]](s64) + ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LSHR1]], [[LSHR]] + ; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_() = G_VSLIDEUP_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR1]](s64), [[VMSET_VL]](), [[ADD]](s64), 0 + ; RV32-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C7]](s64) + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[VSLIDEUP_VL]](), [[SPLAT_VECTOR4]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: insert_subvector_nxv4i1_nxv8i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C2]](s32) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C3]](s32) + ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[SELECT1]](), 0 + ; RV64-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C4]](s32) + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C5]](s32) + ; RV64-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB1]], [[C6]](s32) + ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR]] + ; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_() = G_VSLIDEUP_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR1]](s32), [[VMSET_VL]](), [[ADD]](s32), 0 + ; RV64-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C7]](s32) + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[VSLIDEUP_VL]](), [[SPLAT_VECTOR4]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 4 + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insert_subvector_nxv32i1_nxv64i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: insert_subvector_nxv32i1_nxv64i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[COPY]]() + ; RV32-NEXT: [[BITCAST1:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[BITCAST1]](), 0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C1]](s64) + ; RV32-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB1]], [[C1]](s64) + ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LSHR1]], [[LSHR]] + ; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_() = G_VSLIDEUP_VL [[BITCAST]], [[INSERT_SUBVECTOR]], [[LSHR1]](s64), [[VMSET_VL]](), [[ADD]](s64), 1 + ; RV32-NEXT: [[BITCAST2:%[0-9]+]]:_() = G_BITCAST [[VSLIDEUP_VL]]() + ; RV32-NEXT: $v8 = COPY [[BITCAST2]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: insert_subvector_nxv32i1_nxv64i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[COPY]]() + ; RV64-NEXT: [[BITCAST1:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[BITCAST1]](), 0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C1]](s32) + ; RV64-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB1]], [[C1]](s32) + ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR]] + ; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_() = G_VSLIDEUP_VL [[BITCAST]], [[INSERT_SUBVECTOR]], [[LSHR1]](s32), [[VMSET_VL]](), [[ADD]](s32), 1 + ; RV64-NEXT: [[BITCAST2:%[0-9]+]]:_() = G_BITCAST [[VSLIDEUP_VL]]() + ; RV64-NEXT: $v8 = COPY [[BITCAST2]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 32 + $v8 = COPY %2() + PseudoRET implicit $v8 +... + +# i1-element vectors with zero index +--- +name: insert_subvector_nxv2i1_nxv4i1_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: insert_subvector_nxv2i1_nxv4i1_zero + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C2]](s64) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C3]](s64) + ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[SELECT1]](), 0 + ; RV32-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C4]](s64) + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C5]](s64) + ; RV32-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_() = G_VMV_V_V_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR]](s64) + ; RV32-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C6]](s64) + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[VMV_V_V_VL]](), [[SPLAT_VECTOR4]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: insert_subvector_nxv2i1_nxv4i1_zero + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C2]](s32) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C3]](s32) + ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[SELECT1]](), 0 + ; RV64-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C4]](s32) + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C5]](s32) + ; RV64-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_() = G_VMV_V_V_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR]](s32) + ; RV64-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C6]](s32) + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[VMV_V_V_VL]](), [[SPLAT_VECTOR4]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 0 + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insert_subvector_nxv4i1_nxv8i1_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: insert_subvector_nxv4i1_nxv8i1_zero + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C2]](s64) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C3]](s64) + ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[SELECT1]](), 0 + ; RV32-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C4]](s64) + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C5]](s64) + ; RV32-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_() = G_VMV_V_V_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR]](s64) + ; RV32-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV32-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C6]](s64) + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[VMV_V_V_VL]](), [[SPLAT_VECTOR4]] + ; RV32-NEXT: $v8 = COPY [[ICMP]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: insert_subvector_nxv4i1_nxv8i1_zero + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C2]](s32) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C3]](s32) + ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[SELECT1]](), 0 + ; RV64-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C4]](s32) + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C5]](s32) + ; RV64-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_() = G_VMV_V_V_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR]](s32) + ; RV64-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C6]](s32) + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[VMV_V_V_VL]](), [[SPLAT_VECTOR4]] + ; RV64-NEXT: $v8 = COPY [[ICMP]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 0 + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insert_subvector_nxv32i1_nxv64i1_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: insert_subvector_nxv32i1_nxv64i1_zero + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[COPY]]() + ; RV32-NEXT: [[BITCAST1:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[BITCAST1]](), 0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C1]](s64) + ; RV32-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_() = G_VMV_V_V_VL [[BITCAST]], [[INSERT_SUBVECTOR]], [[LSHR]](s64) + ; RV32-NEXT: [[BITCAST2:%[0-9]+]]:_() = G_BITCAST [[VMV_V_V_VL]]() + ; RV32-NEXT: $v8 = COPY [[BITCAST2]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: insert_subvector_nxv32i1_nxv64i1_zero + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[COPY]]() + ; RV64-NEXT: [[BITCAST1:%[0-9]+]]:_() = G_BITCAST [[DEF]]() + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[BITCAST1]](), 0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C1]](s32) + ; RV64-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_() = G_VMV_V_V_VL [[BITCAST]], [[INSERT_SUBVECTOR]], [[LSHR]](s32) + ; RV64-NEXT: [[BITCAST2:%[0-9]+]]:_() = G_BITCAST [[VMV_V_V_VL]]() + ; RV64-NEXT: $v8 = COPY [[BITCAST2]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 0 + $v8 = COPY %2() + PseudoRET implicit $v8 +... + +# Insert with zero index +--- +name: insert_subvector_nxv1i8_nxv2i8_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: insert_subvector_nxv1i8_nxv2i8_zero + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](), 0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C1]](s64) + ; RV32-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_() = G_VMV_V_V_VL [[COPY]], [[INSERT_SUBVECTOR]], [[LSHR]](s64) + ; RV32-NEXT: $v8 = COPY [[VMV_V_V_VL]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: insert_subvector_nxv1i8_nxv2i8_zero + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](), 0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C1]](s32) + ; RV64-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_() = G_VMV_V_V_VL [[COPY]], [[INSERT_SUBVECTOR]], [[LSHR]](s32) + ; RV64-NEXT: $v8 = COPY [[VMV_V_V_VL]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 0 + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insert_subvector_nxv2i16_nxv4i16_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: insert_subvector_nxv2i16_nxv4i16_zero + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](), 0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C1]](s64) + ; RV32-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_() = G_VMV_V_V_VL [[COPY]], [[INSERT_SUBVECTOR]], [[LSHR]](s64) + ; RV32-NEXT: $v8 = COPY [[VMV_V_V_VL]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: insert_subvector_nxv2i16_nxv4i16_zero + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](), 0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C1]](s32) + ; RV64-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_() = G_VMV_V_V_VL [[COPY]], [[INSERT_SUBVECTOR]], [[LSHR]](s32) + ; RV64-NEXT: $v8 = COPY [[VMV_V_V_VL]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 0 + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insert_subvector_nxv4i32_nxv8i32_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4 + ; CHECK-LABEL: name: insert_subvector_nxv4i32_nxv8i32_zero + ; CHECK: liveins: $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](), 0 + ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 0 + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insert_subvector_nxv2i64_nxv8i64_zero +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8 + ; CHECK-LABEL: name: insert_subvector_nxv2i64_nxv8i64_zero + ; CHECK: liveins: $v8m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](), 0 + ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 0 + $v8 = COPY %2() + PseudoRET implicit $v8 +... + +# Insert with non-zero index +--- +name: insert_subvector_nxv1i8_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: insert_subvector_nxv1i8_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](), 0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C1]](s64) + ; RV32-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB1]], [[C1]](s64) + ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LSHR1]], [[LSHR]] + ; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_() = G_VSLIDEUP_VL [[COPY]], [[INSERT_SUBVECTOR]], [[LSHR1]](s64), [[VMSET_VL]](), [[ADD]](s64), 1 + ; RV32-NEXT: $v8 = COPY [[VSLIDEUP_VL]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: insert_subvector_nxv1i8_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](), 0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C1]](s32) + ; RV64-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB1]], [[C1]](s32) + ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR]] + ; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_() = G_VSLIDEUP_VL [[COPY]], [[INSERT_SUBVECTOR]], [[LSHR1]](s32), [[VMSET_VL]](), [[ADD]](s32), 1 + ; RV64-NEXT: $v8 = COPY [[VSLIDEUP_VL]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 1 + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insert_subvector_nxv2i16_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: insert_subvector_nxv2i16_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](), 0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C1]](s64) + ; RV32-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB1]], [[C1]](s64) + ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LSHR1]], [[LSHR]] + ; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_() = G_VSLIDEUP_VL [[COPY]], [[INSERT_SUBVECTOR]], [[LSHR1]](s64), [[VMSET_VL]](), [[ADD]](s64), 0 + ; RV32-NEXT: $v8 = COPY [[VSLIDEUP_VL]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: insert_subvector_nxv2i16_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](), 0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C1]](s32) + ; RV64-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB1]], [[C1]](s32) + ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR]] + ; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_() = G_VSLIDEUP_VL [[COPY]], [[INSERT_SUBVECTOR]], [[LSHR1]](s32), [[VMSET_VL]](), [[ADD]](s32), 0 + ; RV64-NEXT: $v8 = COPY [[VSLIDEUP_VL]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 1 + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insert_subvector_nxv8i16_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8 + ; RV32-LABEL: name: insert_subvector_nxv8i16_nxv1i16 + ; RV32: liveins: $v8m8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[COPY]](), 4 + ; RV32-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](), 0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C1]](s64) + ; RV32-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_() = G_VMV_V_V_VL [[EXTRACT_SUBVECTOR]], [[INSERT_SUBVECTOR]], [[LSHR]](s64) + ; RV32-NEXT: [[INSERT_SUBVECTOR1:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[COPY]], [[VMV_V_V_VL]](), 4 + ; RV32-NEXT: $v8 = COPY [[INSERT_SUBVECTOR1]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: insert_subvector_nxv8i16_nxv1i16 + ; RV64: liveins: $v8m8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_() = G_EXTRACT_SUBVECTOR [[COPY]](), 4 + ; RV64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](), 0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C1]](s32) + ; RV64-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_() = G_VMV_V_V_VL [[EXTRACT_SUBVECTOR]], [[INSERT_SUBVECTOR]], [[LSHR]](s32) + ; RV64-NEXT: [[INSERT_SUBVECTOR1:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[COPY]], [[VMV_V_V_VL]](), 4 + ; RV64-NEXT: $v8 = COPY [[INSERT_SUBVECTOR1]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 4 + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insert_subvector_nxv4i32_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4 + ; CHECK-LABEL: name: insert_subvector_nxv4i32_nxv8i32 + ; CHECK: liveins: $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](), 4 + ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 4 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 +... +--- +name: insert_subvector_nxv2i64_nxv8i64 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8 + ; CHECK-LABEL: name: insert_subvector_nxv2i64_nxv8i64 + ; CHECK: liveins: $v8m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_() = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](), 4 + ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_INSERT_SUBVECTOR %0(), %1, 4 + $v8 = COPY %2() + PseudoRET implicit $v8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv32.mir new file mode 100644 index 0000000..d7c0e80 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv32.mir @@ -0,0 +1,1742 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: insertelement_nxv1i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i1_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 false + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s32) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv1i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i1_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 true + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s32) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv1i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv1i1_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %2:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %2(s32) + %1:_(s32) = COPY $x11 + %4:_() = G_IMPLICIT_DEF + %3:_() = G_INSERT_VECTOR_ELT %4, %0(s1), %1(s32) + $v0 = COPY %3() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv2i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i1_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 false + %3:_(s32) = G_CONSTANT i32 1 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s32) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv2i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i1_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 true + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s32) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv2i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv2i1_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %2:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %2(s32) + %1:_(s32) = COPY $x11 + %4:_() = G_IMPLICIT_DEF + %3:_() = G_INSERT_VECTOR_ELT %4, %0(s1), %1(s32) + $v0 = COPY %3() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv4i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i1_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 false + %3:_(s32) = G_CONSTANT i32 2 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s32) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv4i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i1_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 true + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s32) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv4i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s32) + %3:_() = G_IMPLICIT_DEF + %4:_(s32) = G_CONSTANT i32 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s1), %4(s32) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv8i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i1_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 false + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s32) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv8i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i1_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 true + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s32) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv8i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv8i1_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %2:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %2(s32) + %1:_(s32) = COPY $x11 + %4:_() = G_IMPLICIT_DEF + %3:_() = G_INSERT_VECTOR_ELT %4, %0(s1), %1(s32) + $v0 = COPY %3() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv16i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i1_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 false + %3:_(s32) = G_CONSTANT i32 15 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s32) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv16i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i1_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 true + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s32) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv16i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv16i1_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %2:_(s32) = COPY $x10 + %0:_(s1) = G_TRUNC %2(s32) + %1:_(s32) = COPY $x11 + %4:_() = G_IMPLICIT_DEF + %3:_() = G_INSERT_VECTOR_ELT %4, %0(s1), %1(s32) + $v0 = COPY %3() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv4i1_3 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0, $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i1_3 + ; CHECK: liveins: $v0, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s1), [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_() = COPY $v0 + %2:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %2(s32) + %4:_(s32) = G_CONSTANT i32 0 + %3:_() = G_INSERT_VECTOR_ELT %0, %1(s1), %4(s32) + $v0 = COPY %3() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv1i8_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i8_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i8_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i8_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i8_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv1i8_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %3:_() = G_IMPLICIT_DEF + %4:_(s32) = G_CONSTANT i32 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s8), %4(s32) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i8_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i8_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i8_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i8_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i8_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv2i8_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %3:_() = G_IMPLICIT_DEF + %4:_(s32) = G_CONSTANT i32 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s8), %4(s32) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i8_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i8_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i8_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i8_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i8_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i8_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %3:_() = G_IMPLICIT_DEF + %4:_(s32) = G_CONSTANT i32 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s8), %4(s32) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv8i8_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i8_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv8i8_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i8_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv8i8_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv8i8_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s32) + %3:_() = G_IMPLICIT_DEF + %4:_(s32) = G_CONSTANT i32 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s8), %4(s32) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv16i8_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i8_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s32) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv16i8_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i8_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s32) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv16i8_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: insertelement_nxv16i8_2 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[COPY1]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %2:_(s32) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $x11 + %4:_(s32) = COPY $x12 + %1:_(s64) = G_MERGE_VALUES %3(s32), %4(s32) + %6:_() = G_IMPLICIT_DEF + %7:_(s32) = G_TRUNC %1(s64) + %5:_() = G_INSERT_VECTOR_ELT %6, %0(s8), %7(s32) + $v8m2 = COPY %5() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv4i8_3 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i8_3 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s8), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %2:_(s32) = COPY $x10 + %1:_(s8) = G_TRUNC %2(s32) + %4:_(s32) = G_CONSTANT i32 0 + %3:_() = G_INSERT_VECTOR_ELT %0, %1(s8), %4(s32) + $v8 = COPY %3() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i16_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i16_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i16_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i16_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i16_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv1i16_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %3:_() = G_IMPLICIT_DEF + %4:_(s32) = G_CONSTANT i32 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s16), %4(s32) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i16_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i16_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 0 + %3:_(s32) = G_CONSTANT i32 1 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i16_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i16_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i16_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv2i16_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %3:_() = G_IMPLICIT_DEF + %4:_(s32) = G_CONSTANT i32 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s16), %4(s32) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i16_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i16_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i16_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i16_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i16_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i16_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %3:_() = G_IMPLICIT_DEF + %4:_(s32) = G_CONSTANT i32 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s16), %4(s32) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv8i16_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i16_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s32) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv8i16_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i16_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s32) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv8i16_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv8i16_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %3:_() = G_IMPLICIT_DEF + %4:_(s32) = G_CONSTANT i32 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s16), %4(s32) + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv16i16_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i16_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s32) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv16i16_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i16_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s32) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv16i16_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv16i16_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s32) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s32) + %3:_() = G_IMPLICIT_DEF + %4:_(s32) = G_CONSTANT i32 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s16), %4(s32) + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i16 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s16), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %2:_(s32) = COPY $x10 + %1:_(s16) = G_TRUNC %2(s32) + %4:_(s32) = G_CONSTANT i32 0 + %3:_() = G_INSERT_VECTOR_ELT %0, %1(s16), %4(s32) + $v8 = COPY %3() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i32_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i32_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %2(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i32_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i32_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i32_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv1i32_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(s32) = COPY $x10 + %2:_() = G_IMPLICIT_DEF + %3:_(s32) = G_CONSTANT i32 0 + %1:_() = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i32_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i32_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %2(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i32_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i32_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i32_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv2i32_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(s32) = COPY $x10 + %2:_() = G_IMPLICIT_DEF + %3:_(s32) = G_CONSTANT i32 0 + %1:_() = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i32_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i32_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %2(s32) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv4i32_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i32_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s32) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv4i32_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i32_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(s32) = COPY $x10 + %2:_() = G_IMPLICIT_DEF + %3:_(s32) = G_CONSTANT i32 0 + %1:_() = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv8i32_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i32_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %2(s32) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv8i32_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i32_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s32) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv8i32_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv8i32_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(s32) = COPY $x10 + %2:_() = G_IMPLICIT_DEF + %3:_(s32) = G_CONSTANT i32 0 + %1:_() = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv16i32_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i32_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; CHECK-NEXT: $v8m8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %2(s32) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: insertelement_nxv16i32_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i32_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; CHECK-NEXT: $v8m8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s32) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: insertelement_nxv16i32_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv16i32_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32) + ; CHECK-NEXT: $v8m8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(s32) = COPY $x10 + %2:_() = G_IMPLICIT_DEF + %3:_(s32) = G_CONSTANT i32 0 + %1:_() = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 +... +--- +name: insertelement_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: insertelement_nxv4i32 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_(s32) = COPY $x10 + %3:_(s32) = G_CONSTANT i32 0 + %2:_() = G_INSERT_VECTOR_ELT %0, %1(s32), %3(s32) + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv1i64_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i64_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i64_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i64_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C1]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i64_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv1i64_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %4:_() = G_IMPLICIT_DEF + %5:_(s32) = G_CONSTANT i32 0 + %3:_() = G_INSERT_VECTOR_ELT %4, %0(s64), %5(s32) + $v8 = COPY %3() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i64_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i64_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %3(s32) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv2i64_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i64_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C1]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %3(s32) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv2i64_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv2i64_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %4:_() = G_IMPLICIT_DEF + %5:_(s32) = G_CONSTANT i32 0 + %3:_() = G_INSERT_VECTOR_ELT %4, %0(s64), %5(s32) + $v8m2 = COPY %3() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv4i64_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i64_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %3(s32) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv4i64_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i64_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C1]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %3(s32) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv4i64_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv4i64_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %4:_() = G_IMPLICIT_DEF + %5:_(s32) = G_CONSTANT i32 0 + %3:_() = G_INSERT_VECTOR_ELT %4, %0(s64), %5(s32) + $v8m4 = COPY %3() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv8i64_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i64_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) + ; CHECK-NEXT: $v8m8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 0 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %3(s32) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: insertelement_nxv8i64_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i64_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C1]](s32) + ; CHECK-NEXT: $v8m8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 -1 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %3(s32) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: insertelement_nxv8i64_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv8i64_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32) + ; CHECK-NEXT: $v8m8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_(s32) = COPY $x10 + %2:_(s32) = COPY $x11 + %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) + %4:_() = G_IMPLICIT_DEF + %5:_(s32) = G_CONSTANT i32 0 + %3:_() = G_INSERT_VECTOR_ELT %4, %0(s64), %5(s32) + $v8m8 = COPY %3() + PseudoRET implicit $v8m8 +... +--- +name: insertelement_nxv4i64 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $v8m4 + + ; CHECK-LABEL: name: insertelement_nxv4i64 + ; CHECK: liveins: $x10, $x11, $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x11 + ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[MV]](s64), [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %2:_(s32) = COPY $x10 + %3:_(s32) = COPY $x11 + %1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %5:_(s32) = G_CONSTANT i32 0 + %4:_() = G_INSERT_VECTOR_ELT %0, %1(s64), %5(s32) + $v8m4 = COPY %4() + PseudoRET implicit $v8m4 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv64.mir new file mode 100644 index 0000000..4c33ddc --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insertelement-rv64.mir @@ -0,0 +1,1731 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: insertelement_nxv1i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i1_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 false + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s64) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv1i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i1_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 true + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s64) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv1i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv1i1_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[AND]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %2:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %5:_() = G_IMPLICIT_DEF + %6:_(s64) = G_ZEXT %1(s32) + %4:_() = G_INSERT_VECTOR_ELT %5, %0(s1), %6(s64) + $v0 = COPY %4() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv2i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i1_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 false + %3:_(s64) = G_CONSTANT i64 1 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s64) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv2i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i1_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 true + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s64) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv2i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv2i1_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[AND]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %2:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %5:_() = G_IMPLICIT_DEF + %6:_(s64) = G_ZEXT %1(s32) + %4:_() = G_INSERT_VECTOR_ELT %5, %0(s1), %6(s64) + $v0 = COPY %4() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv4i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i1_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 false + %3:_(s64) = G_CONSTANT i64 2 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s64) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv4i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i1_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 true + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s64) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv4i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s1), %4(s64) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv8i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i1_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 false + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s64) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv8i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i1_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 true + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s64) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv8i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv8i1_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[AND]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %2:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %5:_() = G_IMPLICIT_DEF + %6:_(s64) = G_ZEXT %1(s32) + %4:_() = G_INSERT_VECTOR_ELT %5, %0(s1), %6(s64) + $v0 = COPY %4() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv16i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i1_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 false + %3:_(s64) = G_CONSTANT i64 15 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s64) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv16i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i1_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C1]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %1:_() = G_IMPLICIT_DEF + %2:_(s1) = G_CONSTANT i1 true + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s1), %3(s64) + $v0 = COPY %0() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv16i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv16i1_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[AND]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %2:_(s64) = COPY $x10 + %0:_(s1) = G_TRUNC %2(s64) + %3:_(s64) = COPY $x11 + %1:_(s32) = G_TRUNC %3(s64) + %5:_() = G_IMPLICIT_DEF + %6:_(s64) = G_ZEXT %1(s32) + %4:_() = G_INSERT_VECTOR_ELT %5, %0(s1), %6(s64) + $v0 = COPY %4() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv4i1_3 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0, $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i1_3 + ; CHECK: liveins: $v0, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s1), [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_() = COPY $v0 + %2:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %2(s64) + %4:_(s64) = G_CONSTANT i64 0 + %3:_() = G_INSERT_VECTOR_ELT %0, %1(s1), %4(s64) + $v0 = COPY %3() + PseudoRET implicit $v0 +... +--- +name: insertelement_nxv1i8_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i8_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i8_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i8_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i8_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv1i8_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s8), %4(s64) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i8_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i8_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i8_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i8_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i8_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv2i8_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s8), %4(s64) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i8_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i8_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i8_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i8_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i8_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i8_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s8), %4(s64) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv8i8_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i8_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv8i8_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i8_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv8i8_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv8i8_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s8), %4(s64) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv16i8_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i8_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv16i8_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i8_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C1]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s8) = G_CONSTANT i8 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s8), %3(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv16i8_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: insertelement_nxv16i8_2 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[COPY1]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %2:_(s64) = COPY $x10 + %0:_(s8) = G_TRUNC %2(s64) + %1:_(s64) = COPY $x11 + %4:_() = G_IMPLICIT_DEF + %3:_() = G_INSERT_VECTOR_ELT %4, %0(s8), %1(s64) + $v8m2 = COPY %3() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv4i8_3 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i8_3 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s8), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %2:_(s64) = COPY $x10 + %1:_(s8) = G_TRUNC %2(s64) + %4:_(s64) = G_CONSTANT i64 0 + %3:_() = G_INSERT_VECTOR_ELT %0, %1(s8), %4(s64) + $v8 = COPY %3() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i16_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i16_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i16_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i16_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i16_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv1i16_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s16), %4(s64) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i16_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i16_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 0 + %3:_(s64) = G_CONSTANT i64 1 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i16_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i16_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i16_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv2i16_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s16), %4(s64) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i16_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i16_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i16_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i16_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i16_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i16_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s16), %4(s64) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv8i16_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i16_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv8i16_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i16_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv8i16_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv8i16_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s16), %4(s64) + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv16i16_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i16_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv16i16_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i16_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_(s16) = G_CONSTANT i16 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s16), %3(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv16i16_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv16i16_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s64) = COPY $x10 + %0:_(s16) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s16), %4(s64) + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i16 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s16), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %2:_(s64) = COPY $x10 + %1:_(s16) = G_TRUNC %2(s64) + %4:_(s64) = G_CONSTANT i64 0 + %3:_() = G_INSERT_VECTOR_ELT %0, %1(s16), %4(s64) + $v8 = COPY %3() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i32_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i32_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i32_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i32_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i32_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv1i32_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s32), %4(s64) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i32_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i32_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i32_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i32_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i32_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv2i32_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s32), %4(s64) + $v8 = COPY %2() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv4i32_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i32_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv4i32_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i32_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv4i32_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i32_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s32), %4(s64) + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv8i32_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i32_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv8i32_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i32_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv8i32_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv8i32_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s32), %4(s64) + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv16i32_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i32_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 0 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s64) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: insertelement_nxv16i32_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv16i32_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C1]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_(s32) = G_CONSTANT i32 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s32), %3(s64) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: insertelement_nxv16i32_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv16i32_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %1(s64) + %3:_() = G_IMPLICIT_DEF + %4:_(s64) = G_CONSTANT i64 0 + %2:_() = G_INSERT_VECTOR_ELT %3, %0(s32), %4(s64) + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 +... +--- +name: insertelement_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: insertelement_nxv4i32 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s32), [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %2:_(s64) = COPY $x10 + %1:_(s32) = G_TRUNC %2(s64) + %4:_(s64) = G_CONSTANT i64 0 + %3:_() = G_INSERT_VECTOR_ELT %0, %1(s32), %4(s64) + $v8m2 = COPY %3() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv1i64_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i64_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %2(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i64_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv1i64_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %3(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv1i64_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv1i64_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(s64) = COPY $x10 + %2:_() = G_IMPLICIT_DEF + %3:_(s64) = G_CONSTANT i64 0 + %1:_() = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64) + $v8 = COPY %1() + PseudoRET implicit $v8 +... +--- +name: insertelement_nxv2i64_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i64_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %2(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv2i64_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv2i64_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %3(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv2i64_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv2i64_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(s64) = COPY $x10 + %2:_() = G_IMPLICIT_DEF + %3:_(s64) = G_CONSTANT i64 0 + %1:_() = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 +... +--- +name: insertelement_nxv4i64_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i64_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %2(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv4i64_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv4i64_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %3(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv4i64_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv4i64_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(s64) = COPY $x10 + %2:_() = G_IMPLICIT_DEF + %3:_(s64) = G_CONSTANT i64 0 + %1:_() = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 +... +--- +name: insertelement_nxv8i64_0 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i64_0 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %2(s64) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: insertelement_nxv8i64_1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: insertelement_nxv8i64_1 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_(s64) = G_CONSTANT i64 -1 + %3:_(s64) = G_CONSTANT i64 0 + %0:_() = G_INSERT_VECTOR_ELT %1, %2(s64), %3(s64) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: insertelement_nxv8i64_2 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: insertelement_nxv8i64_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[IVEC]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(s64) = COPY $x10 + %2:_() = G_IMPLICIT_DEF + %3:_(s64) = G_CONSTANT i64 0 + %1:_() = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64) + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load-rv32.mir new file mode 100644 index 0000000..d8fe9b7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load-rv32.mir @@ -0,0 +1,79 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: vload_nxv1ptr +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv1ptr + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load ()) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load (), align 4) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv2ptr +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2ptr + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load ()) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load (), align 8) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv8ptr +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv8ptr + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load ()) + ; CHECK-NEXT: $v8m4 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load (), align 32) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: vload_nxv16ptr +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv16ptr + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load ()) + ; CHECK-NEXT: $v8m4 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load (), align 64) + $v8m4 = COPY %1() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load-rv64.mir new file mode 100644 index 0000000..98dee70 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load-rv64.mir @@ -0,0 +1,60 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: vload_nxv1ptr +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv1ptr + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load ()) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load (), align 8) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv2ptr +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2ptr + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load ()) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load (), align 16) + $v8 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nxv8ptr +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv8ptr + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load ()) + ; CHECK-NEXT: $v8m4 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load (), align 64) + $v8m4 = COPY %1() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load.mir new file mode 100644 index 0000000..2023bf7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load.mir @@ -0,0 +1,971 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- | + + define @vload_nxv1i8(ptr %pa) #0 { + %va = load , ptr %pa, align 1 + ret %va + } + + define @vload_nxv2i8(ptr %pa) #0 { + %va = load , ptr %pa, align 2 + ret %va + } + + define @vload_nxv4i8(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nxv8i8(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nxv16i8(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nxv32i8(ptr %pa) #0 { + %va = load , ptr %pa, align 32 + ret %va + } + + define @vload_nxv64i8(ptr %pa) #0 { + %va = load , ptr %pa, align 64 + ret %va + } + + define @vload_nxv1i16(ptr %pa) #0 { + %va = load , ptr %pa, align 2 + ret %va + } + + define @vload_nxv2i16(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nxv4i16(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nxv8i16(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nxv16i16(ptr %pa) #0 { + %va = load , ptr %pa, align 32 + ret %va + } + + define @vload_nxv32i16(ptr %pa) #0 { + %va = load , ptr %pa, align 64 + ret %va + } + + define @vload_nxv1i32(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nxv2i32(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nxv4i32(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nxv8i32(ptr %pa) #0 { + %va = load , ptr %pa, align 32 + ret %va + } + + define @vload_nxv16i32(ptr %pa) #0 { + %va = load , ptr %pa, align 64 + ret %va + } + + define @vload_nxv1i64(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nxv2i64(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nxv4i64(ptr %pa) #0 { + %va = load , ptr %pa, align 32 + ret %va + } + + define @vload_nxv8i64(ptr %pa) #0 { + %va = load , ptr %pa, align 64 + ret %va + } + + define @vload_nxv16i8_align1(ptr %pa) #0 { + %va = load , ptr %pa, align 1 + ret %va + } + + define @vload_nxv16i8_align2(ptr %pa) #0 { + %va = load , ptr %pa, align 2 + ret %va + } + + define @vload_nxv16i8_align16(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nxv16i8_align64(ptr %pa) #0 { + %va = load , ptr %pa, align 64 + ret %va + } + + define @vload_nxv4i16_align1(ptr %pa) #0 { + %va = load , ptr %pa, align 1 + ret %va + } + + define @vload_nxv4i16_align2(ptr %pa) #0 { + %va = load , ptr %pa, align 2 + ret %va + } + + define @vload_nxv4i16_align4(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nxv4i16_align8(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nxv4i16_align16(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nxv2i32_align2(ptr %pa) #0 { + %va = load , ptr %pa, align 2 + ret %va + } + + define @vload_nxv2i32_align4(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nxv2i32_align8(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nxv2i32_align16(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nxv2i32_align256(ptr %pa) #0 { + %va = load , ptr %pa, align 256 + ret %va + } + + define @vload_nxv2i64_align4(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nxv2i64_align8(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nxv2i64_align16(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nxv2i64_align32(ptr %pa) #0 { + %va = load , ptr %pa, align 32 + ret %va + } + + attributes #0 = { "target-features"="+v" } + +... +--- +name: vload_nxv1i8 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv1i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv2i8 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv4i8 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv4i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv8i8 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv8i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv16i8 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv16i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nxv32i8 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv32i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m4 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: vload_nxv64i8 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv64i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: vload_nxv1i16 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv1i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv2i16 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv4i16 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv4i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv8i16 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv8i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nxv16i16 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv16i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m4 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: vload_nxv32i16 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv32i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: vload_nxv1i32 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv1i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv2i32 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv4i32 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv4i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nxv8i32 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv8i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m4 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: vload_nxv16i32 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv16i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: vload_nxv1i64 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv1i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv2i64 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nxv4i64 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv4i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m4 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: vload_nxv8i64 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv8i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: vload_nxv16i8_align1 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv16i8_align1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 1) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 1) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nxv16i8_align2 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv16i8_align2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 2) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nxv16i8_align16 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv16i8_align16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nxv16i8_align64 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv16i8_align64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 64) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nxv4i16_align1 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv4i16_align1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 1) + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[LOAD]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 1) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv4i16_align2 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv4i16_align2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 2) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv4i16_align4 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv4i16_align4 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 4) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv4i16_align8 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv4i16_align8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv4i16_align16 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv4i16_align16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 16) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv2i32_align2 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i32_align2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[LOAD]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 2) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv2i32_align4 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i32_align4 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 4) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv2i32_align8 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i32_align8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv2i32_align16 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i32_align16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 16) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv2i32_align256 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i32_align256 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 256) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 256) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nxv2i64_align4 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i64_align4 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[LOAD]]() + ; CHECK-NEXT: $v8m2 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 4) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nxv2i64_align8 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i64_align8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 8) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nxv2i64_align16 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i64_align16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nxv2i64_align32 +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nxv2i64_align32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 32) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-or.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-or.mir new file mode 100644 index 0000000..22c2258 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-or.mir @@ -0,0 +1,399 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: test_nxv1i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_OR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_OR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv64i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_OR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_OR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_OR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_OR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_OR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_OR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_OR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_OR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_OR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv4i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_OR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv8i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_() = G_OR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[OR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_OR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-select.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-select.mir new file mode 100644 index 0000000..6e1d4aa --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-select.mir @@ -0,0 +1,400 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: select_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv1i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv2i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv4i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv8i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv16i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m2 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: select_nxv32i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv32i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m4 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: select_nxv64i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv64i8 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: select_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv1i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv2i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv4i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv8i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m2 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: select_nxv16i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv16i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m4 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: select_nxv32i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv32i16 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: select_nxv1i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv1i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv2i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv2i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv4i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m2 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: select_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv8i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m4 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: select_nxv16i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv16i32 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: select_nxv1i64 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv1i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv2i64 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv2i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m2 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: select_nxv4i64 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv4i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m4 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: select_nxv8i64 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv8i64 + ; CHECK: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sext.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sext.mir new file mode 100644 index 0000000..daf0afa --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sext.mir @@ -0,0 +1,1545 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV32 %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV64 %s + +# Extend from s1 element vectors +--- +name: sext_nxv1i8_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv1i8_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i8_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv1i16_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv1i16_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i16_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv1i32_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv1i32_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i32_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv1i64_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv1i64_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i64_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i8_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv2i8_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv2i8_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i16_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv2i16_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv2i16_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i32_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv2i32_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv2i32_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i64_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv2i64_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv2i64_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i8_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv4i8_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv4i8_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv4i16_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv4i16_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv4i16_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv4i32_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv4i32_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv4i32_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i64_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv4i64_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv4i64_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i8_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv8i8_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv8i8_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv8i16_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv8i16_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv8i16_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv8i32_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv8i32_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv8i32_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i64_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv8i64_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv8i64_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: sext_nxv16i8_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv16i8_nxv16i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv16i8_nxv16i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv16i16_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv16i16_nxv16i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv16i16_nxv16i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv16i32_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv16i32_nxv16i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv16i32_nxv16i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: sext_nxv32i8_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv32i8_nxv32i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv32i8_nxv32i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv32i16_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv32i16_nxv32i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv32i16_nxv32i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: sext_nxv64i8_nxv64i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv64i8_nxv64i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv64i8_nxv64i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v0 + %0:_() = G_SEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... + +# Extend from s8 element vectors +--- +name: sext_nxv1i16_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv1i16_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i16_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv1i32_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv1i32_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i32_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv1i64_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv1i64_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i64_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i16_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv2i16_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv2i16_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i32_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv2i32_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv2i32_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i64_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv2i64_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv2i64_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i16_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv4i16_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv4i16_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv4i32_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv4i32_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv4i32_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i64_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv4i64_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv4i64_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i16_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv8i16_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv8i16_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv8i32_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv8i32_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv8i32_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i64_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv8i64_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv8i64_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: sext_nxv16i16_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv16i16_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv16i16_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8m2 + %0:_() = G_SEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv16i32_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv16i32_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv16i32_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m2 + %0:_() = G_SEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: sext_nxv32i16_nxv32i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv32i16_nxv32i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv32i16_nxv32i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m4 + %0:_() = G_SEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... + +# Extend from s16 element vectors +--- +name: sext_nxv1i32_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv1i32_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i32_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv1i64_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv1i64_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i64_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i32_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv2i32_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv2i32_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i64_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv2i64_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv2i64_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i32_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv4i32_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv4i32_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i64_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv4i64_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv4i64_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i32_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv8i32_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv8i32_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8m2 + %0:_() = G_SEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i64_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv8i64_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv8i64_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m2 + %0:_() = G_SEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: sext_nxv16i32_nxv16i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv16i32_nxv16i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv16i32_nxv16i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m4 + %0:_() = G_SEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... + +# Extend from s32 element vectors +--- +name: sext_nxv1i64_nxv1i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv1i64_nxv1i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i64_nxv1i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i64_nxv2i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv2i64_nxv2i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv2i64_nxv2i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_SEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i64_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv4i64_nxv4i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv4i64_nxv4i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8m2 + %0:_() = G_SEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i64_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv8i64_nxv8i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[SEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv8i64_nxv8i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_() = G_SEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[SEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m4 + %0:_() = G_SEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir new file mode 100644 index 0000000..5b14dcd --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir @@ -0,0 +1,701 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: splatvector_nxv1i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv1i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv1i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv1i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv2i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv2i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv2i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv2i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv4i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv4i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv4i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv4i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv8i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv8i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv8i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv8i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv16i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv16i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv16i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv16i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv32i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv32i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv32i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv32i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv32i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv32i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv64i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv64i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv64i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv64i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv64i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv64i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... + +--- +name: splatvector_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s8) = G_CONSTANT i8 0 + %2:_() = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... + +--- +name: splatvector_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s8) = G_CONSTANT i8 0 + %2:_() = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s8) = G_CONSTANT i8 0 + %2:_() = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s8) = G_CONSTANT i8 0 + %2:_() = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s8) = G_CONSTANT i8 0 + %2:_() = G_SPLAT_VECTOR %1(s8) + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s16) = G_CONSTANT i16 0 + %2:_() = G_SPLAT_VECTOR %1(s16) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s16) = G_CONSTANT i16 0 + %2:_() = G_SPLAT_VECTOR %1(s16) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s16) = G_CONSTANT i16 0 + %2:_() = G_SPLAT_VECTOR %1(s16) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s16) = G_CONSTANT i16 0 + %2:_() = G_SPLAT_VECTOR %1(s16) + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv16i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s16) = G_CONSTANT i16 0 + %2:_() = G_SPLAT_VECTOR %1(s16) + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: splatvector_nxv1i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_CONSTANT i32 0 + %2:_() = G_SPLAT_VECTOR %1(s32) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv2i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_CONSTANT i32 0 + %2:_() = G_SPLAT_VECTOR %1(s32) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s32) = G_CONSTANT i32 0 + %2:_() = G_SPLAT_VECTOR %1(s32) + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s32) = G_CONSTANT i32 0 + %2:_() = G_SPLAT_VECTOR %1(s32) + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: splatvector_nxv16i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_(s32) = G_CONSTANT i32 0 + %2:_() = G_SPLAT_VECTOR %1(s32) + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir new file mode 100644 index 0000000..8ccc231 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir @@ -0,0 +1,788 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: splatvector_nxv1i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv1i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv1i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv1i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv2i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv2i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv2i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv2i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv4i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv4i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv4i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv4i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv8i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv8i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv8i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv8i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv16i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv16i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv16i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv16i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv32i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv32i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv32i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv32i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv32i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv32i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv64i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv64i1_0 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv64i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv64i1_1 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_() = G_VMSET_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_() = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv64i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv64i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[AND1]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_() = G_ICMP intpred(ne), [[SPLAT_VECTOR]](), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_() = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2() + PseudoRET implicit $v0 +... + +--- +name: splatvector_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i8 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_(s8) = G_CONSTANT i8 0 + %2:_() = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... + +--- +name: splatvector_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i8 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_(s8) = G_CONSTANT i8 0 + %2:_() = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i8 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_(s8) = G_CONSTANT i8 0 + %2:_() = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i8 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_(s8) = G_CONSTANT i8 0 + %2:_() = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i8 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + %1:_(s8) = G_CONSTANT i8 0 + %2:_() = G_SPLAT_VECTOR %1(s8) + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i16 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_(s16) = G_CONSTANT i16 0 + %2:_() = G_SPLAT_VECTOR %1(s16) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i16 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_(s16) = G_CONSTANT i16 0 + %2:_() = G_SPLAT_VECTOR %1(s16) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i16 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_(s16) = G_CONSTANT i16 0 + %2:_() = G_SPLAT_VECTOR %1(s16) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i16 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + %1:_(s16) = G_CONSTANT i16 0 + %2:_() = G_SPLAT_VECTOR %1(s16) + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv16i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i16 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + %1:_(s16) = G_CONSTANT i16 0 + %2:_() = G_SPLAT_VECTOR %1(s16) + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: splatvector_nxv1i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i32 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_(s32) = G_CONSTANT i32 0 + %2:_() = G_SPLAT_VECTOR %1(s32) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv2i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i32 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_(s32) = G_CONSTANT i32 0 + %2:_() = G_SPLAT_VECTOR %1(s32) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i32 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + %1:_(s32) = G_CONSTANT i32 0 + %2:_() = G_SPLAT_VECTOR %1(s32) + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i32 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + %1:_(s32) = G_CONSTANT i32 0 + %2:_() = G_SPLAT_VECTOR %1(s32) + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: splatvector_nxv16i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i32 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + %1:_(s32) = G_CONSTANT i32 0 + %2:_() = G_SPLAT_VECTOR %1(s32) + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: splatvector_nxv1i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i64 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_(s64) = G_CONSTANT i64 0 + %2:_() = G_SPLAT_VECTOR %1(s64) + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv2i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i64 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + %1:_(s64) = G_CONSTANT i64 0 + %2:_() = G_SPLAT_VECTOR %1(s64) + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv4i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i64 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + %1:_(s64) = G_CONSTANT i64 0 + %2:_() = G_SPLAT_VECTOR %1(s64) + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: splatvector_nxv8i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i64 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + %1:_(s64) = G_CONSTANT i64 0 + %2:_() = G_SPLAT_VECTOR %1(s64) + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-s64-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-s64-rv32.mir new file mode 100644 index 0000000..f97e27b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-s64-rv32.mir @@ -0,0 +1,112 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=HasF64 %s +# RUN: llc -mtriple=riscv32 -mattr=+zve64x -run-pass=legalizer %s -o - | FileCheck --check-prefix=NoF64 %s + +--- +name: splatvector_nxv1i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; HasF64-LABEL: name: splatvector_nxv1i64 + ; HasF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; HasF64-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[DEF]](s32), [[DEF]](s32) + ; HasF64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; HasF64-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; HasF64-NEXT: PseudoRET implicit $v8 + ; + ; NoF64-LABEL: name: splatvector_nxv1i64 + ; NoF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; NoF64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_() = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF1]], [[DEF]](s32), [[DEF]], [[C]](s32) + ; NoF64-NEXT: $v8 = COPY [[SPLAT_VECTOR_SPLIT_I64_VL]]() + ; NoF64-NEXT: PseudoRET implicit $v8 + %0:_(s64) = G_IMPLICIT_DEF + %1:_() = G_SPLAT_VECTOR %0(s64) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv2i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; HasF64-LABEL: name: splatvector_nxv2i64 + ; HasF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; HasF64-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[DEF]](s32), [[DEF]](s32) + ; HasF64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; HasF64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; HasF64-NEXT: PseudoRET implicit $v8m2 + ; + ; NoF64-LABEL: name: splatvector_nxv2i64 + ; NoF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; NoF64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_() = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF1]], [[DEF]](s32), [[DEF]], [[C]](s32) + ; NoF64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR_SPLIT_I64_VL]]() + ; NoF64-NEXT: PseudoRET implicit $v8m2 + %0:_(s64) = G_IMPLICIT_DEF + %1:_() = G_SPLAT_VECTOR %0(s64) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv4i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; HasF64-LABEL: name: splatvector_nxv4i64 + ; HasF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; HasF64-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[DEF]](s32), [[DEF]](s32) + ; HasF64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; HasF64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; HasF64-NEXT: PseudoRET implicit $v8m4 + ; + ; NoF64-LABEL: name: splatvector_nxv4i64 + ; NoF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; NoF64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_() = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF1]], [[DEF]](s32), [[DEF]], [[C]](s32) + ; NoF64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR_SPLIT_I64_VL]]() + ; NoF64-NEXT: PseudoRET implicit $v8m4 + %0:_(s64) = G_IMPLICIT_DEF + %1:_() = G_SPLAT_VECTOR %0(s64) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: splatvector_nxv8i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; HasF64-LABEL: name: splatvector_nxv8i64 + ; HasF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; HasF64-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[DEF]](s32), [[DEF]](s32) + ; HasF64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; HasF64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; HasF64-NEXT: PseudoRET implicit $v8m8 + ; + ; NoF64-LABEL: name: splatvector_nxv8i64 + ; NoF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_() = G_VMSET_VL [[C]](s32) + ; NoF64-NEXT: [[DEF1:%[0-9]+]]:_() = G_IMPLICIT_DEF + ; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_() = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF1]], [[DEF]](s32), [[DEF]], [[C]](s32) + ; NoF64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR_SPLIT_I64_VL]]() + ; NoF64-NEXT: PseudoRET implicit $v8m8 + %0:_(s64) = G_IMPLICIT_DEF + %1:_() = G_SPLAT_VECTOR %0(s64) + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store-rv32.mir new file mode 100644 index 0000000..a93cce6 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store-rv32.mir @@ -0,0 +1,79 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: vstore_nx1ptr +body: | + bb.1: + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx1ptr + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store ()) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store (), align 4) + PseudoRET + +... +--- +name: vstore_nx2ptr +body: | + bb.1: + liveins: $x10, $v8 + + ; CHECK-LABEL: name: vstore_nx2ptr + ; CHECK: liveins: $x10, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store ()) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store (), align 8) + PseudoRET + +... +--- +name: vstore_nx8ptr +body: | + bb.1: + liveins: $x10, $v8m4 + + ; CHECK-LABEL: name: vstore_nx8ptr + ; CHECK: liveins: $x10, $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store ()) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m4 + G_STORE %1(), %0(p0) :: (store (), align 32) + PseudoRET + +... +--- +name: vstore_nx16ptr +body: | + bb.1: + liveins: $x10, $v8m8 + + ; CHECK-LABEL: name: vstore_nx16ptr + ; CHECK: liveins: $x10, $v8m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store (), align 64) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m8 + G_STORE %1(), %0(p0) :: (store (), align 64) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store-rv64.mir new file mode 100644 index 0000000..3373ed4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store-rv64.mir @@ -0,0 +1,60 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: vstore_nx1ptr +body: | + bb.1: + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx1ptr + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store ()) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store (), align 8) + PseudoRET + +... +--- +name: vstore_nx2ptr +body: | + bb.1: + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx2ptr + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store ()) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store (), align 16) + PseudoRET + +... +--- +name: vstore_nx8ptr +body: | + bb.1: + liveins: $x10, $v8m8 + + ; CHECK-LABEL: name: vstore_nx8ptr + ; CHECK: liveins: $x10, $v8m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store ()) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m8 + G_STORE %1(), %0(p0) :: (store (), align 64) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store.mir new file mode 100644 index 0000000..4bb4eb5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store.mir @@ -0,0 +1,971 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- | + + define void @vstore_nx1i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 1 + ret void + } + + define void @vstore_nx2i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 2 + ret void + } + + define void @vstore_nx4i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx8i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx16i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx32i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 32 + ret void + } + + define void @vstore_nx64i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 64 + ret void + } + + define void @vstore_nx1i16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 2 + ret void + } + + define void @vstore_nx2i16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx4i16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx8i16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx16i16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 32 + ret void + } + + define void @vstore_nx32i16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 64 + ret void + } + + define void @vstore_nx1i32(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx2i32(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx4i32(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx8i32(ptr %pa, %b) #0 { + store %b, ptr %pa, align 32 + ret void + } + + define void @vstore_nx16i32(ptr %pa, %b) #0 { + store %b, ptr %pa, align 64 + ret void + } + + define void @vstore_nx1i64(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx2i64(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx4i64(ptr %pa, %b) #0 { + store %b, ptr %pa, align 32 + ret void + } + + define void @vstore_nx8i64(ptr %pa, %b) #0 { + store %b, ptr %pa, align 64 + ret void + } + + define void @vstore_nx16i8_align1(ptr %pa, %b) #0 { + store %b, ptr %pa, align 1 + ret void + } + + define void @vstore_nx16i8_align2(ptr %pa, %b) #0 { + store %b, ptr %pa, align 2 + ret void + } + + define void @vstore_nx16i8_align16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx16i8_align64(ptr %pa, %b) #0 { + store %b, ptr %pa, align 64 + ret void + } + + define void @vstore_nx4i16_align1(ptr %pa, %b) #0 { + store %b, ptr %pa, align 1 + ret void + } + + define void @vstore_nx4i16_align2(ptr %pa, %b) #0 { + store %b, ptr %pa, align 2 + ret void + } + + define void @vstore_nx4i16_align4(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx4i16_align8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx4i16_align16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx2i32_align2(ptr %pa, %b) #0 { + store %b, ptr %pa, align 2 + ret void + } + + define void @vstore_nx2i32_align4(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx2i32_align8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx2i32_align16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx2i32_align256(ptr %pa, %b) #0 { + store %b, ptr %pa, align 256 + ret void + } + + define void @vstore_nx2i64_align4(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx2i64_align8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx2i64_align16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx2i64_align32(ptr %pa, %b) #0 { + store %b, ptr %pa, align 32 + ret void + } + + attributes #0 = { "target-features"="+v" } + +... +--- +name: vstore_nx1i8 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx1i8 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2i8 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i8 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx4i8 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i8 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx8i8 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx8i8 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx16i8 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx16i8 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx32i8 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m4 + + ; CHECK-LABEL: name: vstore_nx32i8 + ; CHECK: liveins: $x10, $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m4 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx64i8 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m8 + + ; CHECK-LABEL: name: vstore_nx64i8 + ; CHECK: liveins: $x10, $v8m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx1i16 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx1i16 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2i16 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i16 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx4i16 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i16 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx8i16 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx8i16 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx16i16 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m4 + + ; CHECK-LABEL: name: vstore_nx16i16 + ; CHECK: liveins: $x10, $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m4 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx32i16 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m8 + + ; CHECK-LABEL: name: vstore_nx32i16 + ; CHECK: liveins: $x10, $v8m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx1i32 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx1i32 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2i32 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i32 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx4i32 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx4i32 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx8i32 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m4 + + ; CHECK-LABEL: name: vstore_nx8i32 + ; CHECK: liveins: $x10, $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m4 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx16i32 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m8 + + ; CHECK-LABEL: name: vstore_nx16i32 + ; CHECK: liveins: $x10, $v8m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx1i64 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx1i64 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2i64 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx2i64 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx4i64 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m4 + + ; CHECK-LABEL: name: vstore_nx4i64 + ; CHECK: liveins: $x10, $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m4 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx8i64 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m8 + + ; CHECK-LABEL: name: vstore_nx8i64 + ; CHECK: liveins: $x10, $v8m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx16i8_align1 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx16i8_align1 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 1) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 1) + PseudoRET + +... +--- +name: vstore_nx16i8_align2 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx16i8_align2 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 2) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 2) + PseudoRET + +... +--- +name: vstore_nx16i8_align16 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx16i8_align16 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx16i8_align64 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx16i8_align64 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 64) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 64) + PseudoRET + +... +--- +name: vstore_nx4i16_align1 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i16_align1 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[COPY1]]() + ; CHECK-NEXT: G_STORE [[BITCAST]](), [[COPY]](p0) :: (store () into %ir.pa, align 1) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 1) + PseudoRET + +... +--- +name: vstore_nx4i16_align2 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i16_align2 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 2) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 2) + PseudoRET + +... +--- +name: vstore_nx4i16_align4 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i16_align4 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 4) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 4) + PseudoRET + +... +--- +name: vstore_nx4i16_align8 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i16_align8 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx4i16_align16 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i16_align16 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 16) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 16) + PseudoRET + +... +--- +name: vstore_nx2i32_align2 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i32_align2 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[COPY1]]() + ; CHECK-NEXT: G_STORE [[BITCAST]](), [[COPY]](p0) :: (store () into %ir.pa, align 2) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 2) + PseudoRET + +... +--- +name: vstore_nx2i32_align4 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i32_align4 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 4) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 4) + PseudoRET + +... +--- +name: vstore_nx2i32_align8 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i32_align8 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2i32_align16 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i32_align16 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 16) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 16) + PseudoRET + +... +--- +name: vstore_nx2i32_align256 +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i32_align256 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 256) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 256) + PseudoRET + +... +--- +name: vstore_nx2i64_align4 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx2i64_align4 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_() = G_BITCAST [[COPY1]]() + ; CHECK-NEXT: G_STORE [[BITCAST]](), [[COPY]](p0) :: (store () into %ir.pa, align 4) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 4) + PseudoRET + +... +--- +name: vstore_nx2i64_align8 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx2i64_align8 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 8) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 8) + PseudoRET + +... +--- +name: vstore_nx2i64_align16 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx2i64_align16 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2i64_align32 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx2i64_align32 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 32) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 32) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sub.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sub.mir new file mode 100644 index 0000000..eb961b8 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sub.mir @@ -0,0 +1,399 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: test_nxv1i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv64i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv4i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv8i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:_() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir new file mode 100644 index 0000000..ac36a4f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir @@ -0,0 +1,226 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: test_1_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_1_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 1 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_2_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_2_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 2 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_3_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_3_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 3 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_4_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_4_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 4 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_8_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_8_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 8 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_16_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_16_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 16 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_40_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_40_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[READ_VLENB]], [[C]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 40 + $x10 = COPY %0 + PseudoRET implicit $x10 +... + +--- +name: test_1_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_1_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 1 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... +--- +name: test_2_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_2_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 2 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... +--- +name: test_3_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_3_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 3 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... +--- +name: test_4_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_4_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 4 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... +--- +name: test_8_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_8_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 8 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... +--- +name: test_16_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_16_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 16 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... +--- +name: test_40_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_40_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 40 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 40 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir new file mode 100644 index 0000000..1a17ecf --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir @@ -0,0 +1,109 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: test_1 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_1 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 1 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_2 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_2 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 2 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_3 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_3 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C]](s64) + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[LSHR]], [[C]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 3 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_4 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_4 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = exact G_LSHR [[READ_VLENB]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 4 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_8 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 8 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_16 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[READ_VLENB]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 16 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_40 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_40 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[READ_VLENB]], [[C]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 40 + $x10 = COPY %0 + PseudoRET implicit $x10 +... + + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir new file mode 100644 index 0000000..8a34521 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir @@ -0,0 +1,399 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s +--- +name: test_nxv1i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv16i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_XOR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv32i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_XOR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv64i8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv64i8 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_XOR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv8i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_XOR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv16i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_XOR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv32i16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv32i16 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_XOR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv4i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_XOR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv8i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_XOR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv16i32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv16i32 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_XOR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: test_nxv1i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv1i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v9 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_XOR %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: test_nxv2i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv2i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v10m2 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_XOR %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: test_nxv4i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv4i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v12m4 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_XOR %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: test_nxv8i64 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_nxv8i64 + ; CHECK: [[COPY:%[0-9]+]]:_() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_() = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[XOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_XOR %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-zext.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-zext.mir new file mode 100644 index 0000000..34c795d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-zext.mir @@ -0,0 +1,1545 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV32 %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV64 %s + +# Extend from s1 element vectors +--- +name: zext_nxv1i8_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i8_nxv1i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i8_nxv1i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv1i16_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i16_nxv1i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i16_nxv1i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv1i32_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i32_nxv1i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i32_nxv1i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv1i64_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i64_nxv1i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i64_nxv1i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i8_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i8_nxv2i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv2i8_nxv2i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i16_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i16_nxv2i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv2i16_nxv2i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i32_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i32_nxv2i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv2i32_nxv2i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i64_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i64_nxv2i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv2i64_nxv2i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i8_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i8_nxv4i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv4i8_nxv4i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv4i16_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i16_nxv4i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv4i16_nxv4i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv4i32_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i32_nxv4i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv4i32_nxv4i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i64_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i64_nxv4i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv4i64_nxv4i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i8_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i8_nxv8i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv8i8_nxv8i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv8i16_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i16_nxv8i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv8i16_nxv8i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv8i32_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i32_nxv8i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv8i32_nxv8i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i64_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i64_nxv8i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv8i64_nxv8i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: zext_nxv16i8_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv16i8_nxv16i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv16i8_nxv16i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv16i16_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv16i16_nxv16i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv16i16_nxv16i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv16i32_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv16i32_nxv16i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv16i32_nxv16i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: zext_nxv32i8_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv32i8_nxv32i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv32i8_nxv32i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv32i16_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv32i16_nxv32i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv32i16_nxv32i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: zext_nxv64i8_nxv64i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv64i8_nxv64i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv64i8_nxv64i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_() = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_() = G_SELECT [[COPY]](), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... + +# Extend from s8 element vectors +--- +name: zext_nxv1i16_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i16_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i16_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv1i32_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i32_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i32_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv1i64_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i64_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i64_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i16_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i16_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv2i16_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i32_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i32_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv2i32_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i64_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i64_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv2i64_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i16_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i16_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv4i16_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv4i32_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i32_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv4i32_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i64_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i64_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv4i64_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i16_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i16_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv8i16_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv8i32_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i32_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv8i32_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i64_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i64_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv8i64_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: zext_nxv16i16_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv16i16_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv16i16_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8m2 + %0:_() = G_ZEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv16i32_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv16i32_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv16i32_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m2 + %0:_() = G_ZEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: zext_nxv32i16_nxv32i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv32i16_nxv32i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv32i16_nxv32i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m4 + %0:_() = G_ZEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... + +# Extend from s16 element vectors +--- +name: zext_nxv1i32_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i32_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i32_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv1i64_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i64_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i64_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i32_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i32_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv2i32_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i64_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i64_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv2i64_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i32_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i32_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv4i32_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i64_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i64_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv4i64_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i32_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i32_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv8i32_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8m2 + %0:_() = G_ZEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i64_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i64_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv8i64_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m4 + %0:_() = G_ZEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: zext_nxv16i32_nxv16i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv16i32_nxv16i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv16i32_nxv16i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m4 + %0:_() = G_ZEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... + +# Extend from s32 element vectors +--- +name: zext_nxv1i64_nxv1i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i64_nxv1i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i64_nxv1i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i64_nxv2i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i64_nxv2i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m2 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv2i64_nxv2i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m2 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_() = COPY $v8 + %0:_() = G_ZEXT %1() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i64_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i64_nxv4i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m4 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv4i64_nxv4i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m4 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_() = COPY $v8m2 + %0:_() = G_ZEXT %1() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i64_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i64_nxv8i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV32-NEXT: $v8m8 = COPY [[ZEXT]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv8i64_nxv8i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_() = G_ZEXT [[COPY]]() + ; RV64-NEXT: $v8m8 = COPY [[ZEXT]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_() = COPY $v8m4 + %0:_() = G_ZEXT %1() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir new file mode 100644 index 0000000..1b6684d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir @@ -0,0 +1,461 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s + +--- +name: add_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: add_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[ADD]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_ADD %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: sub_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: sub_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SUB]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SUB %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: shl_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: shl_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[COPY1]](s32) + ; RV32I-NEXT: $x10 = COPY [[SHL]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SHL %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: ashr_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: ashr_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]](s32) + ; RV32I-NEXT: $x10 = COPY [[ASHR]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_ASHR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: lshr_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: lshr_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[COPY1]](s32) + ; RV32I-NEXT: $x10 = COPY [[LSHR]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_LSHR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: and_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: and_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[AND]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_AND %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: or_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: or_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[OR]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_OR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: xor_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: xor_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[XOR]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_XOR %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: mul_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: mul_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[MUL]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_MUL %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: sdiv_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[SDIV:%[0-9]+]]:gprb(s32) = G_SDIV [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SDIV]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SDIV %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: srem_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: srem_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[SREM:%[0-9]+]]:gprb(s32) = G_SREM [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SREM]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SREM %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: smulh_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: smulh_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[SMULH:%[0-9]+]]:gprb(s32) = G_SMULH [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SMULH]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SMULH %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: udiv_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: udiv_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[UDIV:%[0-9]+]]:gprb(s32) = G_UDIV [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[UDIV]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_UDIV %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: urem_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: urem_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[UREM:%[0-9]+]]:gprb(s32) = G_UREM [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[UREM]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_UREM %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: umulh_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: umulh_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[UMULH:%[0-9]+]]:gprb(s32) = G_UMULH [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[UMULH]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_UMULH %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: icmp_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: icmp_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[ICMP]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_ICMP intpred(eq), %0(s32), %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: icmp_ptr +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: icmp_ptr + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[ICMP]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + %2:_(s32) = G_ICMP intpred(eq), %0(p0), %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: gep +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: gep + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s32) + ; RV32I-NEXT: $x10 = COPY [[PTR_ADD]](p0) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(p0) = G_PTR_ADD %0, %1(s32) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... +--- +name: ptrtoint +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: ptrtoint + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV32I-NEXT: [[PTRTOINT:%[0-9]+]]:gprb(s32) = G_PTRTOINT [[COPY]](p0) + ; RV32I-NEXT: $x10 = COPY [[PTRTOINT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_PTRTOINT %0(p0) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: inttoprt +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: inttoprt + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[INTTOPTR:%[0-9]+]]:gprb(p0) = G_INTTOPTR [[COPY]](s32) + ; RV32I-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(p0) = G_INTTOPTR %0(s32) + $x10 = COPY %1(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir new file mode 100644 index 0000000..cef929f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir @@ -0,0 +1,482 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- +name: add_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: add_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[ADD:%[0-9]+]]:gprb(s64) = G_ADD [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[ADD]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_ADD %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sub_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: sub_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:gprb(s64) = G_SUB [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SUB %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: shl_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: shl_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:gprb(s64) = G_SHL [[COPY]], [[COPY1]](s64) + ; RV64I-NEXT: $x10 = COPY [[SHL]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SHL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: ashr_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: ashr_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:gprb(s64) = G_ASHR [[COPY]], [[COPY1]](s64) + ; RV64I-NEXT: $x10 = COPY [[ASHR]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_ASHR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: lshr_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: lshr_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[COPY]], [[COPY1]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_LSHR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: and_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: and_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[AND]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_AND %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: or_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: or_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[OR:%[0-9]+]]:gprb(s64) = G_OR [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[OR]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_OR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: xor_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: xor_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:gprb(s64) = G_XOR [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[XOR]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_XOR %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: mul_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: mul_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[MUL:%[0-9]+]]:gprb(s64) = G_MUL [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[MUL]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_MUL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sdiv_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: sdiv_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[SDIV:%[0-9]+]]:gprb(s64) = G_SDIV [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SDIV]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SDIV %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: srem_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: srem_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[SREM:%[0-9]+]]:gprb(s64) = G_SREM [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SREM]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SREM %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: smulh_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: smulh_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[SMULH:%[0-9]+]]:gprb(s64) = G_SMULH [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SMULH]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SMULH %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: udiv_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: udiv_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[UDIV:%[0-9]+]]:gprb(s64) = G_UDIV [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[UDIV]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_UDIV %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: urem_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: urem_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[UREM:%[0-9]+]]:gprb(s64) = G_UREM [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[UREM]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_UREM %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: umulh_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: umulh_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[UMULH:%[0-9]+]]:gprb(s64) = G_UMULH [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[UMULH]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_UMULH %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: icmp_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: icmp_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[ICMP]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_ICMP intpred(eq), %0(s64), %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: icmp_ptr +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: icmp_ptr + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[ICMP]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + %2:_(s64) = G_ICMP intpred(eq), %0(p0), %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: sext_inreg_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: sext_inreg_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:gprb(s64) = G_SEXT_INREG [[COPY]], 32 + ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = G_SEXT_INREG %0, 32 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: gep +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: gep + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s64) + ; RV64I-NEXT: $x10 = COPY [[PTR_ADD]](p0) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(p0) = G_PTR_ADD %0, %1(s64) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 + +... +--- +name: ptrtoint +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: ptrtoint + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[PTRTOINT:%[0-9]+]]:gprb(s64) = G_PTRTOINT [[COPY]](p0) + ; RV64I-NEXT: $x10 = COPY [[PTRTOINT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_PTRTOINT %0(p0) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: inttoprt +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: inttoprt + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[INTTOPTR:%[0-9]+]]:gprb(p0) = G_INTTOPTR [[COPY]](s64) + ; RV64I-NEXT: $x10 = COPY [[INTTOPTR]](p0) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(p0) = G_INTTOPTR %0(s64) + $x10 = COPY %1(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir new file mode 100644 index 0000000..1296d5f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir @@ -0,0 +1,71 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s + +--- +name: virt_to_phys +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + + ; RV32I-LABEL: name: virt_to_phys + ; RV32I: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: $x10 = COPY [[C]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_CONSTANT i32 1 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: phys_to_phys +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: phys_to_phys + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: $x10 = COPY $x11 + ; RV32I-NEXT: PseudoRET implicit $x10 + $x10 = COPY $x11 + PseudoRET implicit $x10 + +... +--- +name: virt_to_virt +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + + ; RV32I-LABEL: name: virt_to_virt + ; RV32I: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY [[C]](s32) + ; RV32I-NEXT: PseudoRET + %0:_(s32) = G_CONSTANT i32 1 + %1:_(s32) = COPY %0(s32) + PseudoRET + +... +--- +name: phys_to_virt +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: phys_to_virt + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: PseudoRET + %0:_(s32) = COPY $x10 + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir new file mode 100644 index 0000000..98c0707 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir @@ -0,0 +1,71 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- +name: virt_to_phys +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + + ; RV64I-LABEL: name: virt_to_phys + ; RV64I: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: $x10 = COPY [[C]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_CONSTANT i64 1 + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: phys_to_phys +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: phys_to_phys + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: $x10 = COPY $x11 + ; RV64I-NEXT: PseudoRET implicit $x10 + $x10 = COPY $x11 + PseudoRET implicit $x10 + +... +--- +name: virt_to_virt +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + + ; RV64I-LABEL: name: virt_to_virt + ; RV64I: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY [[C]](s64) + ; RV64I-NEXT: PseudoRET + %0:_(s64) = G_CONSTANT i64 1 + %1:_(s64) = COPY %0(s64) + PseudoRET + +... +--- +name: phys_to_virt +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: phys_to_virt + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: PseudoRET + %0:_(s64) = COPY $x10 + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir new file mode 100644 index 0000000..9cc0b57 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir @@ -0,0 +1,71 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- +name: anyext_i32_i64 +legalized: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: anyext_i32_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[TRUNC]](s32) + ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %5:_(s64) = G_ANYEXT %0(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: sext_i32_i64 +legalized: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: sext_i32_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:gprb(s64) = G_SEXT [[TRUNC]](s32) + ; RV64I-NEXT: $x10 = COPY [[SEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %5:_(s64) = G_SEXT %0(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: zext_i32_i64 +legalized: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV64I-LABEL: name: zext_i32_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:gprb(s64) = G_ZEXT [[TRUNC]](s32) + ; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %2:_(s64) = COPY $x10 + %0:_(s32) = G_TRUNC %2(s64) + %5:_(s64) = G_ZEXT %0(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir new file mode 100644 index 0000000..2a3f8bd --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir @@ -0,0 +1,27 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: fcmp_f16 +legalized: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %4:_(s32) = G_FCMP floatpred(oeq), %0(s16), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir new file mode 100644 index 0000000..518ef44 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir @@ -0,0 +1,27 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: fcmp_f16 +legalized: true +body: | + bb.1: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcmp_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:gprb(s64) = G_FCMP floatpred(oeq), [[COPY]](s16), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %4:_(s64) = G_FCMP floatpred(oeq), %0(s16), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir new file mode 100644 index 0000000..7020a0b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv32.mir @@ -0,0 +1,49 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: fcmp_f32 +legalized: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %4:_(s32) = G_FCMP floatpred(oeq), %0(s32), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: fcmp_f64 +legalized: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %4:_(s32) = G_FCMP floatpred(oeq), %0(s64), %1 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir new file mode 100644 index 0000000..48f7c4f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-rv64.mir @@ -0,0 +1,49 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: fcmp_f32 +legalized: true +body: | + bb.1: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcmp_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:gprb(s64) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %4:_(s64) = G_FCMP floatpred(oeq), %0(s32), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: fcmp_f64 +legalized: true +body: | + bb.1: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcmp_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCMP:%[0-9]+]]:gprb(s64) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[FCMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %4:_(s64) = G_FCMP floatpred(oeq), %0(s64), %1 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir new file mode 100644 index 0000000..1ef5c48 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir @@ -0,0 +1,349 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: fadd_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fadd_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FADD]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FADD %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fsub_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fsub_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:fprb(s16) = G_FSUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FSUB]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FSUB %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fmul_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fmul_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:fprb(s16) = G_FMUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FMUL]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FMUL %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fdiv_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fdiv_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[FDIV:%[0-9]+]]:fprb(s16) = G_FDIV [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FDIV]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FDIV %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fma_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h, $f12_h + + ; CHECK-LABEL: name: fma_f16 + ; CHECK: liveins: $f10_h, $f11_h, $f12_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s16) = COPY $f12_h + ; CHECK-NEXT: [[FMA:%[0-9]+]]:fprb(s16) = G_FMA [[COPY]], [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $f10_h = COPY [[FMA]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = COPY $f12_h + %3:_(s16) = G_FMA %0, %1, %2 + $f10_h = COPY %3(s16) + PseudoRET implicit $f10_h + +... +--- +name: fneg_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: fneg_f16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[FNEG:%[0-9]+]]:fprb(s16) = G_FNEG [[COPY]] + ; CHECK-NEXT: $f10_h = COPY [[FNEG]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = G_FNEG %0 + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: fabs_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: fabs_f16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[FABS:%[0-9]+]]:fprb(s16) = G_FABS [[COPY]] + ; CHECK-NEXT: $f10_h = COPY [[FABS]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = G_FABS %0 + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: fsqrt_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: fsqrt_f16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:fprb(s16) = G_FSQRT [[COPY]] + ; CHECK-NEXT: $f10_h = COPY [[FSQRT]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = G_FSQRT %0 + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: fmaxnum_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fmaxnum_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:fprb(s16) = G_FMAXNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FMAXNUM]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FMAXNUM %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fminnum_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fminnum_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:fprb(s16) = G_FMINNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FMINNUM]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FMINNUM %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fcopysign_f16_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_h + + ; CHECK-LABEL: name: fcopysign_f16_f16 + ; CHECK: liveins: $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16) + ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s16) = COPY $f11_h + %2:_(s16) = G_FCOPYSIGN %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fcopysign_f16_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_f + + ; CHECK-LABEL: name: fcopysign_f16_f32 + ; CHECK: liveins: $f10_h, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s32) = COPY $f11_f + %2:_(s16) = G_FCOPYSIGN %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fcopysign_f32_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_h + + ; CHECK-LABEL: name: fcopysign_f32_f16 + ; CHECK: liveins: $f10_f, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16) + ; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s16) = COPY $f11_h + %2:_(s32) = G_FCOPYSIGN %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fcopysign_f16_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_h, $f11_d + + ; CHECK-LABEL: name: fcopysign_f16_f64 + ; CHECK: liveins: $f10_h, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s16) = COPY $f10_h + %1:_(s64) = COPY $f11_d + %2:_(s16) = G_FCOPYSIGN %0, %1 + $f10_h = COPY %2(s16) + PseudoRET implicit $f10_h + +... +--- +name: fcopysign_f64_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_h + + ; CHECK-LABEL: name: fcopysign_f64_f16 + ; CHECK: liveins: $f10_d, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s64) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16) + ; CHECK-NEXT: $f10_d = COPY [[FCOPYSIGN]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s16) = COPY $f11_h + %2:_(s64) = G_FCOPYSIGN %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir new file mode 100644 index 0000000..2801faf --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir @@ -0,0 +1,552 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: fadd_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fadd_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FADD]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FADD %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fsub_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fsub_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:fprb(s32) = G_FSUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FSUB]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FSUB %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fmul_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fmul_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:fprb(s32) = G_FMUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FMUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FMUL %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fdiv_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fdiv_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[FDIV:%[0-9]+]]:fprb(s32) = G_FDIV [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FDIV]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FDIV %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fma_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f, $f12_f + + ; CHECK-LABEL: name: fma_f32 + ; CHECK: liveins: $f10_f, $f11_f, $f12_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f12_f + ; CHECK-NEXT: [[FMA:%[0-9]+]]:fprb(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $f10_f = COPY [[FMA]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = COPY $f12_f + %3:_(s32) = G_FMA %0, %1, %2 + $f10_f = COPY %3(s32) + PseudoRET implicit $f10_f + +... +--- +name: fneg_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: fneg_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[FNEG:%[0-9]+]]:fprb(s32) = G_FNEG [[COPY]] + ; CHECK-NEXT: $f10_f = COPY [[FNEG]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = G_FNEG %0 + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fabs_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: fabs_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[FABS:%[0-9]+]]:fprb(s32) = G_FABS [[COPY]] + ; CHECK-NEXT: $f10_f = COPY [[FABS]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = G_FABS %0 + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fsqrt_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: fsqrt_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:fprb(s32) = G_FSQRT [[COPY]] + ; CHECK-NEXT: $f10_f = COPY [[FSQRT]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = G_FSQRT %0 + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fmaxnum_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fmaxnum_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:fprb(s32) = G_FMAXNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FMAXNUM]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FMAXNUM %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fminnum_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fminnum_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:fprb(s32) = G_FMINNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FMINNUM]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FMINNUM %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fcopysign_f32_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: fcopysign_f32_f32 + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s32) = COPY $f11_f + %2:_(s32) = G_FCOPYSIGN %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fcopysign_f32_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_f, $f11_d + + ; CHECK-LABEL: name: fcopysign_f32_f64 + ; CHECK: liveins: $f10_f, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s32) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: $f10_f = COPY [[FCOPYSIGN]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $f10_f + %1:_(s64) = COPY $f11_d + %2:_(s32) = G_FCOPYSIGN %0, %1 + $f10_f = COPY %2(s32) + PseudoRET implicit $f10_f + +... +--- +name: fadd_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fadd_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FADD]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FADD %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fsub_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fsub_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FSUB]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FSUB %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fmul_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fmul_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[FMUL:%[0-9]+]]:fprb(s64) = G_FMUL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FMUL]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FMUL %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fdiv_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fdiv_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[FDIV:%[0-9]+]]:fprb(s64) = G_FDIV [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FDIV]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FDIV %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fma_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d, $f12_d + + ; CHECK-LABEL: name: fma_f64 + ; CHECK: liveins: $f10_d, $f11_d, $f12_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f12_d + ; CHECK-NEXT: [[FMA:%[0-9]+]]:fprb(s64) = G_FMA [[COPY]], [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $f10_d = COPY [[FMA]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = COPY $f12_d + %3:_(s64) = G_FMA %0, %1, %2 + $f10_d = COPY %3(s64) + PseudoRET implicit $f10_d + +... +--- +name: fneg_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: fneg_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[FNEG:%[0-9]+]]:fprb(s64) = G_FNEG [[COPY]] + ; CHECK-NEXT: $f10_d = COPY [[FNEG]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = G_FNEG %0 + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fabs_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: fabs_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[FABS:%[0-9]+]]:fprb(s64) = G_FABS [[COPY]] + ; CHECK-NEXT: $f10_d = COPY [[FABS]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = G_FABS %0 + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fsqrt_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: fsqrt_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:fprb(s64) = G_FSQRT [[COPY]] + ; CHECK-NEXT: $f10_d = COPY [[FSQRT]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = G_FSQRT %0 + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fmaxnum_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fmaxnum_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:fprb(s64) = G_FMAXNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FMAXNUM]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FMAXNUM %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fminnum_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fminnum_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:fprb(s64) = G_FMINNUM [[COPY]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FMINNUM]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FMINNUM %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fcopysign_f64_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_d + + ; CHECK-LABEL: name: fcopysign_f64_f64 + ; CHECK: liveins: $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s64) = G_FCOPYSIGN [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: $f10_d = COPY [[FCOPYSIGN]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s64) = COPY $f11_d + %2:_(s64) = G_FCOPYSIGN %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fcopysign_f64_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $f10_d, $f11_f + + ; CHECK-LABEL: name: fcopysign_f64_f32 + ; CHECK: liveins: $f10_d, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s64) = G_FCOPYSIGN [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: $f10_d = COPY [[FCOPYSIGN]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $f10_d + %1:_(s32) = COPY $f11_f + %2:_(s64) = G_FCOPYSIGN %0, %1 + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir new file mode 100644 index 0000000..7758a64 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir @@ -0,0 +1,92 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d,zfh -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+d,zfh -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: fpext_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fpext_f32 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:fprb(s32) = G_FPEXT [[COPY]](s16) + ; CHECK-NEXT: $f10_f = COPY [[FPEXT]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s16) = COPY $f10_h + %1:_(s32) = G_FPEXT %0(s16) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: fptrunc_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptrunc_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:fprb(s16) = G_FPTRUNC [[COPY]](s32) + ; CHECK-NEXT: $f10_h = COPY [[FPTRUNC]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s32) = COPY $f10_f + %1:_(s16) = G_FPTRUNC %0(s32) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: fpext_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fpext_f64 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:fprb(s64) = G_FPEXT [[COPY]](s16) + ; CHECK-NEXT: $f10_d = COPY [[FPEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s16) = COPY $f10_h + %1:_(s64) = G_FPEXT %0(s16) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fptrunc_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptrunc_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:fprb(s16) = G_FPTRUNC [[COPY]](s64) + ; CHECK-NEXT: $f10_h = COPY [[FPTRUNC]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s64) = COPY $f10_d + %1:_(s16) = G_FPTRUNC %0(s64) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir new file mode 100644 index 0000000..1ed7cee --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: fpext +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fpext + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:fprb(s64) = G_FPEXT [[COPY]](s32) + ; CHECK-NEXT: $f10_d = COPY [[FPEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s32) = COPY $f10_f + %1:_(s64) = G_FPEXT %0(s32) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: fptrunc +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptrunc + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:fprb(s32) = G_FPTRUNC [[COPY]](s64) + ; CHECK-NEXT: $f10_f = COPY [[FPTRUNC]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s64) = COPY $f10_d + %1:_(s32) = G_FPTRUNC %0(s64) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir new file mode 100644 index 0000000..f743622 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir @@ -0,0 +1,202 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s --check-prefixes=CHECK +# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s --check-prefixes=CHECK + +--- +name: fp_store_fp_def_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10, $f10_f, $f11_f + + ; CHECK-LABEL: name: fp_store_fp_def_f32 + ; CHECK: liveins: $x10, $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY1]], [[COPY2]] + ; CHECK-NEXT: G_STORE [[FADD]](s32), [[COPY]](p0) :: (store (s32)) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_(s32) = COPY $f10_f + %2:_(s32) = COPY $f11_f + %3:_(s32) = G_FADD %1, %2 + G_STORE %3(s32), %0(p0) :: (store (s32)) + PseudoRET + +... +--- +name: fp_store_fp_def_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10, $f10_d, $f11_d + + ; CHECK-LABEL: name: fp_store_fp_def_f64 + ; CHECK: liveins: $x10, $f10_d, $f11_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY1]], [[COPY2]] + ; CHECK-NEXT: G_STORE [[FADD]](s64), [[COPY]](p0) :: (store (s64)) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $f10_d + %2:_(s64) = COPY $f11_d + %3:_(s64) = G_FADD %1, %2 + G_STORE %3(s64), %0(p0) :: (store (s64)) + PseudoRET + +... +--- +name: fp_store_no_def_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10, $f10_d + + ; CHECK-LABEL: name: fp_store_no_def_f64 + ; CHECK: liveins: $x10, $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64)) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $f10_d + G_STORE %1(s64), %0(p0) :: (store (s64)) + PseudoRET + +... +--- +name: fp_load_fp_use_f32 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10, $f10_f + + ; CHECK-LABEL: name: fp_load_fp_use_f32 + ; CHECK: liveins: $x10, $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32)) + ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[LOAD]], [[COPY1]] + ; CHECK-NEXT: $f10_f = COPY [[FADD]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(p0) = COPY $x10 + %1:_(s32) = COPY $f10_f + %2:_(s32) = G_LOAD %0(p0) :: (load (s32)) + %3:_(s32) = G_FADD %2, %1 + $f10_f = COPY %3(s32) + PseudoRET implicit $f10_f + +... +--- +name: fp_load_fp_use_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10, $f10_d + + ; CHECK-LABEL: name: fp_load_fp_use_f64 + ; CHECK: liveins: $x10, $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64)) + ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[LOAD]], [[COPY1]] + ; CHECK-NEXT: $f10_d = COPY [[FADD]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $f10_d + %2:_(s64) = G_LOAD %0(p0) :: (load (s64)) + %3:_(s64) = G_FADD %2, %1 + $f10_d = COPY %3(s64) + PseudoRET implicit $f10_d + +... +--- +name: fp_load_no_use_f64 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10, $f10_d + + ; CHECK-LABEL: name: fp_load_no_use_f64 + ; CHECK: liveins: $x10, $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64)) + ; CHECK-NEXT: $f10_d = COPY [[LOAD]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $f10_d + %2:_(s64) = G_LOAD %0(p0) :: (load (s64)) + $f10_d = COPY %2(s64) + PseudoRET implicit $f10_d + +... +--- +name: fp_store_fp_def_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10, $f10_h, $f11_h + + ; CHECK-LABEL: name: fp_store_fp_def_f16 + ; CHECK: liveins: $x10, $f10_h, $f11_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s16) = COPY $f11_h + ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[COPY1]], [[COPY2]] + ; CHECK-NEXT: G_STORE [[FADD]](s16), [[COPY]](p0) :: (store (s16)) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_(s16) = COPY $f10_h + %2:_(s16) = COPY $f11_h + %3:_(s16) = G_FADD %1, %2 + G_STORE %3(s16), %0(p0) :: (store (s16)) + PseudoRET + +... +--- +name: fp_load_fp_use_f16 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10, $f10_h + + ; CHECK-LABEL: name: fp_load_fp_use_f16 + ; CHECK: liveins: $x10, $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s16) = G_LOAD [[COPY]](p0) :: (load (s16)) + ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[LOAD]], [[COPY1]] + ; CHECK-NEXT: $f10_h = COPY [[FADD]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(p0) = COPY $x10 + %1:_(s16) = COPY $f10_h + %2:_(s16) = G_LOAD %0(p0) :: (load (s16)) + %3:_(s16) = G_FADD %2, %1 + $f10_h = COPY %3(s16) + PseudoRET implicit $f10_h + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir new file mode 100644 index 0000000..7dee137 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir @@ -0,0 +1,181 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s + +--- +name: fp_select_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_f, $f11_f + + ; RV32I-LABEL: name: fp_select_s32 + ; RV32I: liveins: $x10, $f10_f, $f11_f + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] + ; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $f10_f + %3:_(s32) = COPY $x10 + %4:_(s32) = COPY $f10_f + %5:_(s32) = COPY $f11_f + %12:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_AND %3, %12 + %10:_(s32) = G_SELECT %11(s32), %4, %5 + $f10_f = COPY %10(s32) + PseudoRET implicit $f10_f + +... +--- +name: fp_select_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_d, $f11_d + + ; RV32I-LABEL: name: fp_select_s64 + ; RV32I: liveins: $x10, $f10_d, $f11_d + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s64) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] + ; RV32I-NEXT: $f10_d = COPY [[SELECT]](s64) + ; RV32I-NEXT: PseudoRET implicit $f10_d + %3:_(s32) = COPY $x10 + %4:_(s64) = COPY $f10_d + %5:_(s64) = COPY $f11_d + %12:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_AND %3, %12 + %10:_(s64) = G_SELECT %11(s32), %4, %5 + $f10_d = COPY %10(s64) + PseudoRET implicit $f10_d + +... +--- +name: fp_select_gpr_use_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_f, $f11_f + + ; RV32I-LABEL: name: fp_select_gpr_use_s32 + ; RV32I: liveins: $x10, $f10_f, $f11_f + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %3:_(s32) = COPY $x10 + %4:_(s32) = COPY $f10_f + %5:_(s32) = COPY $f11_f + %12:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_AND %3, %12 + %10:_(s32) = G_SELECT %11(s32), %4, %5 + $x10 = COPY %10(s32) + PseudoRET implicit $x10 + +... +--- +name: fp_select_gpr_def_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $f10_f + + ; RV32I-LABEL: name: fp_select_gpr_def_s32 + ; RV32I: liveins: $x10, $x11, $f10_f + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:fprb(s32) = COPY [[COPY2]](s32) + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY3]] + ; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $f10_f + %3:_(s32) = COPY $x10 + %4:_(s32) = COPY $f10_f + %5:_(s32) = COPY $x11 + %12:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_AND %3, %12 + %10:_(s32) = G_SELECT %11(s32), %4, %5 + $f10_f = COPY %10(s32) + PseudoRET implicit $f10_f + +... +--- +name: fp_select_only_fpr_use_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; RV32I-LABEL: name: fp_select_only_fpr_use_s32 + ; RV32I: liveins: $x10, $x11, $x12 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x12 + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] + ; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $f10_f + %3:_(s32) = COPY $x10 + %4:_(s32) = COPY $x11 + %5:_(s32) = COPY $x12 + %12:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_AND %3, %12 + %10:_(s32) = G_SELECT %11(s32), %4, %5 + $f10_f = COPY %10(s32) + PseudoRET implicit $f10_f + +... +--- +name: fp_select_only_one_fpr_def_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $f10_f + + ; RV32I-LABEL: name: fp_select_only_one_fpr_def_s32 + ; RV32I: liveins: $x10, $x11, $f10_f + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY1]](s32) + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY2]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %3:_(s32) = COPY $x10 + %4:_(s32) = COPY $f10_f + %5:_(s32) = COPY $x11 + %12:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_AND %3, %12 + %10:_(s32) = G_SELECT %11(s32), %4, %5 + $x10 = COPY %10(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir new file mode 100644 index 0000000..e7f9500 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir @@ -0,0 +1,245 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s + +--- +name: fp_select_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_f, $f11_f + + ; RV32I-LABEL: name: fp_select_s32 + ; RV32I: liveins: $x10, $f10_f, $f11_f + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]] + ; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $f10_f + %3:_(s64) = COPY $x10 + %4:_(s32) = COPY $f10_f + %5:_(s32) = COPY $f11_f + %12:_(s64) = G_CONSTANT i64 1 + %11:_(s64) = G_AND %3, %12 + %10:_(s32) = G_SELECT %11(s64), %4(s32), %5 + $f10_f = COPY %10(s32) + PseudoRET implicit $f10_f + +... +--- +name: fp_select_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_d, $f11_d + + ; RV32I-LABEL: name: fp_select_s64 + ; RV32I: liveins: $x10, $f10_d, $f11_d + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s64) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]] + ; RV32I-NEXT: $f10_d = COPY [[SELECT]](s64) + ; RV32I-NEXT: PseudoRET implicit $f10_d + %3:_(s64) = COPY $x10 + %4:_(s64) = COPY $f10_d + %5:_(s64) = COPY $f11_d + %12:_(s64) = G_CONSTANT i64 1 + %11:_(s64) = G_AND %3, %12 + %10:_(s64) = G_SELECT %11(s64), %4, %5 + $f10_d = COPY %10(s64) + PseudoRET implicit $f10_d + +... +--- +name: fp_select_gpr_use_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_f, $f11_f + + ; RV32I-LABEL: name: fp_select_gpr_use_s32 + ; RV32I: liveins: $x10, $f10_f, $f11_f + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]] + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[SELECT]](s32) + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[COPY3]](s32) + ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV32I-NEXT: PseudoRET implicit $x10 + %3:_(s64) = COPY $x10 + %4:_(s32) = COPY $f10_f + %5:_(s32) = COPY $f11_f + %12:_(s64) = G_CONSTANT i64 1 + %11:_(s64) = G_AND %3, %12 + %10:_(s32) = G_SELECT %11(s64), %4(s32), %5 + %13:_(s64) = G_ANYEXT %10(s32) + $x10 = COPY %13(s64) + PseudoRET implicit $x10 + +... +--- +name: fp_select_gpr_use_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_d, $f11_d + + ; RV32I-LABEL: name: fp_select_gpr_use_s64 + ; RV32I: liveins: $x10, $f10_d, $f11_d + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s64) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV32I-NEXT: PseudoRET implicit $x10 + %3:_(s64) = COPY $x10 + %4:_(s64) = COPY $f10_d + %5:_(s64) = COPY $f11_d + %12:_(s64) = G_CONSTANT i64 1 + %11:_(s64) = G_AND %3, %12 + %10:_(s64) = G_SELECT %11(s64), %4, %5 + $x10 = COPY %10(s64) + PseudoRET implicit $x10 + +... +--- +name: fp_select_gpr_def_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $f10_f + + ; RV32I-LABEL: name: fp_select_gpr_def_s32 + ; RV32I: liveins: $x10, $x11, $f10_f + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY2]](s64) + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:fprb(s32) = COPY [[TRUNC]](s32) + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s64), [[COPY3]], [[COPY1]] + ; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $f10_f + %3:_(s64) = COPY $x10 + %4:_(s32) = COPY $f10_f + %5:_(s64) = COPY $x11 + %6:_(s32) = G_TRUNC %5(s64) + %12:_(s64) = G_CONSTANT i64 1 + %11:_(s64) = G_AND %3, %12 + %10:_(s32) = G_SELECT %11(s64), %6(s32), %4 + $f10_f = COPY %10(s32) + PseudoRET implicit $f10_f + +... +--- +name: fp_select_gpr_def_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $f10_d + + ; RV32I-LABEL: name: fp_select_gpr_def_s64 + ; RV32I: liveins: $x10, $x11, $f10_d + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:fprb(s64) = COPY [[COPY2]](s64) + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s64) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY3]] + ; RV32I-NEXT: $f10_d = COPY [[SELECT]](s64) + ; RV32I-NEXT: PseudoRET implicit $f10_d + %3:_(s64) = COPY $x10 + %4:_(s64) = COPY $f10_d + %5:_(s64) = COPY $x11 + %12:_(s64) = G_CONSTANT i64 1 + %11:_(s64) = G_AND %3, %12 + %10:_(s64) = G_SELECT %11(s64), %4, %5 + $f10_d = COPY %10(s64) + PseudoRET implicit $f10_d + +... +--- +name: fp_select_only_fpr_use_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; RV32I-LABEL: name: fp_select_only_fpr_use_s64 + ; RV32I: liveins: $x10, $x11, $x12 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY $x12 + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s64) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]] + ; RV32I-NEXT: $f10_d = COPY [[SELECT]](s64) + ; RV32I-NEXT: PseudoRET implicit $f10_d + %3:_(s64) = COPY $x10 + %4:_(s64) = COPY $x11 + %5:_(s64) = COPY $x12 + %12:_(s64) = G_CONSTANT i64 1 + %11:_(s64) = G_AND %3, %12 + %10:_(s64) = G_SELECT %11(s64), %4, %5 + $f10_d = COPY %10(s64) + PseudoRET implicit $f10_d + +... +--- +name: fp_select_only_one_fpr_def_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $f10_d + + ; RV32I-LABEL: name: fp_select_only_one_fpr_def_s64 + ; RV32I: liveins: $x10, $x11, $f10_d + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gprb(s64) = COPY [[COPY1]](s64) + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s64) = G_SELECT [[AND]](s64), [[COPY3]], [[COPY2]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV32I-NEXT: PseudoRET implicit $x10 + %3:_(s64) = COPY $x10 + %4:_(s64) = COPY $f10_d + %5:_(s64) = COPY $x11 + %12:_(s64) = G_CONSTANT i64 1 + %11:_(s64) = G_AND %3, %12 + %10:_(s64) = G_SELECT %11(s64), %4, %5 + $x10 = COPY %10(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir new file mode 100644 index 0000000..346dd28 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: fptosi_s32_s16 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s32_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s32) = G_FPTOSI %0(s16) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s16 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s32_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s32) = G_FPTOUI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s32) = G_FPTOUI %0(s16) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir new file mode 100644 index 0000000..d63803f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir @@ -0,0 +1,89 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: fptosi_s32_s16 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s32_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:gprb(s64) = G_FCVT_W_RV64 [[COPY]](s16), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s64) = G_FCVT_W_RV64 %0(s16), 1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s16 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s32_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:gprb(s64) = G_FCVT_WU_RV64 [[COPY]](s16), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s64) = G_FCVT_WU_RV64 %0(s16), 1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s64_s16 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptosi_s64_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s64) = G_FPTOSI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s64) = G_FPTOSI %0(s16) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s64_s16 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_h + + ; CHECK-LABEL: name: fptoui_s64_s16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s64) = G_FPTOUI [[COPY]](s16) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %1:_(s64) = G_FPTOUI %0(s16) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir new file mode 100644 index 0000000..10fb4f6 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv32.mir @@ -0,0 +1,89 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: fptosi_s32_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s32_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = G_FPTOSI %0(s32) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s32_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s32) = G_FPTOUI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s32) = G_FPTOUI %0(s32) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s32_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s32) = G_FPTOSI %0(s64) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s32_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s32) = G_FPTOUI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s32) = G_FPTOUI %0(s64) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir new file mode 100644 index 0000000..d5c2875 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir @@ -0,0 +1,173 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: fptosi_s32_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s32_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:gprb(s64) = G_FCVT_W_RV64 [[COPY]](s32), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s64) = G_FCVT_W_RV64 %0(s32), 1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s32_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[FCVT_WU_RV64_:%[0-9]+]]:gprb(s64) = G_FCVT_WU_RV64 [[COPY]](s32), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_WU_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s64) = G_FCVT_WU_RV64 %0(s32), 1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s64_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptosi_s64_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s64) = G_FPTOSI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s64) = G_FPTOSI %0(s32) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s64_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_f + + ; CHECK-LABEL: name: fptoui_s64_s32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s64) = G_FPTOUI [[COPY]](s32) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %1:_(s64) = G_FPTOUI %0(s32) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s32_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s32_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:gprb(s64) = G_FCVT_W_RV64 [[COPY]](s64), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = G_FCVT_W_RV64 %0(s64), 1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s32_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s32_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[FCVT_W_RV64_:%[0-9]+]]:gprb(s64) = G_FCVT_W_RV64 [[COPY]](s64), 1 + ; CHECK-NEXT: $x10 = COPY [[FCVT_W_RV64_]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = G_FCVT_W_RV64 %0(s64), 1 + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptosi_s64_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptosi_s64_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gprb(s64) = G_FPTOSI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOSI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = G_FPTOSI %0(s64) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: fptoui_s64_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $f10_d + + ; CHECK-LABEL: name: fptoui_s64_s64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:gprb(s64) = G_FPTOUI [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[FPTOUI]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s64) = G_FPTOUI %0(s64) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir new file mode 100644 index 0000000..f701ef6 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir @@ -0,0 +1,33 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=regbankselect %s -o - \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv64 -run-pass=regbankselect %s -o - \ +# RUN: | FileCheck %s +--- | + define ptr @frame_index() { + entry: + %x = alloca i32, align 4 + ret ptr %x + } + +... +--- +name: frame_index +legalized: true +registers: + - { id: 0, class: _, preferred-register: '' } +stack: + - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.1.entry: + ; CHECK-LABEL: name: frame_index + ; CHECK: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %stack.0.x + ; CHECK-NEXT: $x10 = COPY [[FRAME_INDEX]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = G_FRAME_INDEX %stack.0.x + $x10 = COPY %0(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir new file mode 100644 index 0000000..b43371a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir @@ -0,0 +1,28 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s + +--- | + @var = global i32 0 + + define ptr @test_global() { + ret ptr @var + } + +... +--- +name: test_global +legalized: true +tracksRegLiveness: true +body: | + bb.0 (%ir-block.0): + ; RV32I-LABEL: name: test_global + ; RV32I: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @var + ; RV32I-NEXT: $x10 = COPY [[GV]](p0) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = G_GLOBAL_VALUE @var + $x10 = COPY %0(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir new file mode 100644 index 0000000..c4196b0 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir @@ -0,0 +1,28 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- | + @var = global i32 0 + + define ptr @test_global() { + ret ptr @var + } + +... +--- +name: test_global +legalized: true +tracksRegLiveness: true +body: | + bb.0 (%ir-block.0): + ; RV64I-LABEL: name: test_global + ; RV64I: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @var + ; RV64I-NEXT: $x10 = COPY [[GV]](p0) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = G_GLOBAL_VALUE @var + $x10 = COPY %0(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir new file mode 100644 index 0000000..f084af5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir @@ -0,0 +1,55 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+f -run-pass=regbankselect -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32F %s + +--- +name: implicit_def_gpr +legalized: true +body: | + bb.0: + ; RV32F-LABEL: name: implicit_def_gpr + ; RV32F: [[DEF:%[0-9]+]]:gprb(s32) = G_IMPLICIT_DEF + ; RV32F-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[DEF]], [[DEF]] + ; RV32F-NEXT: $x10 = COPY [[ADD]](s32) + %0:_(s32) = G_IMPLICIT_DEF + %1:_(s32) = G_ADD %0, %0 + $x10 = COPY %1(s32) +... +--- +name: implicit_def_copy_gpr +legalized: true +body: | + bb.0: + ; RV32F-LABEL: name: implicit_def_copy_gpr + ; RV32F: [[DEF:%[0-9]+]]:gprb(s32) = G_IMPLICIT_DEF + ; RV32F-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY [[DEF]](s32) + ; RV32F-NEXT: $x10 = COPY [[COPY]](s32) + %0:_(s32) = G_IMPLICIT_DEF + %1:_(s32) = COPY %0(s32) + $x10 = COPY %1(s32) +... + +--- +name: implicit_def_fpr +legalized: true +body: | + bb.0: + ; RV32F-LABEL: name: implicit_def_fpr + ; RV32F: [[DEF:%[0-9]+]]:fprb(s32) = G_IMPLICIT_DEF + ; RV32F-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[DEF]], [[DEF]] + ; RV32F-NEXT: $f10_f = COPY [[FADD]](s32) + %0:_(s32) = G_IMPLICIT_DEF + %1:_(s32) = G_FADD %0, %0 + $f10_f = COPY %1(s32) +... +--- +name: implicit_def_copy_fpr +legalized: true +body: | + bb.0: + ; RV32F-LABEL: name: implicit_def_copy_fpr + ; RV32F: [[DEF:%[0-9]+]]:fprb(s32) = G_IMPLICIT_DEF + ; RV32F-NEXT: $f10_f = COPY [[DEF]](s32) + %0:_(s32) = G_IMPLICIT_DEF + $f10_f = COPY %0(s32) +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir new file mode 100644 index 0000000..caece8b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir @@ -0,0 +1,52 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV64D %s + +--- +name: implicit_def_gpr +legalized: true +body: | + bb.0: + ; RV64D-LABEL: name: implicit_def_gpr + ; RV64D: [[DEF:%[0-9]+]]:gprb(s64) = G_IMPLICIT_DEF + ; RV64D-NEXT: [[ADD:%[0-9]+]]:gprb(s64) = G_ADD [[DEF]], [[DEF]] + ; RV64D-NEXT: $x10 = COPY [[ADD]](s64) + %0:_(s64) = G_IMPLICIT_DEF + %1:_(s64) = G_ADD %0, %0 + $x10 = COPY %1(s64) +... +--- +name: implicit_def_copy_gpr +legalized: true +body: | + bb.0: + ; RV64D-LABEL: name: implicit_def_copy_gpr + ; RV64D: [[DEF:%[0-9]+]]:gprb(s64) = G_IMPLICIT_DEF + ; RV64D-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY [[DEF]](s64) + ; RV64D-NEXT: $x10 = COPY [[COPY]](s64) + %0:_(s64) = G_IMPLICIT_DEF + %1:_(s64) = COPY %0(s64) + $x10 = COPY %1(s64) +... + +--- +name: implicit_def_fpr +legalized: true +body: | + bb.0: + ; RV64D-LABEL: name: implicit_def_fpr + ; RV64D: [[DEF:%[0-9]+]]:fprb(s64) = G_IMPLICIT_DEF + ; RV64D-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[DEF]], [[DEF]] + ; RV64D-NEXT: $f10_d = COPY [[FADD]](s64) + %0:_(s64) = G_IMPLICIT_DEF + %1:_(s64) = G_FADD %0, %0 + $f10_d = COPY %1(s64) +... +--- +name: implicit_def_copy_fpr +legalized: true +body: | + bb.0: + %0:_(s64) = G_IMPLICIT_DEF + $f10_d = COPY %0(s64) +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir new file mode 100644 index 0000000..9224579 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect -verify-machineinstrs %s -o - \ +# RUN: | FileCheck %s + +--- +name: is_fpclass_f16 +legalized: true +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: is_fpclass_f16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 152 + ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:gprb(s32) = G_FCLASS [[COPY]](s16) + ; CHECK-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[FCLASS]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[AND]](s32), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %3:_(s32) = G_CONSTANT i32 152 + %4:_(s32) = G_CONSTANT i32 0 + %5:_(s32) = G_FCLASS %0(s16) + %6:_(s32) = G_AND %5, %3 + %7:_(s32) = G_ICMP intpred(ne), %6(s32), %4 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir new file mode 100644 index 0000000..9bf796d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect -verify-machineinstrs %s -o - \ +# RUN: | FileCheck %s + +--- +name: is_fpclass_f16 +legalized: true +body: | + bb.0: + liveins: $f10_h + + ; CHECK-LABEL: name: is_fpclass_f16 + ; CHECK: liveins: $f10_h + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h + ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 152 + ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:gprb(s64) = G_FCLASS [[COPY]](s16) + ; CHECK-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[FCLASS]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(ne), [[AND]](s64), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s16) = COPY $f10_h + %3:_(s64) = G_CONSTANT i64 152 + %4:_(s64) = G_CONSTANT i64 0 + %5:_(s64) = G_FCLASS %0(s16) + %6:_(s64) = G_AND %5, %3 + %7:_(s64) = G_ICMP intpred(ne), %6(s64), %4 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir new file mode 100644 index 0000000..ad0b73e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir @@ -0,0 +1,58 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect -verify-machineinstrs %s -o - \ +# RUN: | FileCheck %s + +--- +name: is_fpclass_f32 +legalized: true +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: is_fpclass_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 152 + ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:gprb(s32) = G_FCLASS [[COPY]](s32) + ; CHECK-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[FCLASS]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[AND]](s32), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %3:_(s32) = G_CONSTANT i32 152 + %4:_(s32) = G_CONSTANT i32 0 + %5:_(s32) = G_FCLASS %0(s32) + %6:_(s32) = G_AND %5, %3 + %7:_(s32) = G_ICMP intpred(ne), %6(s32), %4 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f64 +legalized: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: is_fpclass_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 152 + ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:gprb(s32) = G_FCLASS [[COPY]](s64) + ; CHECK-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[FCLASS]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[AND]](s32), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %3:_(s32) = G_CONSTANT i32 152 + %4:_(s32) = G_CONSTANT i32 0 + %5:_(s32) = G_FCLASS %0(s64) + %6:_(s32) = G_AND %5, %3 + %7:_(s32) = G_ICMP intpred(ne), %6(s32), %4 + $x10 = COPY %7(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir new file mode 100644 index 0000000..9e602b3 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir @@ -0,0 +1,58 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect -verify-machineinstrs %s -o - \ +# RUN: | FileCheck %s + +--- +name: is_fpclass_f32 +legalized: true +body: | + bb.0: + liveins: $f10_f + + ; CHECK-LABEL: name: is_fpclass_f32 + ; CHECK: liveins: $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f + ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 152 + ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:gprb(s64) = G_FCLASS [[COPY]](s32) + ; CHECK-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[FCLASS]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(ne), [[AND]](s64), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $f10_f + %3:_(s64) = G_CONSTANT i64 152 + %4:_(s64) = G_CONSTANT i64 0 + %5:_(s64) = G_FCLASS %0(s32) + %6:_(s64) = G_AND %5, %3 + %7:_(s64) = G_ICMP intpred(ne), %6(s64), %4 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... +--- +name: is_fpclass_f64 +legalized: true +body: | + bb.0: + liveins: $f10_d + + ; CHECK-LABEL: name: is_fpclass_f64 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 152 + ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[FCLASS:%[0-9]+]]:gprb(s64) = G_FCLASS [[COPY]](s64) + ; CHECK-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[FCLASS]], [[C]] + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(ne), [[AND]](s64), [[C1]] + ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %3:_(s64) = G_CONSTANT i64 152 + %4:_(s64) = G_CONSTANT i64 0 + %5:_(s64) = G_FCLASS %0(s64) + %6:_(s64) = G_AND %5, %3 + %7:_(s64) = G_ICMP intpred(ne), %6(s64), %4 + $x10 = COPY %7(s64) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir new file mode 100644 index 0000000..02e5a9a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: sitofp_s16_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s16_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s16) = G_SITOFP [[COPY]](s32) + ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s32) = COPY $x10 + %1:_(s16) = G_SITOFP %0(s32) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s16_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s16_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s16) = G_UITOFP [[COPY]](s32) + ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s32) = COPY $x10 + %1:_(s16) = G_UITOFP %0(s32) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir new file mode 100644 index 0000000..5b48a7e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: sitofp_s16_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s16_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s16) = G_SITOFP [[COPY]](s64) + ; CHECK-NEXT: $f10_h = COPY [[SITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s64) = COPY $x10 + %1:_(s16) = G_SITOFP %0(s64) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... +--- +name: uitofp_s16_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s16_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s16) = G_UITOFP [[COPY]](s64) + ; CHECK-NEXT: $f10_h = COPY [[UITOFP]](s16) + ; CHECK-NEXT: PseudoRET implicit $f10_h + %0:_(s64) = COPY $x10 + %1:_(s16) = G_UITOFP %0(s64) + $f10_h = COPY %1(s16) + PseudoRET implicit $f10_h + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir new file mode 100644 index 0000000..e4e9af7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv32.mir @@ -0,0 +1,89 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: sitofp_s32_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s32) = G_SITOFP [[COPY]](s32) + ; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $x10 + %1:_(s32) = G_SITOFP %0(s32) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s32) = G_UITOFP [[COPY]](s32) + ; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s32) = COPY $x10 + %1:_(s32) = G_UITOFP %0(s32) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s64_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s64) = G_SITOFP [[COPY]](s32) + ; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s32) = COPY $x10 + %1:_(s64) = G_SITOFP %0(s32) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s64) = G_UITOFP [[COPY]](s32) + ; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s32) = COPY $x10 + %1:_(s64) = G_UITOFP %0(s32) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir new file mode 100644 index 0000000..6cb38cf --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir @@ -0,0 +1,89 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: sitofp_s32_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s32_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s32) = G_SITOFP [[COPY]](s64) + ; CHECK-NEXT: $f10_f = COPY [[SITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s64) = COPY $x10 + %1:_(s32) = G_SITOFP %0(s64) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: uitofp_s32_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s32_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s32) = G_UITOFP [[COPY]](s64) + ; CHECK-NEXT: $f10_f = COPY [[UITOFP]](s32) + ; CHECK-NEXT: PseudoRET implicit $f10_f + %0:_(s64) = COPY $x10 + %1:_(s32) = G_UITOFP %0(s64) + $f10_f = COPY %1(s32) + PseudoRET implicit $f10_f + +... +--- +name: sitofp_s64_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: sitofp_s64_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fprb(s64) = G_SITOFP [[COPY]](s64) + ; CHECK-NEXT: $f10_d = COPY [[SITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $x10 + %1:_(s64) = G_SITOFP %0(s64) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... +--- +name: uitofp_s64_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: uitofp_s64_s64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fprb(s64) = G_UITOFP [[COPY]](s64) + ; CHECK-NEXT: $f10_d = COPY [[UITOFP]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s64) = COPY $x10 + %1:_(s64) = G_UITOFP %0(s64) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir new file mode 100644 index 0000000..b7fd2a3 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir @@ -0,0 +1,154 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s + +--- | + define i32 @jt_test(i32 signext %in) { + entry: + switch i32 %in, label %default [ + i32 1, label %bb1 + i32 2, label %bb2 + i32 3, label %bb3 + i32 4, label %bb4 + i32 5, label %bb5 + i32 6, label %bb6 + ] + + bb1: ; preds = %entry + ret i32 4 + + bb2: ; preds = %entry + ret i32 3 + + bb3: ; preds = %entry + ret i32 2 + + bb4: ; preds = %entry + ret i32 1 + + bb5: ; preds = %entry + ret i32 100 + + bb6: ; preds = %entry + ret i32 200 + + default: ; preds = %entry + ret i32 1000 + } + +... +--- +name: jt_test +legalized: true +tracksRegLiveness: true +jumpTable: + kind: block-address + entries: + - id: 0 + blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ] +body: | + ; RV32I-LABEL: name: jt_test + ; RV32I: bb.0.entry: + ; RV32I-NEXT: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 5 + ; RV32I-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 200 + ; RV32I-NEXT: [[C2:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 100 + ; RV32I-NEXT: [[C3:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[C4:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 2 + ; RV32I-NEXT: [[C5:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3 + ; RV32I-NEXT: [[C6:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4 + ; RV32I-NEXT: [[C7:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1000 + ; RV32I-NEXT: [[C8:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[C8]] + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ugt), [[SUB]](s32), [[C]] + ; RV32I-NEXT: G_BRCOND [[ICMP]](s32), %bb.8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.1.entry: + ; RV32I-NEXT: successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[JUMP_TABLE:%[0-9]+]]:gprb(p0) = G_JUMP_TABLE %jump-table.0 + ; RV32I-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[SUB]](s32) + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.2.bb1: + ; RV32I-NEXT: $x10 = COPY [[C6]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.3.bb2: + ; RV32I-NEXT: $x10 = COPY [[C5]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.4.bb3: + ; RV32I-NEXT: $x10 = COPY [[C4]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.5.bb4: + ; RV32I-NEXT: $x10 = COPY [[C3]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.6.bb5: + ; RV32I-NEXT: $x10 = COPY [[C2]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.7.bb6: + ; RV32I-NEXT: $x10 = COPY [[C1]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.8.default: + ; RV32I-NEXT: $x10 = COPY [[C7]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + bb.1.entry: + successors: %bb.8, %bb.9 + liveins: $x10 + + %0:_(s32) = COPY $x10 + %4:_(s32) = G_CONSTANT i32 5 + %8:_(s32) = G_CONSTANT i32 200 + %9:_(s32) = G_CONSTANT i32 100 + %10:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_CONSTANT i32 2 + %12:_(s32) = G_CONSTANT i32 3 + %13:_(s32) = G_CONSTANT i32 4 + %14:_(s32) = G_CONSTANT i32 1000 + %1:_(s32) = G_CONSTANT i32 1 + %2:_(s32) = G_SUB %0, %1 + %16:_(s32) = G_ICMP intpred(ugt), %2(s32), %4 + G_BRCOND %16(s32), %bb.8 + + bb.9.entry: + successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7 + + %7:_(p0) = G_JUMP_TABLE %jump-table.0 + G_BRJT %7(p0), %jump-table.0, %2(s32) + + bb.2.bb1: + $x10 = COPY %13(s32) + PseudoRET implicit $x10 + + bb.3.bb2: + $x10 = COPY %12(s32) + PseudoRET implicit $x10 + + bb.4.bb3: + $x10 = COPY %11(s32) + PseudoRET implicit $x10 + + bb.5.bb4: + $x10 = COPY %10(s32) + PseudoRET implicit $x10 + + bb.6.bb5: + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + + bb.7.bb6: + $x10 = COPY %8(s32) + PseudoRET implicit $x10 + + bb.8.default: + $x10 = COPY %14(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir new file mode 100644 index 0000000..56cac99 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir @@ -0,0 +1,159 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- | + define i32 @jt_test(i32 signext %in) { + entry: + %0 = sext i32 %in to i64 + switch i64 %0, label %default [ + i64 1, label %bb1 + i64 2, label %bb2 + i64 3, label %bb3 + i64 4, label %bb4 + i64 5, label %bb5 + i64 6, label %bb6 + ] + + bb1: ; preds = %entry + ret i32 4 + + bb2: ; preds = %entry + ret i32 3 + + bb3: ; preds = %entry + ret i32 2 + + bb4: ; preds = %entry + ret i32 1 + + bb5: ; preds = %entry + ret i32 100 + + bb6: ; preds = %entry + ret i32 200 + + default: ; preds = %entry + ret i32 1000 + } + +... +--- +name: jt_test +legalized: true +tracksRegLiveness: true +jumpTable: + kind: custom32 + entries: + - id: 0 + blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ] +body: | + ; RV64I-LABEL: name: jt_test + ; RV64I: bb.0.entry: + ; RV64I-NEXT: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:gprb(s64) = G_ASSERT_SEXT [[COPY]], 32 + ; RV64I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 5 + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:gprb(s64) = G_SEXT_INREG [[ASSERT_SEXT]], 32 + ; RV64I-NEXT: [[C1:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:gprb(s64) = G_SUB [[SEXT_INREG]], [[C1]] + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(ugt), [[SUB]](s64), [[C]] + ; RV64I-NEXT: G_BRCOND [[ICMP]](s64), %bb.8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.1.entry: + ; RV64I-NEXT: successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[JUMP_TABLE:%[0-9]+]]:gprb(p0) = G_JUMP_TABLE %jump-table.0 + ; RV64I-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[SUB]](s64) + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.2.bb1: + ; RV64I-NEXT: [[C2:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 4 + ; RV64I-NEXT: $x10 = COPY [[C2]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.3.bb2: + ; RV64I-NEXT: [[C3:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 3 + ; RV64I-NEXT: $x10 = COPY [[C3]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.4.bb3: + ; RV64I-NEXT: [[C4:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 2 + ; RV64I-NEXT: $x10 = COPY [[C4]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.5.bb4: + ; RV64I-NEXT: [[C5:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: $x10 = COPY [[C5]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.6.bb5: + ; RV64I-NEXT: [[C6:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 100 + ; RV64I-NEXT: $x10 = COPY [[C6]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.7.bb6: + ; RV64I-NEXT: [[C7:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 200 + ; RV64I-NEXT: $x10 = COPY [[C7]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.8.default: + ; RV64I-NEXT: [[C8:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1000 + ; RV64I-NEXT: $x10 = COPY [[C8]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + bb.1.entry: + successors: %bb.8, %bb.9 + liveins: $x10 + + %1:_(s64) = COPY $x10 + %2:_(s64) = G_ASSERT_SEXT %1, 32 + %7:_(s64) = G_CONSTANT i64 5 + %3:_(s64) = G_SEXT_INREG %2, 32 + %4:_(s64) = G_CONSTANT i64 1 + %5:_(s64) = G_SUB %3, %4 + %26:_(s64) = G_ICMP intpred(ugt), %5(s64), %7 + G_BRCOND %26(s64), %bb.8 + + bb.9.entry: + successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7 + + %10:_(p0) = G_JUMP_TABLE %jump-table.0 + G_BRJT %10(p0), %jump-table.0, %5(s64) + + bb.2.bb1: + %22:_(s64) = G_CONSTANT i64 4 + $x10 = COPY %22(s64) + PseudoRET implicit $x10 + + bb.3.bb2: + %20:_(s64) = G_CONSTANT i64 3 + $x10 = COPY %20(s64) + PseudoRET implicit $x10 + + bb.4.bb3: + %18:_(s64) = G_CONSTANT i64 2 + $x10 = COPY %18(s64) + PseudoRET implicit $x10 + + bb.5.bb4: + %16:_(s64) = G_CONSTANT i64 1 + $x10 = COPY %16(s64) + PseudoRET implicit $x10 + + bb.6.bb5: + %14:_(s64) = G_CONSTANT i64 100 + $x10 = COPY %14(s64) + PseudoRET implicit $x10 + + bb.7.bb6: + %12:_(s64) = G_CONSTANT i64 200 + $x10 = COPY %12(s64) + PseudoRET implicit $x10 + + bb.8.default: + %24:_(s64) = G_CONSTANT i64 1000 + $x10 = COPY %24(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir new file mode 100644 index 0000000..45e96b1 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir @@ -0,0 +1,173 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s + +--- +name: load_i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32I-LABEL: name: load_i8 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s8)) + ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %3:_(s32) = G_LOAD %0(p0) :: (load (s8)) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: load_i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32I-LABEL: name: load_i16 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s16)) + ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %3:_(s32) = G_LOAD %0(p0) :: (load (s16)) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: load_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32I-LABEL: name: load_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32)) + ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %3:_(s32) = G_LOAD %0(p0) :: (load (s32)) + $x10 = COPY %3(s32) + PseudoRET implicit $x10 + +... +--- +name: load_ptr +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32I-LABEL: name: load_ptr + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[COPY]](p0) :: (load (p0)) + ; RV32I-NEXT: $x10 = COPY [[LOAD]](p0) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %3:_(p0) = G_LOAD %0(p0) :: (load (p0)) + $x10 = COPY %3(p0) + PseudoRET implicit $x10 + +... +--- +name: zextload_i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32I-LABEL: name: zextload_i8 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV32I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; RV32I-NEXT: $x10 = COPY [[ZEXTLOAD]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: zextload_i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32I-LABEL: name: zextload_i16 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV32I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) + ; RV32I-NEXT: $x10 = COPY [[ZEXTLOAD]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: sextload_i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32I-LABEL: name: sextload_i8 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV32I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8)) + ; RV32I-NEXT: $x10 = COPY [[SEXTLOAD]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... +--- +name: sextload_i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32I-LABEL: name: sextload_i16 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV32I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16)) + ; RV32I-NEXT: $x10 = COPY [[SEXTLOAD]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16)) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir new file mode 100644 index 0000000..77fb05e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir @@ -0,0 +1,242 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- +name: load_i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV64I-LABEL: name: load_i8 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s8)) + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[LOAD]](s32) + ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %3:_(s32) = G_LOAD %0(p0) :: (load (s8)) + %2:_(s64) = G_ANYEXT %3(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV64I-LABEL: name: load_i16 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s16)) + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[LOAD]](s32) + ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %3:_(s32) = G_LOAD %0(p0) :: (load (s16)) + %2:_(s64) = G_ANYEXT %3(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV64I-LABEL: name: load_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32)) + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[LOAD]](s32) + ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = G_LOAD %0(p0) :: (load (s32)) + %2:_(s64) = G_ANYEXT %1(s32) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: load_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV64I-LABEL: name: load_i64 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64)) + ; RV64I-NEXT: $x10 = COPY [[LOAD]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_LOAD %0(p0) :: (load (s64)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: load_ptr +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV64I-LABEL: name: load_ptr + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[COPY]](p0) :: (load (p0)) + ; RV64I-NEXT: $x10 = COPY [[LOAD]](p0) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(p0) = G_LOAD %0(p0) :: (load (p0)) + $x10 = COPY %1(p0) + PseudoRET implicit $x10 + +... +--- +name: zextload_i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV64I-LABEL: name: zextload_i8 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) + ; RV64I-NEXT: $x10 = COPY [[ZEXTLOAD]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %3:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s8)) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: zextload_i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV64I-LABEL: name: zextload_i16 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) + ; RV64I-NEXT: $x10 = COPY [[ZEXTLOAD]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %3:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s16)) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: zextload_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV64I-LABEL: name: zextload_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s32)) + ; RV64I-NEXT: $x10 = COPY [[ZEXTLOAD]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV64I-LABEL: name: sextload_i8 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8)) + ; RV64I-NEXT: $x10 = COPY [[SEXTLOAD]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %3:_(s64) = G_SEXTLOAD %0(p0) :: (load (s8)) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV64I-LABEL: name: sextload_i16 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s16)) + ; RV64I-NEXT: $x10 = COPY [[SEXTLOAD]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %3:_(s64) = G_SEXTLOAD %0(p0) :: (load (s16)) + $x10 = COPY %3(s64) + PseudoRET implicit $x10 + +... +--- +name: sextload_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV64I-LABEL: name: sextload_i32 + ; RV64I: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s32)) + ; RV64I-NEXT: $x10 = COPY [[SEXTLOAD]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32)) + $x10 = COPY %1(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir new file mode 100644 index 0000000..4785b86 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/merge-unmerge-rv32.mir @@ -0,0 +1,40 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect %s -o - \ +# RUN: | FileCheck %s + +--- +name: merge_i64 +legalized: true +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: merge_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; CHECK-NEXT: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32) + ; CHECK-NEXT: $f10_d = COPY [[MV]](s64) + ; CHECK-NEXT: PseudoRET implicit $f10_d + %0:_(s32) = COPY $x10 + %1:_(s64) = G_MERGE_VALUES %0(s32), %0(s32) + $f10_d = COPY %1(s64) + PseudoRET implicit $f10_d +... +--- +name: unmerge_i32 +legalized: true +body: | + bb.0.entry: + liveins: $f10_d + ; CHECK-LABEL: name: unmerge_i32 + ; CHECK: liveins: $f10_d + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d + ; CHECK-NEXT: [[UV:%[0-9]+]]:gprb(s32), [[UV1:%[0-9]+]]:gprb(s32) = G_UNMERGE_VALUES [[COPY]](s64) + ; CHECK-NEXT: $x10 = COPY [[UV]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $f10_d + %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64) + $x10 = COPY %1(s32) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir new file mode 100644 index 0000000..715ba22 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir @@ -0,0 +1,77 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s + +--- +name: smax_i32 +legalized: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: smax_i32 + ; RV32I: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[SMAX:%[0-9]+]]:gprb(s32) = G_SMAX [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SMAX]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SMAX %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: smin_i32 +legalized: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: smin_i32 + ; RV32I: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[SMIN:%[0-9]+]]:gprb(s32) = G_SMIN [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SMIN]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_SMIN %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: umax_i32 +legalized: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: umax_i32 + ; RV32I: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[UMAX:%[0-9]+]]:gprb(s32) = G_UMAX [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[UMAX]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_UMAX %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: umin_i32 +legalized: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: umin_i32 + ; RV32I: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[UMIN:%[0-9]+]]:gprb(s32) = G_UMIN [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[UMIN]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = G_UMIN %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir new file mode 100644 index 0000000..2fb680f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir @@ -0,0 +1,77 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- +name: smax_i64 +legalized: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: smax_i64 + ; RV64I: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[SMAX:%[0-9]+]]:gprb(s64) = G_SMAX [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SMAX]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SMAX %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: smin_i64 +legalized: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: smin_i64 + ; RV64I: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[SMIN:%[0-9]+]]:gprb(s64) = G_SMIN [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[SMIN]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_SMIN %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: umax_i64 +legalized: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: umax_i64 + ; RV64I: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[UMAX:%[0-9]+]]:gprb(s64) = G_UMAX [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[UMAX]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_UMAX %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: umin_i64 +legalized: true +body: | + bb.0.entry: + ; RV64I-LABEL: name: umin_i64 + ; RV64I: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[UMIN:%[0-9]+]]:gprb(s64) = G_UMIN [[COPY]], [[COPY1]] + ; RV64I-NEXT: $x10 = COPY [[UMIN]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = G_UMIN %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir new file mode 100644 index 0000000..8feeebf --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir @@ -0,0 +1,89 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s + +--- +name: phi_i32 +legalized: true +tracksRegLiveness: true +body: | + ; RV32I-LABEL: name: phi_i32 + ; RV32I: bb.0: + ; RV32I-NEXT: liveins: $x10, $x11, $x12 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x12 + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: G_BRCOND [[AND]](s32), %bb.2 + ; RV32I-NEXT: G_BR %bb.1 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.1: + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.2: + ; RV32I-NEXT: [[PHI:%[0-9]+]]:gprb(s32) = G_PHI [[COPY2]](s32), %bb.1, [[COPY1]](s32), %bb.0 + ; RV32I-NEXT: $x10 = COPY [[PHI]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x12 + + %3:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %6:_(s32) = G_CONSTANT i32 1 + %5:_(s32) = G_AND %3, %6 + G_BRCOND %5(s32), %bb.2 + G_BR %bb.1 + + bb.1: + + bb.2: + %4:_(s32) = G_PHI %2(s32), %bb.1, %1(s32), %bb.0 + $x10 = COPY %4(s32) + PseudoRET implicit $x10 + +... +--- +name: phi_ptr +legalized: true +tracksRegLiveness: true +body: | + ; RV32I-LABEL: name: phi_ptr + ; RV32I: bb.0.entry: + ; RV32I-NEXT: liveins: $x10, $x11, $x12 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $x12 + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: G_BRCOND [[AND]](s32), %bb.2 + ; RV32I-NEXT: G_BR %bb.1 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.1: + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.2: + ; RV32I-NEXT: [[PHI:%[0-9]+]]:gprb(p0) = G_PHI [[COPY2]](p0), %bb.1, [[COPY1]](p0), %bb.0 + ; RV32I-NEXT: $x10 = COPY [[PHI]](p0) + ; RV32I-NEXT: PseudoRET implicit $x10 + bb.0.entry: + liveins: $x10, $x11, $x12 + + %3:_(s32) = COPY $x10 + %1:_(p0) = COPY $x11 + %2:_(p0) = COPY $x12 + %6:_(s32) = G_CONSTANT i32 1 + %5:_(s32) = G_AND %3, %6 + G_BRCOND %5(s32), %bb.2 + G_BR %bb.1 + + bb.1: + + bb.2: + %4:_(p0) = G_PHI %2(p0), %bb.1, %1(p0), %bb.0 + $x10 = COPY %4(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir new file mode 100644 index 0000000..a1537ac --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir @@ -0,0 +1,89 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- +name: phi_i64 +legalized: true +tracksRegLiveness: true +body: | + ; RV64I-LABEL: name: phi_i64 + ; RV64I: bb.0: + ; RV64I-NEXT: liveins: $x10, $x11, $x12 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY $x12 + ; RV64I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]] + ; RV64I-NEXT: G_BRCOND [[AND]](s64), %bb.2 + ; RV64I-NEXT: G_BR %bb.1 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.1: + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.2: + ; RV64I-NEXT: [[PHI:%[0-9]+]]:gprb(s64) = G_PHI [[COPY2]](s64), %bb.1, [[COPY1]](s64), %bb.0 + ; RV64I-NEXT: $x10 = COPY [[PHI]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x12 + + %3:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s64) = COPY $x12 + %6:_(s64) = G_CONSTANT i64 1 + %5:_(s64) = G_AND %3, %6 + G_BRCOND %5(s64), %bb.2 + G_BR %bb.1 + + bb.1: + + bb.2: + %4:_(s64) = G_PHI %2(s64), %bb.1, %1(s64), %bb.0 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: phi_ptr +legalized: true +tracksRegLiveness: true +body: | + ; RV64I-LABEL: name: phi_ptr + ; RV64I: bb.0: + ; RV64I-NEXT: liveins: $x10, $x11, $x12 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $x12 + ; RV64I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]] + ; RV64I-NEXT: G_BRCOND [[AND]](s64), %bb.2 + ; RV64I-NEXT: G_BR %bb.1 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.1: + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.2: + ; RV64I-NEXT: [[PHI:%[0-9]+]]:gprb(p0) = G_PHI [[COPY2]](p0), %bb.1, [[COPY1]](p0), %bb.0 + ; RV64I-NEXT: $x10 = COPY [[PHI]](p0) + ; RV64I-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x12 + + %3:_(s64) = COPY $x10 + %1:_(p0) = COPY $x11 + %2:_(p0) = COPY $x12 + %6:_(s64) = G_CONSTANT i64 1 + %5:_(s64) = G_AND %3, %6 + G_BRCOND %5(s64), %bb.2 + G_BR %bb.1 + + bb.1: + + bb.2: + %4:_(p0) = G_PHI %2(p0), %bb.1, %1(p0), %bb.0 + $x10 = COPY %4(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir new file mode 100644 index 0000000..089dd7a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv32.mir @@ -0,0 +1,24 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: ptrmask_p0_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; CHECK-LABEL: name: ptrmask_p0_s32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:gprb(p0) = G_PTRMASK [[COPY]], [[COPY1]](s32) + ; CHECK-NEXT: $x10 = COPY [[PTRMASK]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(p0) = G_PTRMASK %0(p0), %1(s32) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir new file mode 100644 index 0000000..e0e765e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ptrmask-rv64.mir @@ -0,0 +1,24 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: ptrmask_p0_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; CHECK-LABEL: name: ptrmask_p0_s64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:gprb(p0) = G_PTRMASK [[COPY]], [[COPY1]](s64) + ; CHECK-NEXT: $x10 = COPY [[PTRMASK]](p0) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(p0) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(p0) = G_PTRMASK %0(p0), %1(s64) + $x10 = COPY %2(p0) + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir new file mode 100644 index 0000000..ab3d777 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir @@ -0,0 +1,513 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +--- +name: vadd_vv_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vadd_vv_nxv1i8 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vadd_vv_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vadd_vv_nxv2i8 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vadd_vv_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vadd_vv_nxv4i8 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vadd_vv_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vadd_vv_nxv8i8 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vadd_vv_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; CHECK-LABEL: name: vadd_vv_nxv16i8 + ; CHECK: liveins: $v8m2, $v10m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: vadd_vv_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; CHECK-LABEL: name: vadd_vv_nxv32i8 + ; CHECK: liveins: $v8m4, $v12m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: vadd_vv_nxv64i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; CHECK-LABEL: name: vadd_vv_nxv64i8 + ; CHECK: liveins: $v8m8, $v16m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: vadd_vv_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vadd_vv_nxv1i16 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vadd_vv_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vadd_vv_nxv2i16 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vadd_vv_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vadd_vv_nxv4i16 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vadd_vv_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; CHECK-LABEL: name: vadd_vv_nxv8i16 + ; CHECK: liveins: $v8m2, $v10m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: vadd_vv_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; CHECK-LABEL: name: vadd_vv_nxv16i16 + ; CHECK: liveins: $v8m4, $v12m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: vadd_vv_nxv32i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; CHECK-LABEL: name: vadd_vv_nxv32i16 + ; CHECK: liveins: $v8m8, $v16m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: vadd_vv_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vadd_vv_nxv1i32 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vadd_vv_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vadd_vv_nxv2i32 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vadd_vv_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; CHECK-LABEL: name: vadd_vv_nxv4i32 + ; CHECK: liveins: $v8m2, $v10m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: vadd_vv_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; CHECK-LABEL: name: vadd_vv_nxv8i32 + ; CHECK: liveins: $v8m4, $v12m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: vadd_vv_nxv16i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; CHECK-LABEL: name: vadd_vv_nxv16i32 + ; CHECK: liveins: $v8m8, $v16m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: vadd_vv_nxv1i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vadd_vv_nxv1i64 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_ADD %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vadd_vv_nxv2i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; CHECK-LABEL: name: vadd_vv_nxv2i64 + ; CHECK: liveins: $v8m2, $v10m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v10m2 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_ADD %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: vadd_vv_nxv4i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; CHECK-LABEL: name: vadd_vv_nxv4i64 + ; CHECK: liveins: $v8m4, $v12m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v12m4 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_ADD %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: vadd_vv_nxv8i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; CHECK-LABEL: name: vadd_vv_nxv8i64 + ; CHECK: liveins: $v8m8, $v16m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v16m8 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb() = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[ADD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_ADD %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir new file mode 100644 index 0000000..4d1b11b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir @@ -0,0 +1,596 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: anyext_nxv1i16_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv1i16_nxv1i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv1i32_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv1i32_nxv1i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv1i64_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv1i64_nxv1i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i16_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv2i16_nxv2i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i32_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv2i32_nxv2i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i64_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv2i64_nxv2i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i16_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv4i16_nxv4i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv4i32_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv4i32_nxv4i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i64_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv4i64_nxv4i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i16_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv8i16_nxv8i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv8i32_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv8i32_nxv8i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i64_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv8i64_nxv8i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv16i16_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv16i16_nxv16i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m2 + %1:_() = G_ANYEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv16i32_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv16i32_nxv16i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m4 + %1:_() = G_ANYEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv32i16_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv32i16_nxv32i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m4 + %1:_() = G_ANYEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv1i32_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv1i32_nxv1i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv1i64_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv1i64_nxv1i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i32_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv2i32_nxv2i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i64_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv2i64_nxv2i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i32_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv4i32_nxv4i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i64_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv4i64_nxv4i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i32_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv8i32_nxv8i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m2 + %1:_() = G_ANYEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i64_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv8i64_nxv8i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m2 + %1:_() = G_ANYEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv16i32_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv16i32_nxv16i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m4 + %1:_() = G_ANYEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv1i64_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv1i64_nxv1i32 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i64_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv2i64_nxv2i32 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_ANYEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i64_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv4i64_nxv4i32 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m2 + %1:_() = G_ANYEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i64_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: anyext_nxv8i64_nxv8i32 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vrb() = G_ANYEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[ANYEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m4 + %1:_() = G_ANYEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir new file mode 100644 index 0000000..8447b36 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir @@ -0,0 +1,501 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: icmp_nxv1i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv1i1 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv2i1 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv4i1 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv8i1 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv16i1 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv32i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv32i1 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv64i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv64i1 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv1i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv2i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv4i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv8i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv16i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv32i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv64i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv64i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv1i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv2i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv4i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv8i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv16i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv32i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv32i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv1i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv2i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv4i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv8i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv16i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv1i64 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv2i64 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv4i64 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: icmp_nxv8i64 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vrb() = G_ICMP intpred(sgt), [[DEF]](), [[DEF]] + ; CHECK-NEXT: $v8 = COPY [[ICMP]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + %1:_() = G_ICMP intpred(sgt), %0(), %0 + $v8 = COPY %1() + PseudoRET implicit $v8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir new file mode 100644 index 0000000..017da0d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir @@ -0,0 +1,315 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +--- +name: implicitdef_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv1i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv2i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv4i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv8i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv16i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m2 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: implicitdef_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv32i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m4 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: implicitdef_nxv64i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv64i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: implicitdef_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv1i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv2i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv4i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv8i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m2 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: implicitdef_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv16i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m4 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: implicitdef_nxv32i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv32i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: implicitdef_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv1i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv2i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv4i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m2 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: implicitdef_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv8i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m4 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: implicitdef_nxv16i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv16i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: implicitdef_nxv1i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv1i64 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = G_IMPLICIT_DEF + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: implicitdef_nxv2i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv2i64 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m2 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = G_IMPLICIT_DEF + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: implicitdef_nxv4i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv4i64 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m4 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = G_IMPLICIT_DEF + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: implicitdef_nxv8i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicitdef_nxv8i64 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: $v8m8 = COPY [[DEF]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = G_IMPLICIT_DEF + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir new file mode 100644 index 0000000..b58e87c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir @@ -0,0 +1,1134 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +--- | + + define @vload_nx1i8(ptr %pa) #0 { + %va = load , ptr %pa, align 1 + ret %va + } + + define @vload_nx2i8(ptr %pa) #0 { + %va = load , ptr %pa, align 2 + ret %va + } + + define @vload_nx4i8(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nx8i8(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nx16i8(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nx32i8(ptr %pa) #0 { + %va = load , ptr %pa, align 32 + ret %va + } + + define @vload_nx64i8(ptr %pa) #0 { + %va = load , ptr %pa, align 64 + ret %va + } + + define @vload_nx1i16(ptr %pa) #0 { + %va = load , ptr %pa, align 2 + ret %va + } + + define @vload_nx2i16(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nx4i16(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nx8i16(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nx16i16(ptr %pa) #0 { + %va = load , ptr %pa, align 32 + ret %va + } + + define @vload_nx32i16(ptr %pa) #0 { + %va = load , ptr %pa, align 64 + ret %va + } + + define @vload_nx1i32(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nx2i32(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nx4i32(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nx8i32(ptr %pa) #0 { + %va = load , ptr %pa, align 32 + ret %va + } + + define @vload_nx16i32(ptr %pa) #0 { + %va = load , ptr %pa, align 64 + ret %va + } + + define @vload_nx1i64(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nx2i64(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nx4i64(ptr %pa) #0 { + %va = load , ptr %pa, align 32 + ret %va + } + + define @vload_nx8i64(ptr %pa) #0 { + %va = load , ptr %pa, align 64 + ret %va + } + + define @vload_nx16i8_align1(ptr %pa) #0 { + %va = load , ptr %pa, align 1 + ret %va + } + + define @vload_nx16i8_align2(ptr %pa) #0 { + %va = load , ptr %pa, align 2 + ret %va + } + + define @vload_nx16i8_align16(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nx16i8_align64(ptr %pa) #0 { + %va = load , ptr %pa, align 64 + ret %va + } + + define @vload_nx4i16_align1(ptr %pa) #0 { + %va = load , ptr %pa, align 1 + ret %va + } + + define @vload_nx4i16_align2(ptr %pa) #0 { + %va = load , ptr %pa, align 2 + ret %va + } + + define @vload_nx4i16_align4(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nx4i16_align8(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nx4i16_align16(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nx2i32_align2(ptr %pa) #0 { + %va = load , ptr %pa, align 2 + ret %va + } + + define @vload_nx2i32_align4(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nx2i32_align8(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nx2i32_align16(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nx2i32_align256(ptr %pa) #0 { + %va = load , ptr %pa, align 256 + ret %va + } + + define @vload_nx2i64_align4(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nx2i64_align8(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nx2i64_align16(ptr %pa) #0 { + %va = load , ptr %pa, align 16 + ret %va + } + + define @vload_nx2i64_align32(ptr %pa) #0 { + %va = load , ptr %pa, align 32 + ret %va + } + + define @vload_nx1ptr(ptr %pa) #0 { + %va = load , ptr %pa, align 4 + ret %va + } + + define @vload_nx2ptr(ptr %pa) #0 { + %va = load , ptr %pa, align 8 + ret %va + } + + define @vload_nx8ptr(ptr %pa) #0 { + %va = load , ptr %pa, align 32 + ret %va + } + +... +--- +name: vload_nx1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx1i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx4i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx8i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx16i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nx32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx32i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m4 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: vload_nx64i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx64i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: vload_nx1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx1i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx4i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx8i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nx16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx16i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m4 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: vload_nx32i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx32i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: vload_nx1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx1i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx4i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nx8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx8i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m4 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: vload_nx16i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx16i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: vload_nx1i64 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx1i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx2i64 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nx4i64 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx4i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m4 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: vload_nx8i64 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx8i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: vload_nx16i8_align1 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx16i8_align1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 1) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 1) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nx16i8_align2 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx16i8_align2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 2) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nx16i8_align16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx16i8_align16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nx16i8_align64 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx16i8_align64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 64) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nx4i16_align1 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx4i16_align1 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 1) + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:vrb() = G_BITCAST [[LOAD]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %2:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 1) + %1:_() = G_BITCAST %2() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx4i16_align2 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx4i16_align2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 2) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx4i16_align4 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx4i16_align4 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 4) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx4i16_align8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx4i16_align8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx4i16_align16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx4i16_align16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 16) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx2i32_align2 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i32_align2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:vrb() = G_BITCAST [[LOAD]]() + ; CHECK-NEXT: $v8 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %2:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 2) + %1:_() = G_BITCAST %2() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx2i32_align4 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i32_align4 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 4) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx2i32_align8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i32_align8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx2i32_align16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i32_align16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 16) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx2i32_align256 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i32_align256 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 256) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 256) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx2i64_align4 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i64_align4 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:vrb() = G_BITCAST [[LOAD]]() + ; CHECK-NEXT: $v8m2 = COPY [[BITCAST]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %2:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 4) + %1:_() = G_BITCAST %2() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nx2i64_align8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i64_align8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 8) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nx2i64_align16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i64_align16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nx2i64_align32 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2i64_align32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; CHECK-NEXT: $v8m2 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa, align 32) + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: vload_nx1ptr +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx1ptr + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx2ptr +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx2ptr + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: vload_nx8ptr +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vload_nx8ptr + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; CHECK-NEXT: $v8m4 = COPY [[LOAD]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(p0) = COPY $x10 + %1:_() = G_LOAD %0(p0) :: (load () from %ir.pa) + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir new file mode 100644 index 0000000..7e2badb --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir @@ -0,0 +1,404 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: select_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv1i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv2i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv4i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv8i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv16i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m2 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: select_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv32i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m4 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: select_nxv64i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv64i8 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: select_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv1i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv2i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv4i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv8i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m2 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: select_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv16i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m4 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: select_nxv32i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv32i16 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: select_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv1i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv2i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv4i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m2 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: select_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv8i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m4 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: select_nxv16i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv16i32 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... +--- +name: select_nxv1i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv1i64 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8 = COPY %0() + PseudoRET implicit $v8 +... +--- +name: select_nxv2i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv2i64 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m2 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 +... +--- +name: select_nxv4i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv4i64 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m4 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 +... +--- +name: select_nxv8i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: select_nxv8i64 + ; CHECK: [[DEF:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vrb() = G_IMPLICIT_DEF + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vrb() = G_SELECT [[DEF]](), [[DEF1]], [[DEF1]] + ; CHECK-NEXT: $v8m8 = COPY [[SELECT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_() = G_IMPLICIT_DEF + %2:_() = G_IMPLICIT_DEF + %0:_() = G_SELECT %1(), %2(), %2() + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir new file mode 100644 index 0000000..efd7f13 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir @@ -0,0 +1,596 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: sext_nxv1i16_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv1i16_nxv1i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv1i32_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv1i32_nxv1i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv1i64_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv1i64_nxv1i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i16_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv2i16_nxv2i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i32_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv2i32_nxv2i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i64_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv2i64_nxv2i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i16_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv4i16_nxv4i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv4i32_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv4i32_nxv4i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i64_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv4i64_nxv4i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i16_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv8i16_nxv8i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv8i32_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv8i32_nxv8i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i64_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv8i64_nxv8i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv16i16_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv16i16_nxv16i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m2 + %1:_() = G_SEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv16i32_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv16i32_nxv16i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m2 + %1:_() = G_SEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv32i16_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv32i16_nxv32i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m4 + %1:_() = G_SEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv1i32_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv1i32_nxv1i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv1i64_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv1i64_nxv1i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i32_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv2i32_nxv2i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i64_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv2i64_nxv2i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i32_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv4i32_nxv4i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i64_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv4i64_nxv4i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i32_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv8i32_nxv8i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m2 + %1:_() = G_SEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i64_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv8i64_nxv8i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m2 + %1:_() = G_SEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv16i32_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv16i32_nxv16i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m4 + %1:_() = G_SEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv1i64_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv1i64_nxv1i32 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i64_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv2i64_nxv2i32 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_SEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i64_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv4i64_nxv4i32 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m2 + %1:_() = G_SEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i64_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: sext_nxv8i64_nxv8i32 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vrb() = G_SEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[SEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m4 + %1:_() = G_SEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv32.mir new file mode 100644 index 0000000..38d3e83 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv32.mir @@ -0,0 +1,549 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: splat_zero_nxv1i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv2i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv4i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv8i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv16i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv16i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: splat_zero_nxv32i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv32i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: splat_zero_nxv64i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv64i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: splat_zero_nxv1i16 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1i16 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv2i16 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2i16 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv4i16 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4i16 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv8i16 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8i16 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: splat_zero_nxv16i16 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv16i16 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: splat_zero_nxv32i16 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv32i16 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %3:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %3(s32) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: splat_zero_nxv1i32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1i32 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %1(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv2i32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2i32 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %1(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv4i32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4i32 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %1(s32) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: splat_zero_nxv8i32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8i32 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %1(s32) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: splat_zero_nxv16i32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv16i32 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_(s32) = G_CONSTANT i32 0 + %0:_() = G_SPLAT_VECTOR %1(s32) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: splat_zero_nxv1i64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1i64 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[MV]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %2:_(s32) = G_CONSTANT i32 0 + %3:_(s32) = G_CONSTANT i32 0 + %1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv2i64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2i64 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[MV]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %2:_(s32) = G_CONSTANT i32 0 + %3:_(s32) = G_CONSTANT i32 0 + %1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: splat_zero_nxv4i64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4i64 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[MV]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %2:_(s32) = G_CONSTANT i32 0 + %3:_(s32) = G_CONSTANT i32 0 + %1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: splat_zero_nxv8i64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8i64 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[MV]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %2:_(s32) = G_CONSTANT i32 0 + %3:_(s32) = G_CONSTANT i32 0 + %1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... + +--- +name: splat_zero_nxv1f32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1f32 + ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_FCONSTANT float 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv2f32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2f32 + ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_FCONSTANT float 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s32) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv4f32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4f32 + ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s32) = G_FCONSTANT float 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s32) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: splat_zero_nxv8f32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8f32 + ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s32) = G_FCONSTANT float 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s32) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: splat_zero_nxv16f32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv16f32 + ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_(s32) = G_FCONSTANT float 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s32) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: splat_zero_nxv1f64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1f64 + ; CHECK: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s64) = G_FCONSTANT double 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv2f64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2f64 + ; CHECK: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s64) = G_FCONSTANT double 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: splat_zero_nxv4f64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4f64 + ; CHECK: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s64) = G_FCONSTANT double 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: splat_zero_nxv8f64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8f64 + ; CHECK: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_(s64) = G_FCONSTANT double 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv64.mir new file mode 100644 index 0000000..efd5237 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/splatvector-rv64.mir @@ -0,0 +1,583 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: splat_zero_nxv1i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv2i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv4i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv8i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv16i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv16i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: splat_zero_nxv32i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv32i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: splat_zero_nxv64i8 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv64i8 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: splat_zero_nxv1i16 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1i16 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv2i16 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2i16 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv4i16 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4i16 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv8i16 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8i16 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: splat_zero_nxv16i16 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv16i16 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: splat_zero_nxv32i16 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv32i16 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %3:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %3(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: splat_zero_nxv1i32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1i32 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %1(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv2i32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2i32 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %1(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv4i32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4i32 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %1(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: splat_zero_nxv8i32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8i32 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %1(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: splat_zero_nxv16i32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv16i32 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s64) = G_ANYEXT %1(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: splat_zero_nxv1i64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1i64 + ; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s64) = G_CONSTANT i64 0 + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv2i64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2i64 + ; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s64) = G_CONSTANT i64 0 + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: splat_zero_nxv4i64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4i64 + ; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s64) = G_CONSTANT i64 0 + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: splat_zero_nxv8i64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8i64 + ; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_(s64) = G_CONSTANT i64 0 + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: splat_zero_nxv1f32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1f32 + ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[COPY]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_FCONSTANT float 0.000000e+00 + %2:_(s64) = G_ANYEXT %1(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv2f32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2f32 + ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[COPY]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_FCONSTANT float 0.000000e+00 + %2:_(s64) = G_ANYEXT %1(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv4f32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4f32 + ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[COPY]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s32) = G_FCONSTANT float 0.000000e+00 + %2:_(s64) = G_ANYEXT %1(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: splat_zero_nxv8f32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8f32 + ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[COPY]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s32) = G_FCONSTANT float 0.000000e+00 + %2:_(s64) = G_ANYEXT %1(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: splat_zero_nxv16f32 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv16f32 + ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[COPY]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_(s32) = G_FCONSTANT float 0.000000e+00 + %2:_(s64) = G_ANYEXT %1(s32) + %0:_() = G_SPLAT_VECTOR %2(s64) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: splat_zero_nxv1f64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1f64 + ; CHECK: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s64) = G_FCONSTANT double 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: splat_zero_nxv2f64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2f64 + ; CHECK: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s64) = G_FCONSTANT double 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: splat_zero_nxv4f64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4f64 + ; CHECK: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s64) = G_FCONSTANT double 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: splat_zero_nxv8f64 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8f64 + ; CHECK: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0.000000e+00 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb() = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_(s64) = G_FCONSTANT double 0.000000e+00 + %0:_() = G_SPLAT_VECTOR %1(s64) + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir new file mode 100644 index 0000000..3a6a238 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir @@ -0,0 +1,1134 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +--- | + + define void @vstore_nx1i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 1 + ret void + } + + define void @vstore_nx2i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 2 + ret void + } + + define void @vstore_nx4i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx8i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx16i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx32i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 32 + ret void + } + + define void @vstore_nx64i8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 64 + ret void + } + + define void @vstore_nx1i16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 2 + ret void + } + + define void @vstore_nx2i16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx4i16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx8i16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx16i16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 32 + ret void + } + + define void @vstore_nx32i16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 64 + ret void + } + + define void @vstore_nx1i32(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx2i32(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx4i32(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx8i32(ptr %pa, %b) #0 { + store %b, ptr %pa, align 32 + ret void + } + + define void @vstore_nx16i32(ptr %pa, %b) #0 { + store %b, ptr %pa, align 64 + ret void + } + + define void @vstore_nx1i64(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx2i64(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx4i64(ptr %pa, %b) #0 { + store %b, ptr %pa, align 32 + ret void + } + + define void @vstore_nx8i64(ptr %pa, %b) #0 { + store %b, ptr %pa, align 64 + ret void + } + + define void @vstore_nx16i8_align1(ptr %pa, %b) #0 { + store %b, ptr %pa, align 1 + ret void + } + + define void @vstore_nx16i8_align2(ptr %pa, %b) #0 { + store %b, ptr %pa, align 2 + ret void + } + + define void @vstore_nx16i8_align16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx16i8_align64(ptr %pa, %b) #0 { + store %b, ptr %pa, align 64 + ret void + } + + define void @vstore_nx4i16_align1(ptr %pa, %b) #0 { + store %b, ptr %pa, align 1 + ret void + } + + define void @vstore_nx4i16_align2(ptr %pa, %b) #0 { + store %b, ptr %pa, align 2 + ret void + } + + define void @vstore_nx4i16_align4(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx4i16_align8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx4i16_align16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx2i32_align2(ptr %pa, %b) #0 { + store %b, ptr %pa, align 2 + ret void + } + + define void @vstore_nx2i32_align4(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx2i32_align8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx2i32_align16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx2i32_align256(ptr %pa, %b) #0 { + store %b, ptr %pa, align 256 + ret void + } + + define void @vstore_nx2i64_align4(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx2i64_align8(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx2i64_align16(ptr %pa, %b) #0 { + store %b, ptr %pa, align 16 + ret void + } + + define void @vstore_nx2i64_align32(ptr %pa, %b) #0 { + store %b, ptr %pa, align 32 + ret void + } + + define void @vstore_nx1ptr(ptr %pa, %b) #0 { + store %b, ptr %pa, align 4 + ret void + } + + define void @vstore_nx2ptr(ptr %pa, %b) #0 { + store %b, ptr %pa, align 8 + ret void + } + + define void @vstore_nx8ptr(ptr %pa, %b) #0 { + store %b, ptr %pa, align 32 + ret void + } + +... +--- +name: vstore_nx1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx1i8 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i8 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i8 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx8i8 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx16i8 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m4 + + ; CHECK-LABEL: name: vstore_nx32i8 + ; CHECK: liveins: $x10, $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m4 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx64i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m8 + + ; CHECK-LABEL: name: vstore_nx64i8 + ; CHECK: liveins: $x10, $v8m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx1i16 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i16 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i16 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx8i16 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m4 + + ; CHECK-LABEL: name: vstore_nx16i16 + ; CHECK: liveins: $x10, $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m4 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx32i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m8 + + ; CHECK-LABEL: name: vstore_nx32i16 + ; CHECK: liveins: $x10, $v8m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx1i32 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i32 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx4i32 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m4 + + ; CHECK-LABEL: name: vstore_nx8i32 + ; CHECK: liveins: $x10, $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m4 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx16i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m8 + + ; CHECK-LABEL: name: vstore_nx16i32 + ; CHECK: liveins: $x10, $v8m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx1i64 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx1i64 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2i64 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx2i64 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx4i64 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m4 + + ; CHECK-LABEL: name: vstore_nx4i64 + ; CHECK: liveins: $x10, $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m4 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx8i64 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m8 + + ; CHECK-LABEL: name: vstore_nx8i64 + ; CHECK: liveins: $x10, $v8m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx16i8_align1 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx16i8_align1 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 1) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 1) + PseudoRET + +... +--- +name: vstore_nx16i8_align2 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx16i8_align2 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 2) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 2) + PseudoRET + +... +--- +name: vstore_nx16i8_align16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx16i8_align16 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx16i8_align64 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx16i8_align64 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 64) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 64) + PseudoRET + +... +--- +name: vstore_nx4i16_align1 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i16_align1 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:vrb() = G_BITCAST [[COPY1]]() + ; CHECK-NEXT: G_STORE [[BITCAST]](), [[COPY]](p0) :: (store () into %ir.pa, align 1) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + %2:_() = G_BITCAST %1() + G_STORE %2(), %0(p0) :: (store () into %ir.pa, align 1) + PseudoRET + +... +--- +name: vstore_nx4i16_align2 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i16_align2 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 2) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 2) + PseudoRET + +... +--- +name: vstore_nx4i16_align4 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i16_align4 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 4) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 4) + PseudoRET + +... +--- +name: vstore_nx4i16_align8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i16_align8 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx4i16_align16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx4i16_align16 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 16) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 16) + PseudoRET + +... +--- +name: vstore_nx2i32_align2 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i32_align2 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:vrb() = G_BITCAST [[COPY1]]() + ; CHECK-NEXT: G_STORE [[BITCAST]](), [[COPY]](p0) :: (store () into %ir.pa, align 2) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + %2:_() = G_BITCAST %1() + G_STORE %2(), %0(p0) :: (store () into %ir.pa, align 2) + PseudoRET + +... +--- +name: vstore_nx2i32_align4 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i32_align4 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 4) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 4) + PseudoRET + +... +--- +name: vstore_nx2i32_align8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i32_align8 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2i32_align16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i32_align16 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 16) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 16) + PseudoRET + +... +--- +name: vstore_nx2i32_align256 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2i32_align256 + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 256) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 256) + PseudoRET + +... +--- +name: vstore_nx2i64_align4 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx2i64_align4 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:vrb() = G_BITCAST [[COPY1]]() + ; CHECK-NEXT: G_STORE [[BITCAST]](), [[COPY]](p0) :: (store () into %ir.pa, align 4) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + %2:_() = G_BITCAST %1() + G_STORE %2(), %0(p0) :: (store () into %ir.pa, align 4) + PseudoRET + +... +--- +name: vstore_nx2i64_align8 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx2i64_align8 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 8) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 8) + PseudoRET + +... +--- +name: vstore_nx2i64_align16 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx2i64_align16 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2i64_align32 +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m2 + + ; CHECK-LABEL: name: vstore_nx2i64_align32 + ; CHECK: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa, align 32) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m2 + G_STORE %1(), %0(p0) :: (store () into %ir.pa, align 32) + PseudoRET + +... +--- +name: vstore_nx1ptr +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx1ptr + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx2ptr +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $v8, $x10 + + ; CHECK-LABEL: name: vstore_nx2ptr + ; CHECK: liveins: $v8, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... +--- +name: vstore_nx8ptr +legalized: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $x10, $v8m4 + + ; CHECK-LABEL: name: vstore_nx8ptr + ; CHECK: liveins: $x10, $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: G_STORE [[COPY1]](), [[COPY]](p0) :: (store () into %ir.pa) + ; CHECK-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_() = COPY $v8m4 + G_STORE %1(), %0(p0) :: (store () into %ir.pa) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir new file mode 100644 index 0000000..c18423c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir @@ -0,0 +1,513 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +--- +name: vsub_vv_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vsub_vv_nxv1i8 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vsub_vv_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vsub_vv_nxv2i8 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vsub_vv_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vsub_vv_nxv4i8 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vsub_vv_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vsub_vv_nxv8i8 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vsub_vv_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; CHECK-LABEL: name: vsub_vv_nxv16i8 + ; CHECK: liveins: $v8m2, $v10m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v10m2 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: vsub_vv_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; CHECK-LABEL: name: vsub_vv_nxv32i8 + ; CHECK: liveins: $v8m4, $v12m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v12m4 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: vsub_vv_nxv64i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; CHECK-LABEL: name: vsub_vv_nxv64i8 + ; CHECK: liveins: $v8m8, $v16m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v16m8 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: vsub_vv_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vsub_vv_nxv1i16 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vsub_vv_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vsub_vv_nxv2i16 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vsub_vv_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vsub_vv_nxv4i16 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vsub_vv_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; CHECK-LABEL: name: vsub_vv_nxv8i16 + ; CHECK: liveins: $v8m2, $v10m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v10m2 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: vsub_vv_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; CHECK-LABEL: name: vsub_vv_nxv16i16 + ; CHECK: liveins: $v8m4, $v12m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v12m4 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: vsub_vv_nxv32i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; CHECK-LABEL: name: vsub_vv_nxv32i16 + ; CHECK: liveins: $v8m8, $v16m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v16m8 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: vsub_vv_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vsub_vv_nxv1i32 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vsub_vv_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vsub_vv_nxv2i32 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vsub_vv_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; CHECK-LABEL: name: vsub_vv_nxv4i32 + ; CHECK: liveins: $v8m2, $v10m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v10m2 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: vsub_vv_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; CHECK-LABEL: name: vsub_vv_nxv8i32 + ; CHECK: liveins: $v8m4, $v12m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v12m4 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: vsub_vv_nxv16i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; CHECK-LABEL: name: vsub_vv_nxv16i32 + ; CHECK: liveins: $v8m8, $v16m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v16m8 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... +--- +name: vsub_vv_nxv1i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9 + + ; CHECK-LABEL: name: vsub_vv_nxv1i64 + ; CHECK: liveins: $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v9 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = COPY $v9 + %2:_() = G_SUB %0, %1 + $v8 = COPY %2() + PseudoRET implicit $v8 + +... +--- +name: vsub_vv_nxv2i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2 + + ; CHECK-LABEL: name: vsub_vv_nxv2i64 + ; CHECK: liveins: $v8m2, $v10m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v10m2 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8m2 + %1:_() = COPY $v10m2 + %2:_() = G_SUB %0, %1 + $v8m2 = COPY %2() + PseudoRET implicit $v8m2 + +... +--- +name: vsub_vv_nxv4i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m4, $v12m4 + + ; CHECK-LABEL: name: vsub_vv_nxv4i64 + ; CHECK: liveins: $v8m4, $v12m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v12m4 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m4 + %1:_() = COPY $v12m4 + %2:_() = G_SUB %0, %1 + $v8m4 = COPY %2() + PseudoRET implicit $v8m4 + +... +--- +name: vsub_vv_nxv8i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m8, $v16m8 + + ; CHECK-LABEL: name: vsub_vv_nxv8i64 + ; CHECK: liveins: $v8m8, $v16m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb() = COPY $v16m8 + ; CHECK-NEXT: [[SUB:%[0-9]+]]:vrb() = G_SUB [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[SUB]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m8 + %1:_() = COPY $v16m8 + %2:_() = G_SUB %0, %1 + $v8m8 = COPY %2() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir new file mode 100644 index 0000000..abab3cc --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir @@ -0,0 +1,125 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: splat_zero_nxv1i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = G_CONSTANT i32 -1 + %1:_() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv2i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = G_CONSTANT i32 -1 + %1:_() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv4i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = G_CONSTANT i32 -1 + %1:_() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv8i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = G_CONSTANT i32 -1 + %1:_() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv16i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv16i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = G_CONSTANT i32 -1 + %1:_() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv32i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv32i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = G_CONSTANT i32 -1 + %1:_() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv64i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv64i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s32) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = G_CONSTANT i32 -1 + %1:_() = G_VMCLR_VL %0(s32) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir new file mode 100644 index 0000000..d4d7012 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir @@ -0,0 +1,125 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: splat_zero_nxv1i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv1i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = G_CONSTANT i64 -1 + %1:_() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv2i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv2i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = G_CONSTANT i64 -1 + %1:_() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv4i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv4i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = G_CONSTANT i64 -1 + %1:_() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv8i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv8i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = G_CONSTANT i64 -1 + %1:_() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv16i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv16i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = G_CONSTANT i64 -1 + %1:_() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv32i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv32i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = G_CONSTANT i64 -1 + %1:_() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... +--- +name: splat_zero_nxv64i1 +legalized: true +regBankSelected: false +body: | + bb.1: + ; CHECK-LABEL: name: splat_zero_nxv64i1 + ; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb() = G_VMCLR_VL [[C]](s64) + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]]() + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = G_CONSTANT i64 -1 + %1:_() = G_VMCLR_VL %0(s64) + $v0 = COPY %1() + PseudoRET implicit $v0 + +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir new file mode 100644 index 0000000..1d8e676 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir @@ -0,0 +1,48 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: test_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = G_READ_VLENB + %2:_(s32) = G_CONSTANT i32 3 + %0:_(s32) = G_LSHR %1, %2(s32) + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:_(s32) = G_READ_VLENB + %18:_(s32) = G_CONSTANT i32 3 + %2:_(s32) = G_LSHR %17, %18(s32) + %15:_(s32) = G_CONSTANT i32 1 + %9:_(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir new file mode 100644 index 0000000..47117dc --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir @@ -0,0 +1,25 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: test +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test + ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[READ_VLENB]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = G_READ_VLENB + %2:_(s64) = G_CONSTANT i64 3 + %0:_(s64) = G_LSHR %1, %2(s64) + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir new file mode 100644 index 0000000..5070c58 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir @@ -0,0 +1,596 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: zext_nxv1i16_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv1i16_nxv1i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv1i32_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv1i32_nxv1i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv1i64_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv1i64_nxv1i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i16_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv2i16_nxv2i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i32_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv2i32_nxv2i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i64_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv2i64_nxv2i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i16_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv4i16_nxv4i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv4i32_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv4i32_nxv4i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i64_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv4i64_nxv4i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i16_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv8i16_nxv8i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv8i32_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv8i32_nxv8i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i64_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv8i64_nxv8i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv16i16_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv16i16_nxv16i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m2 + %1:_() = G_ZEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv16i32_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv16i32_nxv16i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m2 + %1:_() = G_ZEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv32i16_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv32i16_nxv32i8 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m4 + %1:_() = G_ZEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv1i32_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv1i32_nxv1i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv1i64_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv1i64_nxv1i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i32_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv2i32_nxv2i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i64_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv2i64_nxv2i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i32_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv4i32_nxv4i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i64_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv4i64_nxv4i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i32_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv8i32_nxv8i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m2 + %1:_() = G_ZEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i64_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv8i64_nxv8i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m4 + %1:_() = G_ZEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv16i32_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv16i32_nxv16i16 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m4 + %1:_() = G_ZEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv1i64_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv1i64_nxv1i32 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8 = COPY %1() + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i64_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv2i64_nxv2i32 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m2 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + %1:_() = G_ZEXT %0() + $v8m2 = COPY %1() + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i64_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv4i64_nxv4i32 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m2 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m4 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8m2 + %1:_() = G_ZEXT %0() + $v8m4 = COPY %1() + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i64_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: zext_nxv8i64_nxv8i32 + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8m4 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:vrb() = G_ZEXT [[COPY]]() + ; CHECK-NEXT: $v8m8 = COPY [[ZEXT]]() + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8m4 + %1:_() = G_ZEXT %0() + $v8m8 = COPY %1() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir new file mode 100644 index 0000000..5252b25 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir @@ -0,0 +1,63 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s + +--- +name: select_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; RV32I-LABEL: name: select_i32 + ; RV32I: liveins: $x10, $x11, $x12 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x12 + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + %3:_(s32) = COPY $x10 + %4:_(s32) = COPY $x11 + %5:_(s32) = COPY $x12 + %12:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_AND %3, %12 + %10:_(s32) = G_SELECT %11(s32), %4, %5 + $x10 = COPY %10(s32) + PseudoRET implicit $x10 + +... +--- +name: select_ptr +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; RV32I-LABEL: name: select_ptr + ; RV32I: liveins: $x10, $x11, $x12 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $x12 + ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]] + ; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] + ; RV32I-NEXT: $x10 = COPY [[SELECT]](p0) + ; RV32I-NEXT: PseudoRET implicit $x10 + %3:_(s32) = COPY $x10 + %4:_(p0) = COPY $x11 + %5:_(p0) = COPY $x12 + %12:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_AND %3, %12 + %10:_(p0) = G_SELECT %11(s32), %4, %5 + $x10 = COPY %10(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir new file mode 100644 index 0000000..47d396f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir @@ -0,0 +1,63 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- +name: select_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; RV64I-LABEL: name: select_i64 + ; RV64I: liveins: $x10, $x11, $x12 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY $x12 + ; RV64I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:gprb(s64) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]] + ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + %3:_(s64) = COPY $x10 + %4:_(s64) = COPY $x11 + %5:_(s64) = COPY $x12 + %12:_(s64) = G_CONSTANT i64 1 + %11:_(s64) = G_AND %3, %12 + %10:_(s64) = G_SELECT %11(s64), %4, %5 + $x10 = COPY %10(s64) + PseudoRET implicit $x10 + +... +--- +name: select_ptr +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; RV64I-LABEL: name: select_ptr + ; RV64I: liveins: $x10, $x11, $x12 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $x12 + ; RV64I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1 + ; RV64I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]] + ; RV64I-NEXT: [[SELECT:%[0-9]+]]:gprb(p0) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]] + ; RV64I-NEXT: $x10 = COPY [[SELECT]](p0) + ; RV64I-NEXT: PseudoRET implicit $x10 + %3:_(s64) = COPY $x10 + %4:_(p0) = COPY $x11 + %5:_(p0) = COPY $x12 + %12:_(s64) = G_CONSTANT i64 1 + %11:_(s64) = G_AND %3, %12 + %10:_(p0) = G_SELECT %11(s64), %4, %5 + $x10 = COPY %10(p0) + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir new file mode 100644 index 0000000..544c3bb --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir @@ -0,0 +1,89 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s + +--- +name: store_i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: store_i8 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV32I-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s8)) + ; RV32I-NEXT: PseudoRET + %2:_(s32) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %2(s32), %1(p0) :: (store (s8)) + PseudoRET + +... +--- +name: store_i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: store_i16 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV32I-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s16)) + ; RV32I-NEXT: PseudoRET + %2:_(s32) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %2(s32), %1(p0) :: (store (s16)) + PseudoRET + +... +--- +name: store_i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: store_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV32I-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32)) + ; RV32I-NEXT: PseudoRET + %0:_(s32) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %0(s32), %1(p0) :: (store (s32)) + PseudoRET + +... +--- +name: store_ptr +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: store_ptr + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV32I-NEXT: G_STORE [[COPY]](p0), [[COPY1]](p0) :: (store (p0), align 8) + ; RV32I-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %0(p0), %1(p0) :: (store (p0), align 8) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir new file mode 100644 index 0000000..c3475dd --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir @@ -0,0 +1,113 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- +name: store_i8 +legalized: true +body: | + bb.0: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: store_i8 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s8)) + ; RV64I-NEXT: PseudoRET + %2:_(s64) = COPY $x10 + %1:_(p0) = COPY $x11 + %3:_(s32) = G_TRUNC %2(s64) + G_STORE %3(s32), %1(p0) :: (store (s8)) + PseudoRET + +... +--- +name: store_i16 +legalized: true +body: | + bb.0: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: store_i16 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s16)) + ; RV64I-NEXT: PseudoRET + %2:_(s64) = COPY $x10 + %1:_(p0) = COPY $x11 + %3:_(s32) = G_TRUNC %2(s64) + G_STORE %3(s32), %1(p0) :: (store (s16)) + PseudoRET + +... +--- +name: store_i32 +legalized: true +body: | + bb.0: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: store_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s32)) + ; RV64I-NEXT: PseudoRET + %2:_(s64) = COPY $x10 + %1:_(p0) = COPY $x11 + %3:_(s32) = G_TRUNC %2(s64) + G_STORE %3(s32), %1(p0) :: (store (s32)) + PseudoRET + +... +--- +name: store_i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: store_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV64I-NEXT: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store (s64)) + ; RV64I-NEXT: PseudoRET + %0:_(s64) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %0(s64), %1(p0) :: (store (s64)) + PseudoRET + +... +--- +name: store_ptr +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; RV64I-LABEL: name: store_ptr + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11 + ; RV64I-NEXT: G_STORE [[COPY]](p0), [[COPY1]](p0) :: (store (p0)) + ; RV64I-NEXT: PseudoRET + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + G_STORE %0(p0), %1(p0) :: (store (p0)) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir new file mode 100644 index 0000000..9ed3b67 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir @@ -0,0 +1,1259 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefixes=RV32 %s +# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \ +# RUN: -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefixes=RV64 %s + +... +--- +name: test_ret_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m2 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: test_ret_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m2 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: test_ret_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv32i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m4 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: test_ret_nxv32i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m4 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: test_ret_nxv64i8 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv64i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: test_ret_nxv64i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8 + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: test_ret_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m2 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: test_ret_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m2 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: test_ret_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv16i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m4 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: test_ret_nxv16i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m4 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: test_ret_nxv32i16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv32i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: test_ret_nxv32i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8 + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: test_ret_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv1i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv1i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv2i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv2i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv4i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m2 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: test_ret_nxv4i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m2 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: test_ret_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv8i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m4 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: test_ret_nxv8i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m4 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: test_ret_nxv16i32 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv16i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: test_ret_nxv16i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8 + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: test_ret_nxv1i64 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv1i64 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv1i64 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv2i64 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv2i64 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m2 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: test_ret_nxv2i64 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m2 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: test_ret_nxv4i64 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv4i64 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m4 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: test_ret_nxv4i64 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m4 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: test_ret_nxv8i64 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv8i64 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: test_ret_nxv8i64 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8 + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: test_ret_nxv64i1 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv64i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv64i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv32i1 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv32i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv32i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv16i1 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv16i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv16i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv8i1 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv8i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv8i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv4i1 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv4i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv4i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv2i1 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv2i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv2i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv1i1 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv1i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv1i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv1f32 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv1f32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv1f32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv2f32 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv2f32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv2f32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv4f32 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv4f32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m2 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: test_ret_nxv4f32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m2 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: test_ret_nxv8f32 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv8f32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m4 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: test_ret_nxv8f32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m4 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: test_ret_nxv16f32 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv16f32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: test_ret_nxv16f32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8 + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: test_ret_nxv1f64 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv1f64 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv1f64 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv2f64 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv2f64 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m2 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: test_ret_nxv2f64 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m2 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: test_ret_nxv4f64 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv4f64 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m4 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: test_ret_nxv4f64 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m4 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: test_ret_nxv8f64 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv8f64 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: test_ret_nxv8f64 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8 + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: test_ret_nxv1f16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv1f16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv1f16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv2f16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv2f16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv2f16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv4f16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv4f16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv4f16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv8f16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv8f16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m2 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: test_ret_nxv8f16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m2 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: test_ret_nxv16f16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv16f16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m4 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: test_ret_nxv16f16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m4 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: test_ret_nxv32f16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv32f16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: test_ret_nxv32f16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8 + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... +--- +name: test_ret_nxv1b16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv1b16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv1b16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv2b16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv2b16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv2b16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv4b16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv4b16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: test_ret_nxv4b16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_() = COPY $v8 + $v8 = COPY %0() + PseudoRET implicit $v8 + +... +--- +name: test_ret_nxv8b16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv8b16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m2 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: test_ret_nxv8b16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m2 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %0:_() = COPY $v8 + $v8m2 = COPY %0() + PseudoRET implicit $v8m2 + +... +--- +name: test_ret_nxv16b16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv16b16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m4 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: test_ret_nxv16b16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m4 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %0:_() = COPY $v8 + $v8m4 = COPY %0() + PseudoRET implicit $v8m4 + +... +--- +name: test_ret_nxv32b16 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $v8 + ; RV32-LABEL: name: test_ret_nxv32b16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV32-NEXT: $v8m8 = COPY [[COPY]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: test_ret_nxv32b16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:vrb() = COPY $v8 + ; RV64-NEXT: $v8m8 = COPY [[COPY]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %0:_() = COPY $v8 + $v8m8 = COPY %0() + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir new file mode 100644 index 0000000..8f5c763 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir @@ -0,0 +1,34 @@ +# RUN: llc -mtriple=riscv32 %s -run-pass=machine-sink -o - | FileCheck %s +# RUN: llc -mtriple=riscv32 %s -passes=machine-sink -o - | FileCheck %s + +# Verify that sinking of '%20:gpr = LUI 1, implicit $x0' is not inhibited by +# the implicit use of '$x0'. +# Register '$x0' is a 'MRI->isConstantPhysReg()' on RISCV and such uses should +# not inhibit sinking transformation even though they are livein to the block +# they are to be sunk into (inhibit under such conditions should only happen +# for defines). + +--- +name: f +tracksRegLiveness: true +body: | + ; CHECK-LABEL: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1, implicit $x0 + bb.0: + liveins: $x10 + %10:gpr = COPY $x10 + %20:gpr = LUI 1, implicit $x0 + BEQ %10, %10, %bb.2 + PseudoBR %bb.1 + bb.1: + liveins: $x0 + %30:gpr = ADDI %20, 5 + PseudoBR %bb.3 + bb.2: + PseudoBR %bb.3 + bb.3: + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/branch-opt.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/branch-opt.mir new file mode 100644 index 0000000..76ade18 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/branch-opt.mir @@ -0,0 +1,376 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc %s -mtriple=riscv64 -run-pass=peephole-opt -o - | FileCheck %s + +# Make sure we shouldn't replace the %2 ADDI with the $x10 ADDI since it has a +# physical register destination. + +--- | + define void @foo(i32 signext %0) { + tail call void @bar(i32 1) + %2 = icmp ugt i32 %0, 1 + br i1 %2, label %3, label %4 + + 3: ; preds = %1 + tail call void @bar(i32 3) + ret void + + 4: ; preds = %1 + ret void + } + + define void @ule_negone(ptr %a, i32 signext %b, ptr %c, ptr %d) { + store i32 0, ptr %a + %p = icmp ule i32 %b, -1 + br i1 %p, label %block1, label %block2 + + block1: ; preds = %0 + store i32 %b, ptr %c + br label %end_block + + block2: ; preds = %0 + store i32 87, ptr %d + br label %end_block + + end_block: ; preds = %block2, %block1 + ret void + } + + define void @ult_zero(ptr %a, i32 signext %b, ptr %c, ptr %d) { + store i32 -1, ptr %a + %p = icmp ult i32 %b, 0 + br i1 %p, label %block1, label %block2 + + block1: ; preds = %0 + store i32 %b, ptr %c + br label %end_block + + block2: ; preds = %0 + store i32 87, ptr %d + br label %end_block + + end_block: ; preds = %block2, %block1 + ret void + } + + define void @sle_zero(ptr %a, i32 signext %b, ptr %c, ptr %d) { + store i32 1, ptr %a + %p = icmp sle i32 %b, 0 + br i1 %p, label %block1, label %block2 + + block1: ; preds = %0 + store i32 %b, ptr %c + br label %end_block + + block2: ; preds = %0 + store i32 87, ptr %d + br label %end_block + + end_block: ; preds = %block2, %block1 + ret void + } + + define void @slt_zero(ptr %a, i32 signext %b, ptr %c, ptr %d) { + store i32 -1, ptr %a + %p = icmp slt i32 %b, 0 + br i1 %p, label %block1, label %block2 + + block1: ; preds = %0 + store i32 %b, ptr %c + br label %end_block + + block2: ; preds = %0 + store i32 87, ptr %d + br label %end_block + + end_block: ; preds = %block2, %block1 + ret void + } + + declare void @bar(...) + +... +--- +name: foo +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: foo + ; CHECK: bb.0 (%ir-block.1): + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + ; CHECK-NEXT: $x10 = ADDI $x0, 1 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @bar, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 2 + ; CHECK-NEXT: BLTU [[COPY]], killed [[ADDI]], %bb.2 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1 (%ir-block.3): + ; CHECK-NEXT: $x10 = ADDI $x0, 3 + ; CHECK-NEXT: PseudoTAIL target-flags(riscv-call) @bar, implicit $x2, implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2 (%ir-block.4): + ; CHECK-NEXT: PseudoRET + bb.0 (%ir-block.1): + successors: %bb.1, %bb.2 + liveins: $x10 + + %0:gpr = COPY $x10 + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + $x10 = ADDI $x0, 1 + PseudoCALL target-flags(riscv-call) @bar, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + %2:gpr = ADDI $x0, 2 + BLTU %0, killed %2, %bb.2 + PseudoBR %bb.1 + + bb.1 (%ir-block.3): + $x10 = ADDI $x0, 3 + PseudoTAIL target-flags(riscv-call) @bar, implicit $x2, implicit $x10 + + bb.2 (%ir-block.4): + PseudoRET + +... +--- +name: ule_negone +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: ule_negone + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: SW killed [[ADDI]], [[COPY3]], 0 :: (store (s32)) + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, -1 + ; CHECK-NEXT: BLTU killed [[ADDI1]], [[COPY2]], %bb.2 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[COPY2]] + ; CHECK-NEXT: SW [[COPY4]], [[COPY1]], 0 :: (store (s32)) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 87 + ; CHECK-NEXT: SW killed [[ADDI2]], [[COPY]], 0 :: (store (s32)) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.1, %bb.2 + liveins: $x10, $x11, $x12, $x13 + + %3:gpr = COPY $x13 + %2:gpr = COPY $x12 + %1:gpr = COPY $x11 + %0:gpr = COPY $x10 + %5:gpr = ADDI $x0, 0 + SW killed %5, %0, 0 :: (store (s32)) + %6:gpr = ADDI $x0, -1 + BLTU killed %6, %1, %bb.2 + PseudoBR %bb.1 + + bb.1: + %4:gpr = COPY %1 + SW %4, %2, 0 :: (store (s32)) + PseudoBR %bb.3 + + bb.2: + %7:gpr = ADDI $x0, 87 + SW killed %7, %3, 0 :: (store (s32)) + + bb.3: + PseudoRET +... +--- +name: ult_zero +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: ult_zero + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 + ; CHECK-NEXT: SW killed [[ADDI]], [[COPY3]], 0 :: (store (s32)) + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: BLTU [[COPY2]], killed [[ADDI1]], %bb.2 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[COPY2]] + ; CHECK-NEXT: SW [[COPY4]], [[COPY1]], 0 :: (store (s32)) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 87 + ; CHECK-NEXT: SW killed [[ADDI2]], [[COPY]], 0 :: (store (s32)) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.1, %bb.2 + liveins: $x10, $x11, $x12, $x13 + + %3:gpr = COPY $x13 + %2:gpr = COPY $x12 + %1:gpr = COPY $x11 + %0:gpr = COPY $x10 + %5:gpr = ADDI $x0, -1 + SW killed %5, %0, 0 :: (store (s32)) + %6:gpr = ADDI $x0, 0 + BLTU %1, killed %6, %bb.2 + PseudoBR %bb.1 + + bb.1: + %4:gpr = COPY %1 + SW %4, %2, 0 :: (store (s32)) + PseudoBR %bb.3 + + bb.2: + %7:gpr = ADDI $x0, 87 + SW killed %7, %3, 0 :: (store (s32)) + + bb.3: + PseudoRET +... +--- +name: sle_zero +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: sle_zero + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; CHECK-NEXT: SW killed [[ADDI]], [[COPY3]], 0 :: (store (s32)) + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: BLT killed [[ADDI1]], [[COPY2]], %bb.2 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[COPY2]] + ; CHECK-NEXT: SW [[COPY4]], [[COPY1]], 0 :: (store (s32)) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 87 + ; CHECK-NEXT: SW killed [[ADDI2]], [[COPY]], 0 :: (store (s32)) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.1, %bb.2 + liveins: $x10, $x11, $x12, $x13 + + %3:gpr = COPY $x13 + %2:gpr = COPY $x12 + %1:gpr = COPY $x11 + %0:gpr = COPY $x10 + %5:gpr = ADDI $x0, 1 + SW killed %5, %0, 0 :: (store (s32)) + %6:gpr = ADDI $x0, 0 + BLT killed %6, %1, %bb.2 + PseudoBR %bb.1 + + bb.1: + %4:gpr = COPY %1 + SW %4, %2, 0 :: (store (s32)) + PseudoBR %bb.3 + + bb.2: + %7:gpr = ADDI $x0, 87 + SW killed %7, %3, 0 :: (store (s32)) + + bb.3: + PseudoRET +... +--- +name: slt_zero +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: slt_zero + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 + ; CHECK-NEXT: SW killed [[ADDI]], [[COPY3]], 0 :: (store (s32)) + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: BLT [[COPY2]], killed [[ADDI1]], %bb.2 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[COPY2]] + ; CHECK-NEXT: SW [[COPY4]], [[COPY1]], 0 :: (store (s32)) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 87 + ; CHECK-NEXT: SW killed [[ADDI2]], [[COPY]], 0 :: (store (s32)) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.1, %bb.2 + liveins: $x10, $x11, $x12, $x13 + + %3:gpr = COPY $x13 + %2:gpr = COPY $x12 + %1:gpr = COPY $x11 + %0:gpr = COPY $x10 + %5:gpr = ADDI $x0, -1 + SW killed %5, %0, 0 :: (store (s32)) + %6:gpr = ADDI $x0, 0 + BLT %1, killed %6, %bb.2 + PseudoBR %bb.1 + + bb.1: + %4:gpr = COPY %1 + SW %4, %2, 0 :: (store (s32)) + PseudoBR %bb.3 + + bb.2: + %7:gpr = ADDI $x0, 87 + SW killed %7, %3, 0 :: (store (s32)) + + bb.3: + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/branch-rel.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/branch-rel.mir new file mode 100644 index 0000000..c33c5ec --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/branch-rel.mir @@ -0,0 +1,39 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -mtriple=riscv64 -run-pass=branch-relaxation -o - -verify-machineinstrs | FileCheck %s + +--- | + define void @foo() { + ret void + } +... +--- +name: foo +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: foo + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: INLINEASM &".space 4096", sideeffect attdialect + ; CHECK-NEXT: BGE $x1, $x0, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: PseudoRET + bb.0: + liveins: $x1 + BNE $x1, $x0, %bb.3 + PseudoBR %bb.3 + bb.1: + liveins: $x1 + INLINEASM &".space 4096", sideeffect attdialect + BGE $x1, $x0, %bb.3 + bb.3: + PseudoRET +## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/cfi-multiple-locations.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/cfi-multiple-locations.mir new file mode 100644 index 0000000..43d8baf --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/cfi-multiple-locations.mir @@ -0,0 +1,36 @@ +# RUN: not --crash llc %s -mtriple=riscv64 \ +# RUN: -run-pass=cfi-instr-inserter \ +# RUN: -riscv-enable-cfi-instr-inserter=true \ +# RUN: -o /dev/null 2>&1 | FileCheck %s + +# CHECK: LLVM ERROR: Different saved locations for the same CSR + +# Technically, it is possible that a callee-saved register is saved in multiple different locations. +# CFIInstrInserter should handle this, but currently it does not. +--- +name: multiple_locations +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x9, $x2 + BEQ $x10, $x0, %bb.2 + + bb.1: + liveins: $x10, $x9, $x2 + $x5 = COPY $x9 + CFI_INSTRUCTION register $x9, $x5 + $x9 = COPY $x5 + CFI_INSTRUCTION register $x9, $x9 + PseudoBR %bb.3 + + bb.2: + liveins: $x10, $x9, $x2 + SD $x9, $x2, 0 :: (store (s64)) + CFI_INSTRUCTION offset $x9, 0 + $x9 = LD $x2, 0 :: (load (s64)) + CFI_INSTRUCTION register $x9, $x9 + PseudoBR %bb.3 + + bb.3: + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.mir new file mode 100644 index 0000000..d1c919f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.mir @@ -0,0 +1,48 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck -check-prefixes=CHECK32I %s +# RUN: llc -mtriple=riscv32 -mattr=+zcmp -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck -check-prefixes=CHECK32ZCMP %s +# RUN: llc -mtriple=riscv64 -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck -check-prefixes=CHECK64I %s +# RUN: llc -mtriple=riscv64 -mattr=+zcmp -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck -check-prefixes=CHECK64ZCMP %s +--- +name: zcmp_mv +tracksRegLiveness: true +body: | + bb.0: + liveins: $x11, $x10 + ; CHECK32I-LABEL: name: zcmp_mv + ; CHECK32I: liveins: $x11, $x10 + ; CHECK32I-NEXT: {{ $}} + ; CHECK32I-NEXT: $x8 = ADDI $x11, 0 + ; CHECK32I-NEXT: $x9 = ADDI $x10, 0 + ; CHECK32I-NEXT: $x10 = ADDI killed $x9, 0 + ; CHECK32I-NEXT: $x11 = ADDI $x8, 0 + ; CHECK32I-NEXT: PseudoRET + ; + ; CHECK32ZCMP-LABEL: name: zcmp_mv + ; CHECK32ZCMP: liveins: $x11, $x10 + ; CHECK32ZCMP-NEXT: {{ $}} + ; CHECK32ZCMP-NEXT: $x9, $x8 = CM_MVSA01 implicit $x10, implicit $x11 + ; CHECK32ZCMP-NEXT: CM_MVA01S killed $x9, $x8, implicit-def $x10, implicit-def $x11 + ; CHECK32ZCMP-NEXT: PseudoRET + ; + ; CHECK64I-LABEL: name: zcmp_mv + ; CHECK64I: liveins: $x11, $x10 + ; CHECK64I-NEXT: {{ $}} + ; CHECK64I-NEXT: $x8 = ADDI $x11, 0 + ; CHECK64I-NEXT: $x9 = ADDI $x10, 0 + ; CHECK64I-NEXT: $x10 = ADDI killed $x9, 0 + ; CHECK64I-NEXT: $x11 = ADDI $x8, 0 + ; CHECK64I-NEXT: PseudoRET + ; + ; CHECK64ZCMP-LABEL: name: zcmp_mv + ; CHECK64ZCMP: liveins: $x11, $x10 + ; CHECK64ZCMP-NEXT: {{ $}} + ; CHECK64ZCMP-NEXT: $x9, $x8 = CM_MVSA01 implicit $x10, implicit $x11 + ; CHECK64ZCMP-NEXT: CM_MVA01S killed $x9, $x8, implicit-def $x10, implicit-def $x11 + ; CHECK64ZCMP-NEXT: PseudoRET + $x8 = ADDI $x11, 0 + $x9 = ADDI $x10, 0 + $x10 = ADDI killed $x9, 0 + $x11 = ADDI $x8, 0 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/copy-frameindex.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/copy-frameindex.mir new file mode 100644 index 0000000..9a307d4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/copy-frameindex.mir @@ -0,0 +1,64 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -debugify-and-strip-all-safe -run-pass machine-sink %s -o - 2>&1 | FileCheck %s + +--- | + define void @sink_addi_fi(i32 %0) !dbg !5 { + bb.0: + %1 = alloca i32, align 4 + call void @llvm.dbg.value(metadata ptr %1, metadata !1, metadata !DIExpression()), !dbg !3 + %2 = icmp eq i32 %0, 0 + br i1 %2, label %bb.2, label %bb.1 + bb.1: + store volatile i32 0, ptr %1, align 4 + br label %bb.2 + bb.2: + ret void + } + + !llvm.dbg.cu = !{!0} + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !4) + !1 = !DILocalVariable(name: "var", scope: !5, file: !4, line: 2, type: !2) + !2 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned) + !3 = !DILocation(line: 0, scope: !5) + !4 = !DIFile(filename: "test.c", directory: "") + !5 = distinct !DISubprogram(name: "sink_addi_fi", scope: !4, file: !4, line: 1, type: !6, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !8) + !6 = !DISubroutineType(types: !7) + !7 = !{null, !2} + !8 = !{} + +... +--- +name: sink_addi_fi +liveins: + - { reg: '$x10', virtual-reg: '%0' } +stack: + - { id: 0, offset: 0, size: 4, alignment: 4 } +body: | + ; CHECK-LABEL: name: sink_addi_fi + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: BEQ killed [[COPY]], $x0, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0, 0 + ; CHECK-NEXT: SW $x0, killed [[ADDI]], 0 :: (volatile store (s32) into %stack.0) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: PseudoRET + bb.0: + liveins: $x10 + %0:gpr = COPY $x10 + DBG_VALUE %stack.0, $noreg, !1, !DIExpression(), debug-location !3 + %1:gpr = ADDI %stack.0, 0 + DBG_VALUE %1, $noreg, !1, !DIExpression(DW_OP_plus_uconst, 0, DW_OP_stack_value), debug-location !3 + BEQ killed %0:gpr, $x0, %bb.2 + bb.1: + SW $x0, killed %1:gpr, 0 :: (volatile store (s32) into %stack.0, align 4) + bb.2: + PseudoRET diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/fold-addi-loadstore-cpi.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/fold-addi-loadstore-cpi.mir new file mode 100644 index 0000000..42cac83 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/fold-addi-loadstore-cpi.mir @@ -0,0 +1,76 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mattr=+m -mtriple=riscv64 -run-pass riscv-merge-base-offset %s -o - | FileCheck %s + +--- | + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" + target triple = "riscv64" + + define i64 @udiv64_constant_add(i64 %a) nounwind { + %1 = udiv i64 %a, 7 + ret i64 %1 + } +... +--- +name: udiv64_constant_add +alignment: 4 +liveins: + - { reg: '$x10', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 0 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + isCalleeSavedInfoValid: false + localFrameSize: 0 +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: + - id: 0 + value: i64 2635249153387078803 + alignment: 8 + isTargetSpecific: false +body: | + bb.1 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: udiv64_constant_add + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) %const.0 + ; CHECK-NEXT: [[LD:%[0-9]+]]:gpr = LD [[LUI]], target-flags(riscv-lo) %const.0 :: (load (s64) from constant-pool) + ; CHECK-NEXT: [[MULHU:%[0-9]+]]:gpr = MULHU [[COPY]], [[LD]] + ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[MULHU]] + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[SUB]], 1 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[SRLI]], [[MULHU]] + ; CHECK-NEXT: [[SRLI1:%[0-9]+]]:gpr = SRLI [[ADD]], 2 + ; CHECK-NEXT: $x10 = COPY [[SRLI1]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gpr = COPY $x10 + %17:gpr = LUI target-flags(riscv-hi) %const.0 + %16:gpr = ADDI %17, target-flags(riscv-lo) %const.0 + %4:gpr = LD %16, 0 :: (load (s64) from constant-pool) + %8:gpr = MULHU %0, %4 + %9:gpr = SUB %0, %8 + %11:gpr = SRLI %9, 1 + %12:gpr = ADD %11, %8 + %13:gpr = SRLI %12, 2 + $x10 = COPY %13 + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/fold-mem-offset.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/fold-mem-offset.mir new file mode 100644 index 0000000..41afa26 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/fold-mem-offset.mir @@ -0,0 +1,43 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -mtriple=riscv32 -run-pass=riscv-fold-mem-offset -verify-machineinstrs -o - | FileCheck %s + +--- +name: crash +tracksRegLiveness: true +noPhis: false +isSSA: true +noVRegs: false +hasFakeUses: false +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: crash + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 3 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD killed [[SLLI]], [[COPY1]] + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 23 + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[LUI]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD]], [[LUI]] + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW killed [[ADD2]], 1792 + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW killed [[ADD1]], 1796 + ; CHECK-NEXT: $x10 = COPY [[LW]] + ; CHECK-NEXT: $x11 = COPY [[LW1]] + ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 + %1:gpr = COPY $x11 + %0:gpr = COPY $x10 + %3:gpr = SLLI %1, 3 + %4:gpr = ADD killed %3, %0 + %5:gpr = LUI 23 + %6:gpr = ADDI %5, 1792 + %7:gpr = ADD %4, killed %6 + %8:gpr = ADD %4, %5 + %9:gpr = LW killed %8, 1792 + %10:gpr = LW killed %7, 4 + $x10 = COPY %9 + $x11 = COPY %10 + PseudoRET implicit $x10, implicit $x11 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/instruction-count-remark.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/instruction-count-remark.mir new file mode 100644 index 0000000..f39a6ea --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/instruction-count-remark.mir @@ -0,0 +1,75 @@ +# RUN: llc -mtriple=riscv32 -verify-machineinstrs -start-before=riscv-asm-printer -simplify-mir -o /dev/null -pass-remarks-analysis=asm-printer %s 2>&1 | FileCheck %s +--- +name: instrs +tracksRegLiveness: true +body: | + bb.0: + $x0 = ADDI $x0, 0 + $x0 = ADDI $x0, 0 + $x0 = ADDI $x0, 0 + $x0 = LW $x0, 0 + $x0 = LW $x0, 0 + $x0 = XORI $x0, 0 + ; CHECK: addi : 3 + ; CHECK-NEXT: lw : 2 + ; CHECK-NEXT: xori : 1 + ; CHECK: 6 instructions in function +... +--- +name: bundles +tracksRegLiveness: true +body: | + bb.0: + $x0 = ADDI $x0, 0 + BUNDLE { + $x0 = ADDI $x0, 0 + $x0 = ADDI $x0, 0 + $x0 = LW $x0, 0 + } + $x0 = LW $x0, 0 + $x0 = XORI $x0, 0 + ; CHECK: addi : 3 + ; CHECK-NEXT: lw : 2 + ; CHECK-NEXT: xori : 1 + ; CHECK: 6 instructions in function +... +--- +name: metainstrs +tracksRegLiveness: true +body: | + bb.0: + $x0 = ADDI $x0, 0 + $x0 = ADDI $x0, 0 + $x0 = ADDI $x0, 0 + $x0 = IMPLICIT_DEF + $x0 = LW $x0, 0 + $x0 = LW $x0, 0 + CFI_INSTRUCTION adjust_cfa_offset 4 + $x0 = XORI $x0, 0 + DBG_VALUE $x0, 0 + ; CHECK: addi : 3 + ; CHECK-NEXT: lw : 2 + ; CHECK-NEXT: xori : 1 + ; CHECK: 6 instructions in function +... +--- +name: metabundles +tracksRegLiveness: true +body: | + bb.0: + $x0 = ADDI $x0, 0 + BUNDLE { + CFI_INSTRUCTION adjust_cfa_offset 4 + $x0 = ADDI $x0, 0 + $x0 = ADDI $x0, 0 + DBG_VALUE $x0, 0 + $x0 = LW $x0, 0 + } + $x0 = LW $x0, 0 + $x0 = IMPLICIT_DEF + $x0 = XORI $x0, 0 + ; CHECK: addi : 3 + ; CHECK-NEXT: lw : 2 + ; CHECK-NEXT: xori : 1 + ; CHECK: 6 instructions in function +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/live-sp.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/live-sp.mir new file mode 100644 index 0000000..b8d6962 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/live-sp.mir @@ -0,0 +1,91 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=prologepilog -simplify-mir -o - %s | FileCheck %s +# verify live-on-entry registers are not marked killed by spills +--- | + + declare void @vararg(i32 signext, ...) + + define void @test1() { + entry: + %a = alloca i32, align 4 + %0 = call ptr @llvm.returnaddress(i32 0) + %1 = ptrtoint ptr %0 to i64 + %conv = trunc i64 %1 to i32 + store i32 %conv, ptr %a, align 4 + %2 = load i32, ptr %a, align 4 + call void (i32, ...) @vararg(i32 signext 0, i32 signext %2) + ret void + } + +... +--- +name: test1 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +registers: [] +liveins: + - { reg: '$x1', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: true + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + stackProtector: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: [] + restorePoint: [] +fixedStack: [] +stack: + - { id: 0, name: a, type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x1 + + ; CHECK-LABEL: name: test1 + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: frame-setup SD $x1, $x2, 8 :: (store (s64) into %stack.1) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-NEXT: SW renamable $x1, $x2, 4 :: (store (s32) into %ir.a) + ; CHECK-NEXT: renamable $x11 = ADDIW killed renamable $x1, 0 + ; CHECK-NEXT: $x10 = COPY $x0 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @vararg, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit $x11, implicit-def $x2 + ; CHECK-NEXT: $x1 = frame-destroy LD $x2, 8 :: (load (s64) from %stack.1) + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NEXT: PseudoRET + SW renamable $x1, %stack.0.a, 0 :: (store (s32) into %ir.a) + renamable $x11 = ADDIW killed renamable $x1, 0 + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + $x10 = COPY $x0 + PseudoCALL target-flags(riscv-call) @vararg, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit $x11, implicit-def $x2 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machine-combiner.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-combiner.mir new file mode 100644 index 0000000..e110dd9 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-combiner.mir @@ -0,0 +1,87 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+f -run-pass=machine-combiner \ +# RUN: -verify-machineinstrs | FileCheck %s + +--- | + source_filename = "test.ll" + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" + target triple = "riscv64" + + define void @foo(ptr %0, ptr %1, float %2, float %3, ptr %4, ptr %5) #0 { + %7 = load float, ptr %0, align 4 + %8 = load float, ptr %1, align 4 + %9 = fmul fast float %8, %7 + %10 = fadd fast float %9, %2 + store float %10, ptr %4, align 4 + %11 = fsub fast float %3, %9 + store float %11, ptr %5, align 4 + ret void + } + + attributes #0 = { "target-features"="+f" } + +... +--- +name: foo +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: fpr32 } + - { id: 3, class: fpr32 } + - { id: 4, class: gpr } + - { id: 5, class: gpr } + - { id: 6, class: fpr32 } + - { id: 7, class: fpr32 } + - { id: 8, class: fpr32 } + - { id: 9, class: fpr32 } + - { id: 10, class: fpr32 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } + - { reg: '$f10_f', virtual-reg: '%2' } + - { reg: '$f11_f', virtual-reg: '%3' } + - { reg: '$x12', virtual-reg: '%4' } + - { reg: '$x13', virtual-reg: '%5' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0 (%ir-block.6): + liveins: $x10, $x11, $f10_f, $f11_f, $x12, $x13 + + ; CHECK-LABEL: name: foo + ; CHECK: liveins: $x10, $x11, $f10_f, $f11_f, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[FLW:%[0-9]+]]:fpr32 = FLW [[COPY5]], 0 :: (load (s32) from %ir.0) + ; CHECK-NEXT: [[FLW1:%[0-9]+]]:fpr32 = FLW [[COPY4]], 0 :: (load (s32) from %ir.1) + ; CHECK-NEXT: [[FMADD_S:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FMADD_S [[FLW1]], [[FLW]], [[COPY3]], 7, implicit $frm + ; CHECK-NEXT: FSW killed [[FMADD_S]], [[COPY1]], 0 :: (store (s32) into %ir.4) + ; CHECK-NEXT: [[FNMSUB_S:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FNMSUB_S [[FLW1]], [[FLW]], [[COPY2]], 7, implicit $frm + ; CHECK-NEXT: FSW killed [[FNMSUB_S]], [[COPY]], 0 :: (store (s32) into %ir.5) + ; CHECK-NEXT: PseudoRET + %5:gpr = COPY $x13 + %4:gpr = COPY $x12 + %3:fpr32 = COPY $f11_f + %2:fpr32 = COPY $f10_f + %1:gpr = COPY $x11 + %0:gpr = COPY $x10 + %6:fpr32 = FLW %0, 0 :: (load (s32) from %ir.0) + %7:fpr32 = FLW %1, 0 :: (load (s32) from %ir.1) + %8:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FMUL_S killed %7, killed %6, 7, implicit $frm + %9:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADD_S %8, %2, 7, implicit $frm + FSW killed %9, %4, 0 :: (store (s32) into %ir.4) + %10:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FSUB_S %3, %8, 7, implicit $frm + FSW killed %10, %5, 0 :: (store (s32) into %ir.5) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machine-copyprop-noop-removal.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-copyprop-noop-removal.mir new file mode 100644 index 0000000..293b15b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-copyprop-noop-removal.mir @@ -0,0 +1,78 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -o - %s -mtriple=riscv64 -run-pass=machine-cp -mcp-use-is-copy-instr | FileCheck %s + +## This test was added to capture a case where MachineCopyPropagation may +## leave a no-op register move (add reg, x0, reg). +## Due to the bug reported in +## , we are not currently +## able to optimize this case. + +--- +name: ham +body: | + ; CHECK-LABEL: name: ham + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = ANDI killed renamable $x10, 1 + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 1 + ; CHECK-NEXT: BEQ killed renamable $x11, $x0, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ADDI $x0, 0 + ; CHECK-NEXT: renamable $x10 = ADDI killed renamable $x10, 0 + ; CHECK-NEXT: BEQ renamable $x10, $x0, %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1 + ; CHECK-NEXT: renamable $x10 = ADD killed renamable $x11, killed renamable $x10 + ; CHECK-NEXT: BNE renamable $x10, $x0, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: $x10 + + renamable $x11 = ANDI killed renamable $x10, 1 + renamable $x10 = ADDI $x0, 1 + BEQ killed renamable $x11, $x0, %bb.2 + + bb.1: + successors: %bb.4(0x40000000), %bb.5(0x40000000) + liveins: $x10 + + $x11 = ADDI $x0, 0 + renamable $x10 = ADD killed renamable $x11, killed renamable $x10 + BEQ renamable $x10, $x0, %bb.4 + + bb.5: + $x10 = ADDI $x0, 0 + PseudoRET implicit $x10 + + bb.2: + successors: %bb.4(0x40000000), %bb.5(0x40000000) + liveins: $x10 + + renamable $x11 = ADDI $x0, 1 + renamable $x10 = ADD killed renamable $x11, killed renamable $x10 + BNE renamable $x10, $x0, %bb.5 + + bb.4: + liveins: $x10 + + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir new file mode 100644 index 0000000..31c1649 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir @@ -0,0 +1,828 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -o - %s -mtriple=riscv64 -run-pass=machine-cp -mcp-use-is-copy-instr | FileCheck %s + +# Check that instruction simplifications expected to be performed after +# machine copy propagation are done. + +--- +name: add1 +body: | + bb.0: + ; CHECK-LABEL: name: add1 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = ADD renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: add2 +body: | + bb.0: + ; CHECK-LABEL: name: add2 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = ADD $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: or1 +body: | + bb.0: + ; CHECK-LABEL: name: or1 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = OR renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: or2 +body: | + bb.0: + ; CHECK-LABEL: name: or2 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = OR $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: xor1 +body: | + bb.0: + ; CHECK-LABEL: name: xor1 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = XOR renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: xor2 +body: | + bb.0: + ; CHECK-LABEL: name: xor2 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = XOR $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +--- +name: xor3 +body: | + bb.0: + ; CHECK-LABEL: name: xor3 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = XOR renamable $x11, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: addw1 +body: | + bb.0: + ; CHECK-LABEL: name: addw1 + ; CHECK: renamable $x10 = ADDIW $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = ADDW renamable $x11, $x12 + PseudoRET implicit $x10 +... +--- +name: addw2 +body: | + bb.0: + ; CHECK-LABEL: name: addw2 + ; CHECK: renamable $x10 = ADDIW $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = ADDW $x12, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sub +body: | + bb.0: + ; CHECK-LABEL: name: sub + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SUB renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: subw +body: | + bb.0: + ; CHECK-LABEL: name: subw + ; CHECK: renamable $x10 = ADDIW $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SUBW renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: sh1add1 +body: | + bb.0: + ; CHECK-LABEL: name: sh1add1 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SH1ADD $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sh1add2 +body: | + bb.0: + ; CHECK-LABEL: name: sh1add2 + ; CHECK: renamable $x10 = SLLI $x12, 1 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SH1ADD renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: sh1add.uw1 +body: | + bb.0: + ; CHECK-LABEL: name: sh1add.uw1 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SH1ADD_UW $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sh1add.uw2 +body: | + bb.0: + ; CHECK-LABEL: name: sh1add.uw2 + ; CHECK: renamable $x10 = SLLI_UW $x12, 1 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SH1ADD_UW renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: sh2add1 +body: | + bb.0: + ; CHECK-LABEL: name: sh2add1 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SH2ADD $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sh2add2 +body: | + bb.0: + ; CHECK-LABEL: name: sh2add2 + ; CHECK: renamable $x10 = SLLI $x12, 2 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SH2ADD renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: sh2add.uw1 +body: | + bb.0: + ; CHECK-LABEL: name: sh2add.uw1 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SH2ADD_UW $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sh2add.uw2 +body: | + bb.0: + ; CHECK-LABEL: name: sh2add.uw2 + ; CHECK: renamable $x10 = SLLI_UW $x12, 2 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SH2ADD_UW renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: sh3add1 +body: | + bb.0: + ; CHECK-LABEL: name: sh3add1 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SH3ADD $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sh3add2 +body: | + bb.0: + ; CHECK-LABEL: name: sh3add2 + ; CHECK: renamable $x10 = SLLI $x12, 3 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SH3ADD renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: sh3add.uw1 +body: | + bb.0: + ; CHECK-LABEL: name: sh3add.uw1 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SH3ADD_UW $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sh3add.uw2 +body: | + bb.0: + ; CHECK-LABEL: name: sh3add.uw2 + ; CHECK: renamable $x10 = SLLI_UW $x12, 3 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SH3ADD_UW renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: andi +body: | + bb.0: + ; CHECK-LABEL: name: andi + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = ANDI renamable $x11, 13 + PseudoRET implicit $x10 +... +--- +name: and1 +body: | + bb.0: + ; CHECK-LABEL: name: and1 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = AND renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: and2 +body: | + bb.0: + ; CHECK-LABEL: name: and2 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = AND $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: mul1 +body: | + bb.0: + ; CHECK-LABEL: name: mul1 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MUL renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: mul2 +body: | + bb.0: + ; CHECK-LABEL: name: mul2 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MUL $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: mulh1 +body: | + bb.0: + ; CHECK-LABEL: name: mulh1 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MULH renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: mulh2 +body: | + bb.0: + ; CHECK-LABEL: name: mulh2 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MULH $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: mulhsu1 +body: | + bb.0: + ; CHECK-LABEL: name: mulhsu1 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MULHSU renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: mulhsu2 +body: | + bb.0: + ; CHECK-LABEL: name: mulhsu2 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MULHSU $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: mulhu1 +body: | + bb.0: + ; CHECK-LABEL: name: mulhu1 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MULHU renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: mulhu2 +body: | + bb.0: + ; CHECK-LABEL: name: mulhu2 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MULHU $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: mulw1 +body: | + bb.0: + ; CHECK-LABEL: name: mulw1 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MULW renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: mulw2 +body: | + bb.0: + ; CHECK-LABEL: name: mulw2 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MULW $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: slli +body: | + bb.0: + ; CHECK-LABEL: name: slli + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = SLLI renamable $x11, 13 + PseudoRET implicit $x10 +... +--- +name: srli +body: | + bb.0: + ; CHECK-LABEL: name: srli + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = SRLI renamable $x11, 13 + PseudoRET implicit $x10 +... +--- +name: srai +body: | + bb.0: + ; CHECK-LABEL: name: srai + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = SRAI renamable $x11, 13 + PseudoRET implicit $x10 +... +--- +name: slliw +body: | + bb.0: + ; CHECK-LABEL: name: slliw + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = SLLIW renamable $x11, 13 + PseudoRET implicit $x10 +... +--- +name: srliw +body: | + bb.0: + ; CHECK-LABEL: name: srliw + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = SRLIW renamable $x11, 13 + PseudoRET implicit $x10 +... +--- +name: sraiw +body: | + bb.0: + ; CHECK-LABEL: name: sraiw + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = SRAIW renamable $x11, 13 + PseudoRET implicit $x10 +... +--- +name: slli_uw +body: | + bb.0: + ; CHECK-LABEL: name: slli_uw + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = SLLI_UW renamable $x11, 13 + PseudoRET implicit $x10 +... +--- +name: ori +body: | + bb.0: + ; CHECK-LABEL: name: ori + ; CHECK: renamable $x10 = ADDI $x0, 13 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = ORI renamable $x11, 13 + PseudoRET implicit $x10 +... +--- +name: xori +body: | + bb.0: + ; CHECK-LABEL: name: xori + ; CHECK: renamable $x10 = ADDI $x0, 13 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = XORI renamable $x11, 13 + PseudoRET implicit $x10 +... +--- +name: sltiu1 +body: | + bb.0: + ; CHECK-LABEL: name: sltiu1 + ; CHECK: renamable $x10 = ADDI $x0, 1 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = SLTIU renamable $x11, 2 + PseudoRET implicit $x10 +... +--- +name: sltiu2 +body: | + bb.0: + ; CHECK-LABEL: name: sltiu2 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = SLTIU renamable $x11, 0 + PseudoRET implicit $x10 +... +--- +name: sltu +body: | + bb.0: + ; CHECK-LABEL: name: sltu + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = SLTU renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: add.uw1 +body: | + bb.0: + ; CHECK-LABEL: name: add.uw1 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = ADD_UW renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: add.uw2 +body: | + bb.0: + ; CHECK-LABEL: name: add.uw2 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = ADD_UW $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sext.h +body: | + bb.0: + ; CHECK-LABEL: name: sext.h + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = SEXT_H renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sext.b +body: | + bb.0: + ; CHECK-LABEL: name: sext.b + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = SEXT_B renamable $x11 + PseudoRET implicit $x10 +... +--- +name: zext.h.rv32 +body: | + bb.0: + ; CHECK-LABEL: name: zext.h.rv32 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = ZEXT_H_RV32 renamable $x11 + PseudoRET implicit $x10 +... +--- +name: zext.h.rv64 +body: | + bb.0: + ; CHECK-LABEL: name: zext.h.rv64 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x0 + renamable $x10 = ZEXT_H_RV64 renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sll1 +body: | + bb.0: + ; CHECK-LABEL: name: sll1 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SLL $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sll2 +body: | + bb.0: + ; CHECK-LABEL: name: sll2 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SLL renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: sr11 +body: | + bb.0: + ; CHECK-LABEL: name: sr11 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SRL $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sr12 +body: | + bb.0: + ; CHECK-LABEL: name: sr12 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SRL renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: sra1 +body: | + bb.0: + ; CHECK-LABEL: name: sra1 + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SRA $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sra2 +body: | + bb.0: + ; CHECK-LABEL: name: sra2 + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SRA renamable $x11, $x0 + PseudoRET implicit $x10 +... +--- +name: sllw +body: | + bb.0: + ; CHECK-LABEL: name: sllw + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SLLW $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: srlw +body: | + bb.0: + ; CHECK-LABEL: name: srlw + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SRLW $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: sraw +body: | + bb.0: + ; CHECK-LABEL: name: sraw + ; CHECK: renamable $x10 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = SRAW $x0, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: min +body: | + bb.0: + ; CHECK-LABEL: name: min + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MIN renamable $x11, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: minu +body: | + bb.0: + ; CHECK-LABEL: name: minu + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MINU renamable $x11, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: max +body: | + bb.0: + ; CHECK-LABEL: name: max + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MAX renamable $x11, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: maxu +body: | + bb.0: + ; CHECK-LABEL: name: maxu + ; CHECK: renamable $x10 = ADDI $x12, 0 + ; CHECK-NEXT: PseudoRET implicit $x10 + renamable $x11 = COPY $x12 + renamable $x10 = MAXU renamable $x11, renamable $x11 + PseudoRET implicit $x10 +... +--- +name: multipass +body: | + bb.0: + ; CHECK-LABEL: name: multipass + ; CHECK: renamable $x9 = ADDI $x0, 0 + ; CHECK-NEXT: PseudoRET implicit $x9 + renamable $x11 = COPY $x0 + renamable $x10 = SLLI renamable $x11, 13 + renamable $x9 = SRLI renamable $x10, 13 + PseudoRET implicit $x9 +... +--- +name: beq +body: | + ; CHECK-LABEL: name: beq + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = COPY $x12 + ; CHECK-NEXT: BEQ $x12, $x0, %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: PseudoRET + bb.0: + renamable $x11 = COPY $x12 + BEQ $x0, renamable $x11, %bb.1 + bb.1: + PseudoRET +... +--- +name: bne +body: | + ; CHECK-LABEL: name: bne + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = COPY $x12 + ; CHECK-NEXT: BNE $x12, $x0, %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: PseudoRET + bb.0: + renamable $x11 = COPY $x12 + BNE $x0, renamable $x11, %bb.1 + bb.1: + PseudoRET +... +--- +name: bltu +body: | + ; CHECK-LABEL: name: bltu + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = COPY $x12 + ; CHECK-NEXT: BNE $x12, $x0, %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: PseudoRET + bb.0: + renamable $x11 = COPY $x12 + BLTU $x0, renamable $x11, %bb.1 + bb.1: + PseudoRET +... +--- +name: bgeu +body: | + ; CHECK-LABEL: name: bgeu + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = COPY $x12 + ; CHECK-NEXT: BEQ $x12, $x0, %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: PseudoRET + bb.0: + renamable $x11 = COPY $x12 + BGEU $x0, renamable $x11, %bb.1 + bb.1: + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machine-cp.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-cp.mir new file mode 100644 index 0000000..f3674f8 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-cp.mir @@ -0,0 +1,34 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -o - %s -mtriple=riscv32 -simplify-mir \ +# RUN: -run-pass=machine-cp | FileCheck --check-prefix=RV32 %s +# RUN: llc -o - %s -mtriple=riscv64 -simplify-mir \ +# RUN: -run-pass=machine-cp | FileCheck --check-prefix=RV64 %s + +--- | + define void @foo() { + entry: + ret void + } +... +--- +name: foo +body: | + bb.0.entry: + liveins: $v28_v29_v30, $v8_v9, $v1 + ; RV32-LABEL: name: foo + ; RV32: liveins: $v28_v29_v30, $v8_v9, $v1 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: renamable $v4_v5_v6_v7_v8_v9_v10_v11 = COPY killed renamable $v0_v1_v2_v3_v4_v5_v6_v7 + ; RV32-NEXT: renamable $v28 = COPY renamable $v8, implicit killed $v28_v29_v30, implicit-def $v28_v29_v30 + ; RV32-NEXT: PseudoRET implicit $v28 + ; RV64-LABEL: name: foo + ; RV64: liveins: $v28_v29_v30, $v8_v9, $v1 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: renamable $v4_v5_v6_v7_v8_v9_v10_v11 = COPY killed renamable $v0_v1_v2_v3_v4_v5_v6_v7 + ; RV64-NEXT: renamable $v28 = COPY renamable $v8, implicit killed $v28_v29_v30, implicit-def $v28_v29_v30 + ; RV64-NEXT: PseudoRET implicit $v28 + renamable $v8 = COPY renamable $v1, implicit killed $v8_v9, implicit-def $v8_v9 + renamable $v4_v5_v6_v7_v8_v9_v10_v11 = COPY killed renamable $v0_v1_v2_v3_v4_v5_v6_v7 + renamable $v28 = COPY renamable $v8, implicit killed $v28_v29_v30, implicit-def $v28_v29_v30 + PseudoRET implicit $v28 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-call-reg-live-across.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-call-reg-live-across.mir new file mode 100644 index 0000000..3a7f2ed --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-call-reg-live-across.mir @@ -0,0 +1,354 @@ +# RUN: llc -mtriple=riscv32 -enable-machine-outliner -start-before=machine-outliner \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s +--- | + define i8 @test1(ptr %var1, ptr %0, ptr %var12, ptr %var2, ptr %var3, ptr %var11, ptr %var6, ptr %var7, ptr %var8, ptr %var9, ptr %1, ptr %var10, ptr %2) #0 { + ; CHECK-LABEL: test1: + ; CHECK: # %bb.0: # %entry + ; CHECK-NEXT: addi sp, sp, -32 + ; CHECK-NEXT: sw ra, 28(sp) # 4-byte Folded Spill + ; CHECK-NEXT: sw s0, 24(sp) # 4-byte Folded Spill + ; CHECK-NEXT: sw s1, 20(sp) # 4-byte Folded Spill + ; CHECK-NEXT: sw s2, 16(sp) # 4-byte Folded Spill + ; CHECK-NEXT: sw s3, 12(sp) # 4-byte Folded Spill + ; CHECK-NEXT: mv s0, a7 + ; CHECK-NEXT: mv t0, a6 + ; CHECK-NEXT: mv t1, a5 + ; CHECK-NEXT: mv s1, a4 + ; CHECK-NEXT: mv a1, a3 + ; CHECK-NEXT: lw s2, 48(sp) + ; CHECK-NEXT: lw s3, 40(sp) + ; CHECK-NEXT: lw a5, 32(sp) + ; CHECK-NEXT: li a6, 1 + ; CHECK-NEXT: li a7, 1 + ; CHECK-NEXT: li t3, 0 + ; CHECK-NEXT: mv a2, a0 + ; CHECK-NEXT: mv a3, t1 + ; CHECK-NEXT: tail OUTLINED_FUNCTION_0 + entry: + %var4 = alloca ptr, align 4 + %var5 = alloca ptr, align 4 + %call = call fastcc i8 null(ptr %var1, ptr %var2, ptr %var1, ptr %var11, ptr %var6, ptr %var8, i32 1, i8 1) + store ptr %1, ptr %var3, align 4 + store ptr %2, ptr %var7, align 4 + ret i8 1 + } + + define i8 @test2(ptr %var1, ptr %0, ptr %var12, ptr %var2, ptr %var3, ptr %var11, ptr %var6, ptr %var7, ptr %var8, ptr %var9, ptr %1, ptr %var10, ptr %2) #0 { + ; CHECK-LABEL: test2: + ; CHECK: # %bb.0: # %entry + ; CHECK-NEXT: addi sp, sp, -32 + ; CHECK-NEXT: sw ra, 28(sp) # 4-byte Folded Spill + ; CHECK-NEXT: sw s0, 24(sp) # 4-byte Folded Spill + ; CHECK-NEXT: sw s1, 20(sp) # 4-byte Folded Spill + ; CHECK-NEXT: sw s2, 16(sp) # 4-byte Folded Spill + ; CHECK-NEXT: sw s3, 12(sp) # 4-byte Folded Spill + ; CHECK-NEXT: mv s0, a7 + ; CHECK-NEXT: mv t0, a6 + ; CHECK-NEXT: mv t1, a5 + ; CHECK-NEXT: mv s1, a4 + ; CHECK-NEXT: mv a2, a3 + ; CHECK-NEXT: lw s2, 48(sp) + ; CHECK-NEXT: lw s3, 40(sp) + ; CHECK-NEXT: lw a5, 32(sp) + ; CHECK-NEXT: li a6, 1 + ; CHECK-NEXT: li a7, 1 + ; CHECK-NEXT: li t3, 0 + ; CHECK-NEXT: mv a1, a0 + ; CHECK-NEXT: mv a3, t1 + ; CHECK-NEXT: tail OUTLINED_FUNCTION_0 + entry: + %var4 = alloca ptr, align 4 + %var5 = alloca ptr, align 4 + %call = call fastcc i8 null(ptr %var1, ptr %var1, ptr %var2, ptr %var11, ptr %var6, ptr %var8, i32 1, i8 1) + store ptr %1, ptr %var3, align 4 + store ptr %2, ptr %var7, align 4 + ret i8 1 + } + + ; NOTE: the utils/update_llc_test_checks.py script does not produce checks for the outlined function + ; so this is manually specified. + ; CHECK-LABEL: OUTLINED_FUNCTION_0: + ; CHECK: # %bb.0: + ; CHECK-NEXT: mv a4, t0 + ; CHECK-NEXT: jalr t3 + ; CHECK-NEXT: sw s3, 0(s1) + ; CHECK-NEXT: li a0, 1 + ; CHECK-NEXT: sw s2, 0(s0) + ; CHECK-NEXT: lw ra, 28(sp) + ; CHECK-NEXT: lw s0, 24(sp) + ; CHECK-NEXT: lw s1, 20(sp) + ; CHECK-NEXT: lw s2, 16(sp) + ; CHECK-NEXT: lw s3, 12(sp) + ; CHECK-NEXT: addi sp, sp, 32 + ; CHECK-NEXT: ret + + attributes #0 = { minsize nounwind } +... +--- +name: test1 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +noPhis: true +isSSA: false +noVRegs: true +hasFakeUses: false +callsEHReturn: false +callsUnwindInit: false +hasEHContTarget: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: true +registers: [] +liveins: + - { reg: '$x10', virtual-reg: '' } + - { reg: '$x13', virtual-reg: '' } + - { reg: '$x14', virtual-reg: '' } + - { reg: '$x15', virtual-reg: '' } + - { reg: '$x16', virtual-reg: '' } + - { reg: '$x17', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 32 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 0 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + isCalleeSavedInfoValid: true + localFrameSize: 8 +fixedStack: + - { id: 0, type: default, offset: 16, size: 4, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, type: default, offset: 12, size: 4, alignment: 4, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, type: default, offset: 8, size: 4, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, type: default, offset: 4, size: 4, alignment: 4, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, type: default, offset: 0, size: 4, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +stack: + - { id: 0, name: var4, type: default, offset: -24, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + local-offset: -4, debug-info-variable: '', debug-info-expression: '', + debug-info-location: '' } + - { id: 1, name: var5, type: default, offset: -28, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + local-offset: -8, debug-info-variable: '', debug-info-expression: '', + debug-info-location: '' } + - { id: 2, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$x1', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$x8', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$x9', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$x18', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 6, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$x19', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + liveins: $x10, $x13, $x14, $x15, $x16, $x17, $x1, $x8, $x9, $x18, $x19 + + $x2 = frame-setup ADDI $x2, -32 + frame-setup SW killed $x1, $x2, 28 :: (store (s32) into %stack.2) + frame-setup SW killed $x8, $x2, 24 :: (store (s32) into %stack.3) + frame-setup SW killed $x9, $x2, 20 :: (store (s32) into %stack.4) + frame-setup SW killed $x18, $x2, 16 :: (store (s32) into %stack.5) + frame-setup SW killed $x19, $x2, 12 :: (store (s32) into %stack.6) + $x8 = ADDI $x17, 0 + $x5 = ADDI $x16, 0 + $x6 = ADDI $x15, 0 + $x9 = ADDI $x14, 0 + $x11 = ADDI $x13, 0 + renamable $x18 = LW $x2, 48 :: (load (s32) from %fixed-stack.0, align 16) + renamable $x19 = LW $x2, 40 :: (load (s32) from %fixed-stack.2, align 8) + renamable $x15 = LW $x2, 32 :: (load (s32) from %fixed-stack.4, align 16) + $x16 = ADDI $x0, 1 + $x17 = ADDI $x0, 1 + $x28 = ADDI $x0, 0 + $x12 = ADDI renamable $x10, 0 + $x13 = ADDI killed renamable $x6, 0 + $x14 = ADDI killed renamable $x5, 0 + PseudoCALLIndirect killed renamable $x28, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x2, implicit-def dead $x10 + SW killed renamable $x19, killed renamable $x9, 0 :: (store (s32) into %ir.var3) + $x10 = ADDI $x0, 1 + SW killed renamable $x18, killed renamable $x8, 0 :: (store (s32) into %ir.var7) + $x1 = frame-destroy LW $x2, 28 :: (load (s32) from %stack.2) + $x8 = frame-destroy LW $x2, 24 :: (load (s32) from %stack.3) + $x9 = frame-destroy LW $x2, 20 :: (load (s32) from %stack.4) + $x18 = frame-destroy LW $x2, 16 :: (load (s32) from %stack.5) + $x19 = frame-destroy LW $x2, 12 :: (load (s32) from %stack.6) + $x2 = frame-destroy ADDI $x2, 32 + PseudoRET implicit $x10 +... +--- +name: test2 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +noPhis: true +isSSA: false +noVRegs: true +hasFakeUses: false +callsEHReturn: false +callsUnwindInit: false +hasEHContTarget: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: true +registers: [] +liveins: + - { reg: '$x10', virtual-reg: '' } + - { reg: '$x13', virtual-reg: '' } + - { reg: '$x14', virtual-reg: '' } + - { reg: '$x15', virtual-reg: '' } + - { reg: '$x16', virtual-reg: '' } + - { reg: '$x17', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 32 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 0 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + isCalleeSavedInfoValid: true + localFrameSize: 8 +fixedStack: + - { id: 0, type: default, offset: 16, size: 4, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, type: default, offset: 12, size: 4, alignment: 4, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, type: default, offset: 8, size: 4, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, type: default, offset: 4, size: 4, alignment: 4, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, type: default, offset: 0, size: 4, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +stack: + - { id: 0, name: var4, type: default, offset: -24, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + local-offset: -4, debug-info-variable: '', debug-info-expression: '', + debug-info-location: '' } + - { id: 1, name: var5, type: default, offset: -28, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + local-offset: -8, debug-info-variable: '', debug-info-expression: '', + debug-info-location: '' } + - { id: 2, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$x1', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$x8', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$x9', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$x18', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 6, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$x19', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + liveins: $x10, $x13, $x14, $x15, $x16, $x17, $x1, $x8, $x9, $x18, $x19 + + $x2 = frame-setup ADDI $x2, -32 + frame-setup SW killed $x1, $x2, 28 :: (store (s32) into %stack.2) + frame-setup SW killed $x8, $x2, 24 :: (store (s32) into %stack.3) + frame-setup SW killed $x9, $x2, 20 :: (store (s32) into %stack.4) + frame-setup SW killed $x18, $x2, 16 :: (store (s32) into %stack.5) + frame-setup SW killed $x19, $x2, 12 :: (store (s32) into %stack.6) + $x8 = ADDI $x17, 0 + $x5 = ADDI $x16, 0 + $x6 = ADDI $x15, 0 + $x9 = ADDI $x14, 0 + $x12 = ADDI $x13, 0 + renamable $x18 = LW $x2, 48 :: (load (s32) from %fixed-stack.0, align 16) + renamable $x19 = LW $x2, 40 :: (load (s32) from %fixed-stack.2, align 8) + renamable $x15 = LW $x2, 32 :: (load (s32) from %fixed-stack.4, align 16) + $x16 = ADDI $x0, 1 + $x17 = ADDI $x0, 1 + $x28 = ADDI $x0, 0 + $x11 = ADDI renamable $x10, 0 + $x13 = ADDI killed renamable $x6, 0 + $x14 = ADDI killed renamable $x5, 0 + PseudoCALLIndirect killed renamable $x28, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x2, implicit-def dead $x10 + SW killed renamable $x19, killed renamable $x9, 0 :: (store (s32) into %ir.var3) + $x10 = ADDI $x0, 1 + SW killed renamable $x18, killed renamable $x8, 0 :: (store (s32) into %ir.var7) + $x1 = frame-destroy LW $x2, 28 :: (load (s32) from %stack.2) + $x8 = frame-destroy LW $x2, 24 :: (load (s32) from %stack.3) + $x9 = frame-destroy LW $x2, 20 :: (load (s32) from %stack.4) + $x18 = frame-destroy LW $x2, 16 :: (load (s32) from %stack.5) + $x19 = frame-destroy LW $x2, 12 :: (load (s32) from %stack.6) + $x2 = frame-destroy ADDI $x2, 32 + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-call-x5-liveout.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-call-x5-liveout.mir new file mode 100644 index 0000000..4858a9b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-call-x5-liveout.mir @@ -0,0 +1,136 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefixes=RV32I-MO %s +# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefixes=RV64I-MO %s + +# MIR has been edited by hand to have x5 as live out in @dont_outline + +--- + +name: outline_0 +tracksRegLiveness: true +isOutlined: false +body: | + bb.0: + liveins: $x10, $x11 + + ; RV32I-MO-LABEL: name: outline_0 + ; RV32I-MO: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; RV32I-MO-NEXT: PseudoRET implicit $x11 + ; + ; RV64I-MO-LABEL: name: outline_0 + ; RV64I-MO: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; RV64I-MO-NEXT: PseudoRET implicit $x11 + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET implicit $x11 + +... +--- + +name: dont_outline +tracksRegLiveness: true +isOutlined: false +body: | + ; RV32I-MO-LABEL: name: dont_outline + ; RV32I-MO: bb.0: + ; RV32I-MO-NEXT: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: $x11 = ORI $x11, 1023 + ; RV32I-MO-NEXT: $x12 = ADDI $x10, 17 + ; RV32I-MO-NEXT: $x11 = AND $x12, $x11 + ; RV32I-MO-NEXT: $x10 = SUB $x10, $x11 + ; RV32I-MO-NEXT: BEQ $x10, $x11, %bb.1 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: bb.1: + ; RV32I-MO-NEXT: liveins: $x10, $x5, $x6, $x7, $x28, $x29, $x30, $x31 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: PseudoRET implicit $x10, implicit $x5, implicit $x6, implicit $x7, implicit $x28, implicit $x29, implicit $x30, implicit $x31 + ; + ; RV64I-MO-LABEL: name: dont_outline + ; RV64I-MO: bb.0: + ; RV64I-MO-NEXT: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: $x11 = ORI $x11, 1023 + ; RV64I-MO-NEXT: $x12 = ADDI $x10, 17 + ; RV64I-MO-NEXT: $x11 = AND $x12, $x11 + ; RV64I-MO-NEXT: $x10 = SUB $x10, $x11 + ; RV64I-MO-NEXT: BEQ $x10, $x11, %bb.1 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: bb.1: + ; RV64I-MO-NEXT: liveins: $x10, $x5, $x6, $x7, $x28, $x29, $x30, $x31 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: PseudoRET implicit $x10, implicit $x5, implicit $x6, implicit $x7, implicit $x28, implicit $x29, implicit $x30, implicit $x31 + bb.0: + liveins: $x10, $x11 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + BEQ $x10, $x11, %bb.1 + + bb.1: + liveins: $x10, $x5, $x6, $x7, $x28, $x29, $x30, $x31 + PseudoRET implicit $x10, implicit $x5, implicit $x6, implicit $x7, implicit $x28, implicit $x29, implicit $x30, implicit $x31 + +... +--- + +name: outline_1 +tracksRegLiveness: true +isOutlined: false +body: | + bb.0: + liveins: $x10, $x11 + + ; RV32I-MO-LABEL: name: outline_1 + ; RV32I-MO: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; RV32I-MO-NEXT: PseudoRET implicit $x10 + ; + ; RV64I-MO-LABEL: name: outline_1 + ; RV64I-MO: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; RV64I-MO-NEXT: PseudoRET implicit $x10 + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET implicit $x10 + +... +--- +name: outline_2 +tracksRegLiveness: true +isOutlined: false +body: | + bb.0: + liveins: $x10, $x11 + + ; RV32I-MO-LABEL: name: outline_2 + ; RV32I-MO: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; RV32I-MO-NEXT: PseudoRET implicit $x12 + ; + ; RV64I-MO-LABEL: name: outline_2 + ; RV64I-MO: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; RV64I-MO-NEXT: PseudoRET implicit $x12 + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET implicit $x12 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir new file mode 100644 index 0000000..78d242b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir @@ -0,0 +1,257 @@ +# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefixes=OUTLINED,RV32I-MO %s +# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefixes=OUTLINED,RV64I-MO %s + +# Combined tests for outlining with CFI instructions on RISC-V: +# 1) All CFIs present in candidate: outline as tail-call and keep CFIs. +# 2) Partial CFIs in function (extra outside candidate): do not outline. +# 3) CFIs present but candidate is not a tail-call: do not outline. + +--- | + define void @funcA(i32 %a, i32 %b) nounwind { ret void } + define void @funcB(i32 %a, i32 %b) nounwind { ret void } + define void @funcC(i32 %a, i32 %b) nounwind { ret void } + define void @funcD(i32 %a, i32 %b) nounwind { ret void } + define void @funcE(i32 %a, i32 %b) nounwind { ret void } + define void @funcF(i32 %a, i32 %b) nounwind { ret void } +... + +# Case 1: All CFIs present; expect outlining and CFIs retained in outlined body. +--- +name: funcA +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: funcA + ; RV32I-MO: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: funcA + ; RV64I-MO: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + $x10 = ORI $x10, 1023 + CFI_INSTRUCTION offset $x1, 0 + $x11 = ORI $x11, 1023 + CFI_INSTRUCTION offset $x1, -4 + $x12 = ADDI $x10, 17 + CFI_INSTRUCTION offset $x1, -8 + $x11 = AND $x12, $x11 + CFI_INSTRUCTION offset $x1, -12 + $x10 = SUB $x10, $x11 + PseudoRET +... +--- +name: funcB +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: funcB + ; RV32I-MO: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: funcB + ; RV64I-MO: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + $x10 = ORI $x10, 1023 + CFI_INSTRUCTION offset $x1, 0 + $x11 = ORI $x11, 1023 + CFI_INSTRUCTION offset $x1, -4 + $x12 = ADDI $x10, 17 + CFI_INSTRUCTION offset $x1, -8 + $x11 = AND $x12, $x11 + CFI_INSTRUCTION offset $x1, -12 + $x10 = SUB $x10, $x11 + PseudoRET +... + +# Case 2: Partial CFIs (extra CFI outside candidate in funcD); expect no outlining. +--- +name: funcC +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: funcC + ; RV32I-MO: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: funcC + ; RV64I-MO: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + $x10 = ORI $x10, 1023 + CFI_INSTRUCTION offset $x1, 0 + $x11 = ORI $x11, 1023 + CFI_INSTRUCTION offset $x1, -4 + $x12 = ADDI $x10, 17 + CFI_INSTRUCTION offset $x1, -8 + $x11 = AND $x12, $x11 + CFI_INSTRUCTION offset $x1, -12 + $x10 = SUB $x10, $x11 + PseudoRET +... +--- +name: funcD +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: funcD + ; RV32I-MO: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -16 + ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023 + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0 + ; RV32I-MO-NEXT: $x11 = ORI $x11, 1023 + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4 + ; RV32I-MO-NEXT: $x12 = ADDI $x10, 17 + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8 + ; RV32I-MO-NEXT: $x11 = AND $x12, $x11 + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12 + ; RV32I-MO-NEXT: $x10 = SUB $x10, $x11 + ; RV32I-MO-NEXT: PseudoRET + ; + ; RV64I-MO-LABEL: name: funcD + ; RV64I-MO: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -16 + ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023 + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0 + ; RV64I-MO-NEXT: $x11 = ORI $x11, 1023 + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4 + ; RV64I-MO-NEXT: $x12 = ADDI $x10, 17 + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8 + ; RV64I-MO-NEXT: $x11 = AND $x12, $x11 + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12 + ; RV64I-MO-NEXT: $x10 = SUB $x10, $x11 + ; RV64I-MO-NEXT: PseudoRET + CFI_INSTRUCTION offset $x1, -16 + $x10 = ORI $x10, 1023 + CFI_INSTRUCTION offset $x1, 0 + $x11 = ORI $x11, 1023 + CFI_INSTRUCTION offset $x1, -4 + $x12 = ADDI $x10, 17 + CFI_INSTRUCTION offset $x1, -8 + $x11 = AND $x12, $x11 + CFI_INSTRUCTION offset $x1, -12 + $x10 = SUB $x10, $x11 + PseudoRET +... + +# Case 3: CFIs present but candidate is not a tail-call; expect no outlining. +--- +name: funcE +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: funcE + ; RV32I-MO: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023 + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0 + ; RV32I-MO-NEXT: $x11 = ORI $x11, 1023 + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4 + ; RV32I-MO-NEXT: $x12 = ADDI $x10, 17 + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8 + ; RV32I-MO-NEXT: $x11 = AND $x12, $x11 + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12 + ; RV32I-MO-NEXT: $x10 = SUB $x10, $x11 + ; RV32I-MO-NEXT: $x10 = ADDI $x10, 1 + ; RV32I-MO-NEXT: PseudoRET + ; + ; RV64I-MO-LABEL: name: funcE + ; RV64I-MO: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023 + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0 + ; RV64I-MO-NEXT: $x11 = ORI $x11, 1023 + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4 + ; RV64I-MO-NEXT: $x12 = ADDI $x10, 17 + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8 + ; RV64I-MO-NEXT: $x11 = AND $x12, $x11 + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12 + ; RV64I-MO-NEXT: $x10 = SUB $x10, $x11 + ; RV64I-MO-NEXT: $x10 = ADDI $x10, 1 + ; RV64I-MO-NEXT: PseudoRET + $x10 = ORI $x10, 1023 + CFI_INSTRUCTION offset $x1, 0 + $x11 = ORI $x11, 1023 + CFI_INSTRUCTION offset $x1, -4 + $x12 = ADDI $x10, 17 + CFI_INSTRUCTION offset $x1, -8 + $x11 = AND $x12, $x11 + CFI_INSTRUCTION offset $x1, -12 + $x10 = SUB $x10, $x11 + $x10 = ADDI $x10, 1 + PseudoRET +... +--- +name: funcF +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: funcF + ; RV32I-MO: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023 + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0 + ; RV32I-MO-NEXT: $x11 = ORI $x11, 1023 + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4 + ; RV32I-MO-NEXT: $x12 = ADDI $x10, 17 + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8 + ; RV32I-MO-NEXT: $x11 = AND $x12, $x11 + ; RV32I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12 + ; RV32I-MO-NEXT: $x10 = SUB $x10, $x11 + ; RV32I-MO-NEXT: $x10 = ADDI $x10, 2 + ; RV32I-MO-NEXT: PseudoRET + ; + ; RV64I-MO-LABEL: name: funcF + ; RV64I-MO: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023 + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, 0 + ; RV64I-MO-NEXT: $x11 = ORI $x11, 1023 + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -4 + ; RV64I-MO-NEXT: $x12 = ADDI $x10, 17 + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -8 + ; RV64I-MO-NEXT: $x11 = AND $x12, $x11 + ; RV64I-MO-NEXT: CFI_INSTRUCTION offset $x1, -12 + ; RV64I-MO-NEXT: $x10 = SUB $x10, $x11 + ; RV64I-MO-NEXT: $x10 = ADDI $x10, 2 + ; RV64I-MO-NEXT: PseudoRET + $x10 = ORI $x10, 1023 + CFI_INSTRUCTION offset $x1, 0 + $x11 = ORI $x11, 1023 + CFI_INSTRUCTION offset $x1, -4 + $x12 = ADDI $x10, 17 + CFI_INSTRUCTION offset $x1, -8 + $x11 = AND $x12, $x11 + CFI_INSTRUCTION offset $x1, -12 + $x10 = SUB $x10, $x11 + $x10 = ADDI $x10, 2 + PseudoRET +... + +# OUTLINED-LABEL: name: OUTLINED_FUNCTION_0 +# OUTLINED: liveins: $x11, $x10 +# OUTLINED-NEXT: {{ $}} +# OUTLINED-NEXT: $x10 = ORI $x10, 1023 +# OUTLINED-NEXT: CFI_INSTRUCTION offset $x1, 0 +# OUTLINED-NEXT: $x11 = ORI $x11, 1023 +# OUTLINED-NEXT: CFI_INSTRUCTION offset $x1, -4 +# OUTLINED-NEXT: $x12 = ADDI $x10, 17 +# OUTLINED-NEXT: CFI_INSTRUCTION offset $x1, -8 +# OUTLINED-NEXT: $x11 = AND $x12, $x11 +# OUTLINED-NEXT: CFI_INSTRUCTION offset $x1, -12 +# OUTLINED-NEXT: $x10 = SUB $x10, $x11 +# OUTLINED-NEXT: PseudoRET diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-position.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-position.mir new file mode 100644 index 0000000..47ec447 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-position.mir @@ -0,0 +1,96 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefixes=RV32I-MO %s +# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefixes=RV64I-MO %s + +# Position instructions are illegal to outline. The first instruction won't be outlined +# because position instructions break the sequence. + +--- | + define void @func1(i32 %a, i32 %b) { ret void } + + define void @func2(i32 %a, i32 %b) { ret void } + + define void @func3(i32 %a, i32 %b) { ret void } +... +--- +name: func1 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: func1 + ; RV32I-MO: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023 + ; RV32I-MO-NEXT: EH_LABEL + ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: func1 + ; RV64I-MO: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023 + ; RV64I-MO-NEXT: EH_LABEL + ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + $x10 = ORI $x10, 1023 + EH_LABEL + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET +... +--- +name: func2 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: func2 + ; RV32I-MO: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023 + ; RV32I-MO-NEXT: GC_LABEL + ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: func2 + ; RV64I-MO: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023 + ; RV64I-MO-NEXT: GC_LABEL + ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + $x10 = ORI $x10, 1023 + GC_LABEL + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET +... +--- +name: func3 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: func3 + ; RV32I-MO: liveins: $x10, $x11 + ; RV32I-MO-NEXT: {{ $}} + ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023 + ; RV32I-MO-NEXT: ANNOTATION_LABEL + ; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: func3 + ; RV64I-MO: liveins: $x10, $x11 + ; RV64I-MO-NEXT: {{ $}} + ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023 + ; RV64I-MO-NEXT: ANNOTATION_LABEL + ; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + $x10 = ORI $x10, 1023 + ANNOTATION_LABEL + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-reserved-regs.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-reserved-regs.mir new file mode 100644 index 0000000..5d6a536 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-reserved-regs.mir @@ -0,0 +1,166 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+reserve-x6 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \ +# RUN: -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK-X6-RESERVED %s +# RUN: llc -mtriple=riscv32 -mattr=+reserve-x6,+reserve-x7 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \ +# RUN: -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK-X6-X7-RESERVED %s + +--- | + define i32 @outline_x5_live_reserved_0(i32 %a, i32 %b) { ret i32 0 } + define i32 @outline_x5_live_reserved_1(i32 %a, i32 %b) { ret i32 0 } + define i32 @outline_x5_live_reserved_2(i32 %a, i32 %b) { ret i32 0 } +... +--- +name: outline_x5_live_reserved_0 +tracksRegLiveness: true +body: | + ; CHECK-X6-RESERVED-LABEL: name: outline_x5_live_reserved_0 + ; CHECK-X6-RESERVED: bb.0: + ; CHECK-X6-RESERVED-NEXT: liveins: $x10, $x11, $x5 + ; CHECK-X6-RESERVED-NEXT: {{ $}} + ; CHECK-X6-RESERVED-NEXT: $x7 = ADDI $x5, 0 + ; CHECK-X6-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x7, implicit $x10, implicit $x11 + ; CHECK-X6-RESERVED-NEXT: $x5 = ADDI $x7, 0 + ; CHECK-X6-RESERVED-NEXT: PseudoBR %bb.1 + ; CHECK-X6-RESERVED-NEXT: {{ $}} + ; CHECK-X6-RESERVED-NEXT: bb.1: + ; CHECK-X6-RESERVED-NEXT: liveins: $x5, $x14 + ; CHECK-X6-RESERVED-NEXT: {{ $}} + ; CHECK-X6-RESERVED-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-X6-RESERVED-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-X6-X7-RESERVED-LABEL: name: outline_x5_live_reserved_0 + ; CHECK-X6-X7-RESERVED: bb.0: + ; CHECK-X6-X7-RESERVED-NEXT: liveins: $x10, $x11, $x5 + ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} + ; CHECK-X6-X7-RESERVED-NEXT: $x28 = ADDI $x5, 0 + ; CHECK-X6-X7-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28 + ; CHECK-X6-X7-RESERVED-NEXT: $x5 = ADDI $x28, 0 + ; CHECK-X6-X7-RESERVED-NEXT: PseudoBR %bb.1 + ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} + ; CHECK-X6-X7-RESERVED-NEXT: bb.1: + ; CHECK-X6-X7-RESERVED-NEXT: liveins: $x5, $x14 + ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} + ; CHECK-X6-X7-RESERVED-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-X6-X7-RESERVED-NEXT: PseudoRET implicit $x10 + + bb.0: + liveins: $x10, $x11, $x5 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + PseudoBR %bb.1 + + bb.1: + liveins: $x5, $x14 + $x10 = ADD $x14, $x5 + PseudoRET implicit $x10 +... +--- +name: outline_x5_live_reserved_1 +tracksRegLiveness: true +body: | + ; CHECK-X6-RESERVED-LABEL: name: outline_x5_live_reserved_1 + ; CHECK-X6-RESERVED: bb.0: + ; CHECK-X6-RESERVED-NEXT: liveins: $x10, $x11, $x5 + ; CHECK-X6-RESERVED-NEXT: {{ $}} + ; CHECK-X6-RESERVED-NEXT: $x7 = ADDI $x5, 0 + ; CHECK-X6-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x7, implicit $x10, implicit $x11 + ; CHECK-X6-RESERVED-NEXT: $x5 = ADDI $x7, 0 + ; CHECK-X6-RESERVED-NEXT: PseudoBR %bb.1 + ; CHECK-X6-RESERVED-NEXT: {{ $}} + ; CHECK-X6-RESERVED-NEXT: bb.1: + ; CHECK-X6-RESERVED-NEXT: liveins: $x5, $x14 + ; CHECK-X6-RESERVED-NEXT: {{ $}} + ; CHECK-X6-RESERVED-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-X6-RESERVED-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-X6-X7-RESERVED-LABEL: name: outline_x5_live_reserved_1 + ; CHECK-X6-X7-RESERVED: bb.0: + ; CHECK-X6-X7-RESERVED-NEXT: liveins: $x10, $x11, $x5 + ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} + ; CHECK-X6-X7-RESERVED-NEXT: $x28 = ADDI $x5, 0 + ; CHECK-X6-X7-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28 + ; CHECK-X6-X7-RESERVED-NEXT: $x5 = ADDI $x28, 0 + ; CHECK-X6-X7-RESERVED-NEXT: PseudoBR %bb.1 + ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} + ; CHECK-X6-X7-RESERVED-NEXT: bb.1: + ; CHECK-X6-X7-RESERVED-NEXT: liveins: $x5, $x14 + ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} + ; CHECK-X6-X7-RESERVED-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-X6-X7-RESERVED-NEXT: PseudoRET implicit $x10 + + + bb.0: + liveins: $x10, $x11, $x5 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + PseudoBR %bb.1 + + bb.1: + liveins: $x5, $x14 + $x10 = ADD $x14, $x5 + PseudoRET implicit $x10 +... +--- +name: outline_x5_live_reserved_2 +tracksRegLiveness: true +body: | + ; CHECK-X6-RESERVED-LABEL: name: outline_x5_live_reserved_2 + ; CHECK-X6-RESERVED: bb.0: + ; CHECK-X6-RESERVED-NEXT: liveins: $x10, $x11, $x5 + ; CHECK-X6-RESERVED-NEXT: {{ $}} + ; CHECK-X6-RESERVED-NEXT: $x7 = ADDI $x5, 0 + ; CHECK-X6-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x7, implicit $x10, implicit $x11 + ; CHECK-X6-RESERVED-NEXT: $x5 = ADDI $x7, 0 + ; CHECK-X6-RESERVED-NEXT: PseudoBR %bb.1 + ; CHECK-X6-RESERVED-NEXT: {{ $}} + ; CHECK-X6-RESERVED-NEXT: bb.1: + ; CHECK-X6-RESERVED-NEXT: liveins: $x5, $x14 + ; CHECK-X6-RESERVED-NEXT: {{ $}} + ; CHECK-X6-RESERVED-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-X6-RESERVED-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-X6-X7-RESERVED-LABEL: name: outline_x5_live_reserved_2 + ; CHECK-X6-X7-RESERVED: bb.0: + ; CHECK-X6-X7-RESERVED-NEXT: liveins: $x10, $x11, $x5 + ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} + ; CHECK-X6-X7-RESERVED-NEXT: $x28 = ADDI $x5, 0 + ; CHECK-X6-X7-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28 + ; CHECK-X6-X7-RESERVED-NEXT: $x5 = ADDI $x28, 0 + ; CHECK-X6-X7-RESERVED-NEXT: PseudoBR %bb.1 + ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} + ; CHECK-X6-X7-RESERVED-NEXT: bb.1: + ; CHECK-X6-X7-RESERVED-NEXT: liveins: $x5, $x14 + ; CHECK-X6-X7-RESERVED-NEXT: {{ $}} + ; CHECK-X6-X7-RESERVED-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-X6-X7-RESERVED-NEXT: PseudoRET implicit $x10 + + + bb.0: + liveins: $x10, $x11, $x5 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + PseudoBR %bb.1 + + bb.1: + liveins: $x5, $x14 + $x10 = ADD $x14, $x5 + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave-rv32e.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave-rv32e.mir new file mode 100644 index 0000000..8935c30 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave-rv32e.mir @@ -0,0 +1,250 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+e -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \ +# RUN: -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK %s + +--- | + define i32 @outline_x5_live_0(i32 %a, i32 %b) { ret i32 0 } + define i32 @outline_x5_live_1(i32 %a, i32 %b) { ret i32 0 } + define i32 @outline_x5_live_2(i32 %a, i32 %b) { ret i32 0 } + + define i32 @outline_no_temp_0(i32 %a, i32 %b) { ret i32 0 } + define i32 @outline_no_temp_1(i32 %a, i32 %b) { ret i32 0 } + define i32 @outline_no_temp_2(i32 %a, i32 %b) { ret i32 0 } +... +--- +name: outline_x5_live_0 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: outline_x5_live_0 + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x6 = ADDI $x5, 0 + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x6, implicit $x10, implicit $x11 + ; CHECK-NEXT: $x5 = ADDI $x6, 0 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x5, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x5 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + PseudoBR %bb.1 + + bb.1: + liveins: $x5, $x14 + $x10 = ADD $x14, $x5 + PseudoRET implicit $x10 +... +--- +name: outline_x5_live_1 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: outline_x5_live_1 + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x6 = ADDI $x5, 0 + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x6, implicit $x10, implicit $x11 + ; CHECK-NEXT: $x5 = ADDI $x6, 0 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x5, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x5 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + PseudoBR %bb.1 + + bb.1: + liveins: $x5, $x14 + $x10 = ADD $x14, $x5 + PseudoRET implicit $x10 +... +--- +name: outline_x5_live_2 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: outline_x5_live_2 + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x6 = ADDI $x5, 0 + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x6, implicit $x10, implicit $x11 + ; CHECK-NEXT: $x5 = ADDI $x6, 0 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x5, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x5 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + PseudoBR %bb.1 + + bb.1: + liveins: $x5, $x14 + $x10 = ADD $x14, $x5 + PseudoRET implicit $x10 +... +--- +name: outline_no_temp_0 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: outline_no_temp_0 + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x5, $x6, $x7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ANDI $x11, 1023 + ; CHECK-NEXT: $x12 = ADDI $x10, 17 + ; CHECK-NEXT: $x11 = AND $x12, $x11 + ; CHECK-NEXT: $x14 = SUB $x10, $x11 + ; CHECK-NEXT: $x11 = ANDI $x11, 1023 + ; CHECK-NEXT: $x12 = ADDI $x10, 17 + ; CHECK-NEXT: $x11 = AND $x12, $x11 + ; CHECK-NEXT: $x14 = SUB $x10, $x11 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x5, $x6, $x7, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-NEXT: $x10 = ADD $x10, $x6 + ; CHECK-NEXT: $x10 = ADD $x10, $x7 + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x5, $x6, $x7 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + PseudoBR %bb.1 + + bb.1: + liveins: $x5, $x6, $x7, $x14 + $x10 = ADD $x14, $x5 + $x10 = ADD $x10, $x6 + $x10 = ADD $x10, $x7 + PseudoRET implicit $x10 +... +--- +name: outline_no_temp_1 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: outline_no_temp_1 + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x5, $x6, $x7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ANDI $x11, 1023 + ; CHECK-NEXT: $x12 = ADDI $x10, 17 + ; CHECK-NEXT: $x11 = AND $x12, $x11 + ; CHECK-NEXT: $x14 = SUB $x10, $x11 + ; CHECK-NEXT: $x11 = ANDI $x11, 1023 + ; CHECK-NEXT: $x12 = ADDI $x10, 17 + ; CHECK-NEXT: $x11 = AND $x12, $x11 + ; CHECK-NEXT: $x14 = SUB $x10, $x11 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x5, $x6, $x7, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-NEXT: $x10 = ADD $x10, $x6 + ; CHECK-NEXT: $x10 = ADD $x10, $x7 + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x5, $x6, $x7 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + PseudoBR %bb.1 + + bb.1: + liveins: $x5, $x6, $x7, $x14 + $x10 = ADD $x14, $x5 + $x10 = ADD $x10, $x6 + $x10 = ADD $x10, $x7 + PseudoRET implicit $x10 +... +--- +name: outline_no_temp_2 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: outline_no_temp_2 + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x5, $x6, $x7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ANDI $x11, 1023 + ; CHECK-NEXT: $x12 = ADDI $x10, 17 + ; CHECK-NEXT: $x11 = AND $x12, $x11 + ; CHECK-NEXT: $x14 = SUB $x10, $x11 + ; CHECK-NEXT: $x11 = ANDI $x11, 1023 + ; CHECK-NEXT: $x12 = ADDI $x10, 17 + ; CHECK-NEXT: $x11 = AND $x12, $x11 + ; CHECK-NEXT: $x14 = SUB $x10, $x11 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x5, $x6, $x7, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-NEXT: $x10 = ADD $x10, $x6 + ; CHECK-NEXT: $x10 = ADD $x10, $x7 + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x5, $x6, $x7 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + PseudoBR %bb.1 + + bb.1: + liveins: $x5, $x6, $x7, $x14 + $x10 = ADD $x14, $x5 + $x10 = ADD $x10, $x6 + $x10 = ADD $x10, $x7 + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave.mir new file mode 100644 index 0000000..e473c94 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave.mir @@ -0,0 +1,116 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \ +# RUN: -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK %s +# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \ +# RUN: -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK %s + +--- | + define i32 @outline_x5_live_0(i32 %a, i32 %b) { ret i32 0 } + define i32 @outline_x5_live_1(i32 %a, i32 %b) { ret i32 0 } + define i32 @outline_x5_live_2(i32 %a, i32 %b) { ret i32 0 } +... +--- +name: outline_x5_live_0 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: outline_x5_live_0 + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x6 = ADDI $x5, 0 + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x6, implicit $x10, implicit $x11 + ; CHECK-NEXT: $x5 = ADDI $x6, 0 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x5, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x5 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + PseudoBR %bb.1 + + bb.1: + liveins: $x5, $x14 + $x10 = ADD $x14, $x5 + PseudoRET implicit $x10 +... +--- +name: outline_x5_live_1 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: outline_x5_live_1 + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x6 = ADDI $x5, 0 + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x6, implicit $x10, implicit $x11 + ; CHECK-NEXT: $x5 = ADDI $x6, 0 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x5, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x5 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + PseudoBR %bb.1 + + bb.1: + liveins: $x5, $x14 + $x10 = ADD $x14, $x5 + PseudoRET implicit $x10 +... +--- +name: outline_x5_live_2 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: outline_x5_live_2 + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x6 = ADDI $x5, 0 + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x6, implicit $x10, implicit $x11 + ; CHECK-NEXT: $x5 = ADDI $x6, 0 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x5, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x10 = ADD $x14, $x5 + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $x10, $x11, $x5 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + $x11 = ANDI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x14 = SUB $x10, $x11 + PseudoBR %bb.1 + + bb.1: + liveins: $x5, $x14 + $x10 = ADD $x14, $x5 + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir new file mode 100644 index 0000000..563d155 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir @@ -0,0 +1,65 @@ +# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefix=RV32I-MO %s +# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefix=RV64I-MO %s + +--- | + ; Cannot outline instructions with jump-table index operands + define i32 @foo(i32 %a, i32 %b) #0 { ret i32 0 } + +... +--- +name: foo +tracksRegLiveness: true +jumpTable: + kind: block-address + entries: + - id: 0 + blocks: [ '%bb.0', '%bb.1', '%bb.2', '%bb.3' ] +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: foo + ; RV32I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0 + ; RV32I-MO: $x12 = LUI target-flags(riscv-hi) %jump-table.0 + ; RV32I-MO: $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0 + ; + ; RV64I-MO-LABEL: name: foo + ; RV64I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0 + ; RV64I-MO: $x12 = LUI target-flags(riscv-hi) %jump-table.0 + ; RV64I-MO: $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x12 = LUI target-flags(riscv-hi) %jump-table.0 + $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0 + PseudoBR %bb.3 + + bb.1: + liveins: $x10, $x11 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x12 = LUI target-flags(riscv-hi) %jump-table.0 + $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0 + PseudoBR %bb.3 + + bb.2: + liveins: $x10, $x11 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x12 = LUI target-flags(riscv-hi) %jump-table.0 + $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0 + PseudoBR %bb.3 + + bb.3: + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir new file mode 100644 index 0000000..fd3630b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir @@ -0,0 +1,383 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs -outliner-leaf-descendants=false < %s \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs -outliner-leaf-descendants=false < %s \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs -outliner-leaf-descendants=false < %s \ +# RUN: | FileCheck -check-prefix=CHECK-FS %s +# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs -outliner-leaf-descendants=false < %s \ +# RUN: | FileCheck -check-prefix=CHECK-FS %s + +--- | + ; Cannot outline instructions with pcrel-lo operands if function section + ; enabled. + @bar = dso_local local_unnamed_addr global i32 0, align 4 + define i32 @foo(i32 %a, i32 %b) { ret i32 0 } + + $foo2 = comdat any + define i32 @foo2(i32 %a, i32 %b) comdat { ret i32 0 } + + define i32 @foo3(i32 %a, i32 %b) section ".abc" { ret i32 0 } + + define i32 @foo4(i32 %a, i32 %b) !section_prefix !0 { ret i32 0 } + !0 = !{!"function_section_prefix", !"myprefix"} +... +--- +name: foo +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: foo + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13 + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13 + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11, implicit $x13 + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-FS-LABEL: name: foo + ; CHECK-FS: bb.0: + ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-FS-NEXT: PseudoBR %bb.3 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: bb.1: + ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-FS-NEXT: PseudoBR %bb.3 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: bb.2: + ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-FS-NEXT: PseudoBR %bb.3 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: bb.3: + ; CHECK-FS-NEXT: PseudoRET + bb.0: + liveins: $x10, $x11, $x13 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + PseudoBR %bb.3 + + bb.1: + liveins: $x10, $x11, $x13 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + PseudoBR %bb.3 + + bb.2: + liveins: $x10, $x11, $x13 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + PseudoBR %bb.3 + + bb.3: + PseudoRET +... +--- +name: foo2 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: foo2 + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-FS-LABEL: name: foo2 + ; CHECK-FS: bb.0: + ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-FS-NEXT: PseudoBR %bb.3 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: bb.1: + ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-FS-NEXT: PseudoBR %bb.3 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: bb.2: + ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-FS-NEXT: PseudoBR %bb.3 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: bb.3: + ; CHECK-FS-NEXT: PseudoRET + bb.0: + liveins: $x10, $x11, $x13 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + PseudoBR %bb.3 + + bb.1: + liveins: $x10, $x11, $x13 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + PseudoBR %bb.3 + + bb.2: + liveins: $x10, $x11, $x13 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + PseudoBR %bb.3 + + bb.3: + PseudoRET +... +--- +name: foo3 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: foo3 + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ORI $x11, 1023 + ; CHECK-NEXT: $x12 = ADDI $x10, 17 + ; CHECK-NEXT: $x11 = AND $x12, $x11 + ; CHECK-NEXT: $x10 = SUB $x10, $x11 + ; CHECK-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ORI $x11, 1023 + ; CHECK-NEXT: $x12 = ADDI $x10, 17 + ; CHECK-NEXT: $x11 = AND $x12, $x11 + ; CHECK-NEXT: $x10 = SUB $x10, $x11 + ; CHECK-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ORI $x11, 1023 + ; CHECK-NEXT: $x12 = ADDI $x10, 17 + ; CHECK-NEXT: $x11 = AND $x12, $x11 + ; CHECK-NEXT: $x10 = SUB $x10, $x11 + ; CHECK-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-FS-LABEL: name: foo3 + ; CHECK-FS: bb.0: + ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: $x11 = ORI $x11, 1023 + ; CHECK-FS-NEXT: $x12 = ADDI $x10, 17 + ; CHECK-FS-NEXT: $x11 = AND $x12, $x11 + ; CHECK-FS-NEXT: $x10 = SUB $x10, $x11 + ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-FS-NEXT: PseudoBR %bb.3 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: bb.1: + ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: $x11 = ORI $x11, 1023 + ; CHECK-FS-NEXT: $x12 = ADDI $x10, 17 + ; CHECK-FS-NEXT: $x11 = AND $x12, $x11 + ; CHECK-FS-NEXT: $x10 = SUB $x10, $x11 + ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-FS-NEXT: PseudoBR %bb.3 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: bb.2: + ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: $x11 = ORI $x11, 1023 + ; CHECK-FS-NEXT: $x12 = ADDI $x10, 17 + ; CHECK-FS-NEXT: $x11 = AND $x12, $x11 + ; CHECK-FS-NEXT: $x10 = SUB $x10, $x11 + ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-FS-NEXT: PseudoBR %bb.3 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: bb.3: + ; CHECK-FS-NEXT: PseudoRET + bb.0: + liveins: $x10, $x11, $x13 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + PseudoBR %bb.3 + + bb.1: + liveins: $x10, $x11, $x13 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + PseudoBR %bb.3 + + bb.2: + liveins: $x10, $x11, $x13 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + PseudoBR %bb.3 + + bb.3: + PseudoRET +... +--- +name: foo4 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: foo4 + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-FS-LABEL: name: foo4 + ; CHECK-FS: bb.0: + ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-FS-NEXT: PseudoBR %bb.3 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: bb.1: + ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-FS-NEXT: PseudoBR %bb.3 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: bb.2: + ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11 + ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + ; CHECK-FS-NEXT: PseudoBR %bb.3 + ; CHECK-FS-NEXT: {{ $}} + ; CHECK-FS-NEXT: bb.3: + ; CHECK-FS-NEXT: PseudoRET + bb.0: + liveins: $x10, $x11, $x13 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + PseudoBR %bb.3 + + bb.1: + liveins: $x10, $x11, $x13 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + PseudoBR %bb.3 + + bb.2: + liveins: $x10, $x11, $x13 + + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) :: (dereferenceable load (s32) from @bar) + PseudoBR %bb.3 + + bb.3: + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machineoutliner-x5.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machineoutliner-x5.mir new file mode 100644 index 0000000..14a9cd7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machineoutliner-x5.mir @@ -0,0 +1,54 @@ +# Check that modifying X5 register is not a problem for machine outliner + +# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefixes=CHECK,RV32I-MO %s +# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefixes=CHECK,RV64I-MO %s + +--- | + define i32 @outline_tail_1(i32 %a, i32 %b) { ret i32 0 } + + define i32 @outline_tail_2(i32 %a, i32 %b) { ret i32 0 } +... +--- +name: outline_tail_1 +tracksRegLiveness: true +isOutlined: false +body: | + bb.0: + liveins: $x10, $x11, $x5 + ; RV32I-MO-LABEL: name: outline_tail_1 + ; RV32I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x5, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: outline_tail_1 + ; RV64I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x5, implicit $x10, implicit $x11 + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x10 = ADD $x10, $x5 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET implicit $x10 +... +--- +name: outline_tail_2 +tracksRegLiveness: true +isOutlined: false +body: | + bb.0: + liveins: $x10, $x11, $x5 + ; RV32I-MO-LABEL: name: outline_tail_2 + ; RV32I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x5, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: outline_tail_2 + ; RV64I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x5, implicit $x10, implicit $x11 + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x10 = ADD $x10, $x5 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET implicit $x10 +... + + +# CHECK-LABEL: name: OUTLINED_FUNCTION_0 +# CHECK: isOutlined: true diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/machineoutliner.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/machineoutliner.mir new file mode 100644 index 0000000..ab12bfb --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/machineoutliner.mir @@ -0,0 +1,147 @@ +# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefixes=CHECK,RV32I-MO %s +# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefixes=CHECK,RV64I-MO %s + +--- | + define i32 @outline_0(i32 %a, i32 %b) { ret i32 0 } + + define i32 @outline_1(i32 %a, i32 %b) { ret i32 0 } + + define i32 @outline_2(i32 %a, i32 %b) { ret i32 0 } + + ; Should not outline linkonce_odr functions which could be deduplicated by the + ; linker. + define linkonce_odr i32 @dont_outline_0(i32 %a, i32 %b) { ret i32 0 } + + ; Should not outline functions with named linker sections + define i32 @dont_outline_1(i32 %a, i32 %b) section "named" { ret i32 0 } + + ; Cannot outline if the X5 (t0) register is not free + define i32 @dont_outline_2(i32 %a, i32 %b) { ret i32 0 } + +... +--- +name: outline_0 +tracksRegLiveness: true +isOutlined: false +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: outline_0 + ; RV32I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: outline_0 + ; RV64I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET implicit $x10 + +... +--- +name: outline_1 +tracksRegLiveness: true +isOutlined: false +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: outline_1 + ; RV32I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: outline_1 + ; RV64I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET implicit $x10 + +... +--- +name: outline_2 +tracksRegLiveness: true +isOutlined: false +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: outline_2 + ; RV32I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: outline_2 + ; RV64I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET implicit $x10 + +... +--- +name: dont_outline_0 +tracksRegLiveness: true +isOutlined: false +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: dont_outline_0 + ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0 + ; RV32I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: dont_outline_0 + ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0 + ; RV64I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET implicit $x10 + +... +--- +name: dont_outline_1 +tracksRegLiveness: true +isOutlined: false +body: | + bb.0: + liveins: $x10, $x11 + ; RV32I-MO-LABEL: name: dont_outline_1 + ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0 + ; RV32I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: dont_outline_1 + ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0 + ; RV64I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + PseudoRET implicit $x10 + +... +--- +name: dont_outline_2 +tracksRegLiveness: true +isOutlined: false +body: | + bb.0: + liveins: $x10, $x11, $x5 + ; RV32I-MO-LABEL: name: dont_outline_2 + ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0 + ; RV32I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + ; + ; RV64I-MO-LABEL: name: dont_outline_2 + ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0 + ; RV64I-MO-NOT: PseudoTAIL @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11 + $x11 = ORI $x11, 1023 + $x12 = ADDI $x10, 17 + $x11 = AND $x12, $x11 + $x10 = SUB $x10, $x11 + $x10 = ADD $x10, $x5 + PseudoRET implicit $x10 + +... + +# CHECK-LABEL: name: OUTLINED_FUNCTION_0 +# CHECK: isOutlined: true diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-add-mem.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-add-mem.mir new file mode 100644 index 0000000..66029bd --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-add-mem.mir @@ -0,0 +1,102 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+fusion-add-mem | FileCheck %s + +# Test add-mem fusion: ADD + load/store with offset 0 +# This fusion combines an address calculation (ADD) with a memory operation +# that uses the calculated address with zero offset. + +# CHECK: add_lb +# CHECK: Macro fuse: {{.*}}ADD - LB +--- +name: add_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = ADD %1, %2 + %5:gpr = LB %4, 0 + %6:gpr = XORI %3, 3 + $x10 = COPY %6 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: add_lh +# CHECK: Macro fuse: {{.*}}ADD - LH +--- +name: add_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = ADD %1, %2 + %5:gpr = LH %4, 0 + %6:gpr = XORI %3, 3 + $x10 = COPY %6 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: add_sw +# CHECK: Macro fuse: {{.*}}ADD - SW +--- +name: add_sw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = ADD %1, %2 + SW %3, %4, 0 + %5:gpr = XORI %3, 3 + $x10 = COPY %5 + PseudoRET +... + +# CHECK: add_sd +# CHECK: Macro fuse: {{.*}}ADD - SD +--- +name: add_sd +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = ADD %1, %2 + SD %3, %4, 0 + %5:gpr = XORI %3, 3 + $x10 = COPY %5 + PseudoRET +... + +# Test that add-mem fusion does not happen with non-zero offset +# CHECK: add_lb_no_fusion +# CHECK-NOT: Macro fuse: {{.*}}ADD - LB +--- +name: add_lb_no_fusion +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = ADD %1, %2 + %5:gpr = LB %4, 8 + %6:gpr = XORI %3, 3 + $x10 = COPY %6 + $x11 = COPY %5 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-logic-imm-reg.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-logic-imm-reg.mir new file mode 100644 index 0000000..55261ab --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-logic-imm-reg.mir @@ -0,0 +1,62 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+fusion-logic-imm-reg | FileCheck %s + +# Test logic immediate-register fusion: ANDI/ORI/XORI + AND/OR/XOR +# This fusion combines a logic operation with an immediate followed by +# a logic operation on registers. + +# CHECK: andi_and +# CHECK: Macro fuse: {{.*}}ANDI - AND +--- +name: andi_and +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ANDI %1, 255 + %4:gpr = XORI %2, 3 + %5:gpr = AND %3, %2 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: ori_or +# CHECK: Macro fuse: {{.*}}ORI - OR +--- +name: ori_or +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ORI %1, 15 + %4:gpr = XORI %2, 3 + %5:gpr = OR %3, %2 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: xori_xor +# CHECK: Macro fuse: {{.*}}XORI - XOR +--- +name: xori_xor +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = XORI %1, 15 + %4:gpr = XORI %2, 3 + %5:gpr = XOR %3, %2 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-imm.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-imm.mir new file mode 100644 index 0000000..eba113b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-imm.mir @@ -0,0 +1,62 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+fusion-logic-reg-imm | FileCheck %s + +# Test logic register-immediate fusion: AND/OR/XOR + ANDI/ORI/XORI +# This fusion combines a logic operation on registers followed by +# a logic operation with an immediate. + +# CHECK: and_andi +# CHECK: Macro fuse: {{.*}}AND - ANDI +--- +name: and_andi +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = AND %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = ANDI %3, 255 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: or_ori +# CHECK: Macro fuse: {{.*}}OR - ORI +--- +name: or_ori +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = OR %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = ORI %3, 15 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: xor_xori +# CHECK: Macro fuse: {{.*}}XOR - XORI +--- +name: xor_xori +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = XOR %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = XORI %3, 7 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-reg.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-reg.mir new file mode 100644 index 0000000..582d7c7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-reg.mir @@ -0,0 +1,64 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+fusion-logic-reg-reg | FileCheck %s + +# Test logic register-register fusion: AND/OR/XOR + AND/OR/XOR +# This fusion combines two consecutive logic operations on registers. + +# CHECK: and_or +# CHECK: Macro fuse: {{.*}}AND - OR +--- +name: and_or +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = AND %1, %2 + %5:gpr = XORI %3, 3 + %6:gpr = OR %4, %3 + $x10 = COPY %5 + $x11 = COPY %6 + PseudoRET +... + +# CHECK: xor_and +# CHECK: Macro fuse: {{.*}}XOR - AND +--- +name: xor_and +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = XOR %1, %2 + %5:gpr = XORI %3, 3 + %6:gpr = AND %4, %3 + $x10 = COPY %5 + $x11 = COPY %6 + PseudoRET +... + +# CHECK: or_xor +# CHECK: Macro fuse: {{.*}}OR - XOR +--- +name: or_xor +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = OR %1, %2 + %5:gpr = XORI %3, 3 + %6:gpr = XOR %4, %3 + $x10 = COPY %5 + $x11 = COPY %6 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-mul-add.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-mul-add.mir new file mode 100644 index 0000000..08c3f24 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-mul-add.mir @@ -0,0 +1,67 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+m,+fusion-mul-add | FileCheck %s + +# Test mul-add fusion: MUL + ADD and MULW + ADDW +# This fusion combines a multiplication followed by an addition. +# Both instructions must have the same width (W suffix or not). + +# CHECK: mul_add +# CHECK: Macro fuse: {{.*}}MUL - ADD +--- +name: mul_add +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = MUL %1, %2 + %5:gpr = XORI %3, 3 + %6:gpr = ADD %4, %3 + $x10 = COPY %5 + $x11 = COPY %6 + PseudoRET +... + +# CHECK: mulw_addw +# CHECK: Macro fuse: {{.*}}MULW - ADDW +--- +name: mulw_addw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = MULW %1, %2 + %5:gpr = XORI %3, 3 + %6:gpr = ADDW %4, %3 + $x10 = COPY %5 + $x11 = COPY %6 + PseudoRET +... + +# Test that fusion does not happen with different widths +# CHECK: mul_addw_no_fusion +# CHECK-NOT: Macro fuse: {{.*}}MUL - ADDW +--- +name: mul_addw_no_fusion +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = MUL %1, %2 + %5:gpr = XORI %3, 3 + %6:gpr = ADDW %4, %3 + $x10 = COPY %5 + $x11 = COPY %6 + PseudoRET +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-shift-bit-extract.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-shift-bit-extract.mir new file mode 100644 index 0000000..4ce6c14 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusion-shift-bit-extract.mir @@ -0,0 +1,132 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+fusion-shift-bit-extract | FileCheck %s + +# Test shift-bit-extract fusion: SLLI + SRLI/SRAI +# This fusion combines left shift followed by right shift with the constraint +# that the first immediate must be less than or equal to the second immediate. +# It also checks that both instructions have the same width (W suffix or not). + +# CHECK: slli_srli +# CHECK: Macro fuse: {{.*}}SLLI - SRLI +--- +name: slli_srli +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 8 + %3:gpr = XORI %1, 3 + %4:gpr = SRLI %2, 16 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: slli_srai +# CHECK: Macro fuse: {{.*}}SLLI - SRAI +--- +name: slli_srai +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 4 + %3:gpr = XORI %1, 3 + %4:gpr = SRAI %2, 8 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# Test with equal immediates +# CHECK: slli_srai_equal +# CHECK: Macro fuse: {{.*}}SLLI - SRAI +--- +name: slli_srai_equal +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 12 + %3:gpr = XORI %1, 3 + %4:gpr = SRAI %2, 12 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# Test W-suffix variants (32-bit operations on RV64) +# CHECK: slliw_srliw +# CHECK: Macro fuse: {{.*}}SLLIW - SRLIW +--- +name: slliw_srliw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLIW %1, 8 + %3:gpr = XORI %1, 3 + %4:gpr = SRLIW %2, 16 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: slliw_sraiw +# CHECK: Macro fuse: {{.*}}SLLIW - SRAIW +--- +name: slliw_sraiw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLIW %1, 4 + %3:gpr = XORI %1, 3 + %4:gpr = SRAIW %2, 8 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# Test that fusion does not happen with different widths +# CHECK: slli_srliw_no_fusion +# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLIW +--- +name: slli_srliw_no_fusion +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 8 + %3:gpr = XORI %1, 3 + %4:gpr = SRLIW %2, 16 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# Test that fusion does not happen when imm1 > imm2 +# CHECK: slli_srli_no_fusion +# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI +--- +name: slli_srli_no_fusion +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 16 + %3:gpr = XORI %1, 3 + %4:gpr = SRLI %2, 8 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusions.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusions.mir new file mode 100644 index 0000000..77fc03c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/macro-fusions.mir @@ -0,0 +1,1552 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+fusion-lui-addi,+fusion-auipc-addi,+fusion-zexth,+fusion-zextw,+fusion-shifted-zextw,+fusion-ld-add \ +# RUN: -mattr=+fusion-add-load,+fusion-auipc-load,+fusion-lui-load,+fusion-addi-load \ +# RUN: -mattr=+zba,+fusion-shxadd-load \ +# RUN: | FileCheck %s +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+zba,+fusion-bfext | FileCheck --check-prefixes=CHECK-BFEXT %s + +# CHECK: lui_addi:%bb.0 +# CHECK: Macro fuse: {{.*}}LUI - ADDI +--- +name: lui_addi +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = LUI 1 + %3:gpr = XORI %1, 2 + %4:gpr = ADDI %2, 3 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: auipc_addi +# CHECK: Macro fuse: {{.*}}AUIPC - ADDI +--- +name: auipc_addi +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = AUIPC 1 + %3:gpr = XORI %1, 2 + %4:gpr = ADDI %2, 3 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: slli_srli_shifted_zext +# CHECK: Macro fuse: {{.*}}SLLI - SRLI +--- +name: slli_srli_shifted_zext +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 32 + %3:gpr = XORI %1, 3 + %4:gpr = SRLI %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: slli_srli_zexth +# CHECK: Macro fuse: {{.*}}SLLI - SRLI +--- +name: slli_srli_zexth +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 48 + %3:gpr = XORI %1, 3 + %4:gpr = SRLI %2, 48 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: slli_srli_zextw +# CHECK: Macro fuse: {{.*}}SLLI - SRLI +--- +name: slli_srli_zextw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 32 + %3:gpr = XORI %1, 3 + %4:gpr = SRLI %2, 32 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: slli_srli_no_fusion_0 +# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI +--- +name: slli_srli_no_fusion_0 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 32 + %3:gpr = XORI %1, 3 + %4:gpr = SRLI %2, 33 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: slli_srli_no_fusion_1 +# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI +--- +name: slli_srli_no_fusion_1 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 48 + %3:gpr = XORI %1, 3 + %4:gpr = SRLI %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: slli_srli_no_fusion_2 +# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI +--- +name: slli_srli_no_fusion_2 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 31 + %3:gpr = XORI %1, 3 + %4:gpr = SRLI %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: slli_srli_no_fusion_3 +# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI +--- +name: slli_srli_no_fusion_3 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 31 + %3:gpr = XORI %1, 3 + %4:gpr = SRLI %2, 48 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: ld_add +# CHECK: Macro fuse: {{.*}}ADD - LD +--- +name: ld_add +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LD %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: add_lb +# CHECK: Macro fuse: {{.*}}ADD - LB +--- +name: add_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LB %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: add_lh +# CHECK: Macro fuse: {{.*}}ADD - LH +--- +name: add_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LH %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: add_lw +# CHECK: Macro fuse: {{.*}}ADD - LW +--- +name: add_lw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LW %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: add_lbu +# CHECK: Macro fuse: {{.*}}ADD - LBU +--- +name: add_lbu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LBU %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: add_lhu +# CHECK: Macro fuse: {{.*}}ADD - LHU +--- +name: add_lhu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LHU %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: add_lwu +# CHECK: Macro fuse: {{.*}}ADD - LWU +--- +name: add_lwu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LWU %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: auipc_lb +# CHECK: Macro fuse: {{.*}}AUIPC - LB +--- +name: auipc_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = AUIPC 1 + %3:gpr = XORI %1, 2 + %4:gpr = LB %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: auipc_lh +# CHECK: Macro fuse: {{.*}}AUIPC - LH +--- +name: auipc_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = AUIPC 1 + %3:gpr = XORI %1, 2 + %4:gpr = LH %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: auipc_lw +# CHECK: Macro fuse: {{.*}}AUIPC - LW +--- +name: auipc_lw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = AUIPC 1 + %3:gpr = XORI %1, 2 + %4:gpr = LW %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: auipc_ld +# CHECK: Macro fuse: {{.*}}AUIPC - LD +--- +name: auipc_ld +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = AUIPC 1 + %3:gpr = XORI %1, 2 + %4:gpr = LD %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: auipc_lbu +# CHECK: Macro fuse: {{.*}}AUIPC - LBU +--- +name: auipc_lbu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = AUIPC 1 + %3:gpr = XORI %1, 2 + %4:gpr = LBU %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: auipc_lhu +# CHECK: Macro fuse: {{.*}}AUIPC - LHU +--- +name: auipc_lhu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = AUIPC 1 + %3:gpr = XORI %1, 2 + %4:gpr = LHU %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: auipc_lwu +# CHECK: Macro fuse: {{.*}}AUIPC - LWU +--- +name: auipc_lwu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = AUIPC 1 + %3:gpr = XORI %1, 2 + %4:gpr = LWU %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: lui_lb +# CHECK: Macro fuse: {{.*}}LUI - LB +--- +name: lui_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = LUI 1 + %3:gpr = XORI %1, 2 + %4:gpr = LB %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: lui_lh +# CHECK: Macro fuse: {{.*}}LUI - LH +--- +name: lui_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = LUI 1 + %3:gpr = XORI %1, 2 + %4:gpr = LH %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: lui_lw +# CHECK: Macro fuse: {{.*}}LUI - LW +--- +name: lui_lw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = LUI 1 + %3:gpr = XORI %1, 2 + %4:gpr = LW %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: lui_ld +# CHECK: Macro fuse: {{.*}}LUI - LD +--- +name: lui_ld +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = LUI 1 + %3:gpr = XORI %1, 2 + %4:gpr = LD %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: lui_lbu +# CHECK: Macro fuse: {{.*}}LUI - LBU +--- +name: lui_lbu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = LUI 1 + %3:gpr = XORI %1, 2 + %4:gpr = LBU %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: lui_lhu +# CHECK: Macro fuse: {{.*}}LUI - LHU +--- +name: lui_lhu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = LUI 1 + %3:gpr = XORI %1, 2 + %4:gpr = LHU %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: lui_lwu +# CHECK: Macro fuse: {{.*}}LUI - LWU +--- +name: lui_lwu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = LUI 1 + %3:gpr = XORI %1, 2 + %4:gpr = LWU %2, 4 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK-BFEXT: bitfield_extract +# CHECK-BFEXT: Macro fuse: {{.*}}SLLI - SRLI +--- +name: bitfield_extract +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 31 + %3:gpr = XORI %1, 3 + %4:gpr = SRLI %2, 48 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: addi_lb +# CHECK: Macro fuse: {{.*}}ADDI - LB +--- +name: addi_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADDI %1, 8 + %4:gpr = XORI %2, 3 + %5:gpr = LB %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: addi_lh +# CHECK: Macro fuse: {{.*}}ADDI - LH +--- +name: addi_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADDI %1, 8 + %4:gpr = XORI %2, 3 + %5:gpr = LH %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: addi_lw +# CHECK: Macro fuse: {{.*}}ADDI - LW +--- +name: addi_lw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADDI %1, 8 + %4:gpr = XORI %2, 3 + %5:gpr = LW %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: addi_ld +# CHECK: Macro fuse: {{.*}}ADDI - LD +--- +name: addi_ld +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADDI %1, 8 + %4:gpr = XORI %2, 3 + %5:gpr = LD %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: addi_lbu +# CHECK: Macro fuse: {{.*}}ADDI - LBU +--- +name: addi_lbu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADDI %1, 8 + %4:gpr = XORI %2, 3 + %5:gpr = LBU %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: addi_lhu +# CHECK: Macro fuse: {{.*}}ADDI - LHU +--- +name: addi_lhu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADDI %1, 8 + %4:gpr = XORI %2, 3 + %5:gpr = LHU %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: addi_lwu +# CHECK: Macro fuse: {{.*}}ADDI - LWU +--- +name: addi_lwu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADDI %1, 8 + %4:gpr = XORI %2, 3 + %5:gpr = LWU %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: adduw_lb +# CHECK: Macro fuse: {{.*}}ADD_UW - LB +--- +name: adduw_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LB %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: adduw_lh +# CHECK: Macro fuse: {{.*}}ADD_UW - LH +--- +name: adduw_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LH %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: adduw_lw +# CHECK: Macro fuse: {{.*}}ADD_UW - LW +--- +name: adduw_lw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LW %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: adduw_ld +# CHECK: Macro fuse: {{.*}}ADD_UW - LD +--- +name: adduw_ld +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LD %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: adduw_lbu +# CHECK: Macro fuse: {{.*}}ADD_UW - LBU +--- +name: adduw_lbu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LBU %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: adduw_lhu +# CHECK: Macro fuse: {{.*}}ADD_UW - LHU +--- +name: adduw_lhu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LHU %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: adduw_lwu +# CHECK: Macro fuse: {{.*}}ADD_UW - LWU +--- +name: adduw_lwu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LWU %3, 0 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1add_lb +# CHECK: Macro fuse: {{.*}}SH1ADD - LB +--- +name: sh1add_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LB %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2add_lb +# CHECK: Macro fuse: {{.*}}SH2ADD - LB +--- +name: sh2add_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LB %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3add_lb +# CHECK: Macro fuse: {{.*}}SH3ADD - LB +--- +name: sh3add_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LB %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1add_lh +# CHECK: Macro fuse: {{.*}}SH1ADD - LH +--- +name: sh1add_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LH %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2add_lh +# CHECK: Macro fuse: {{.*}}SH2ADD - LH +--- +name: sh2add_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LH %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3add_lh +# CHECK: Macro fuse: {{.*}}SH3ADD - LH +--- +name: sh3add_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LH %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1add_lw +# CHECK: Macro fuse: {{.*}}SH1ADD - LW +--- +name: sh1add_lw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LW %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2add_lw +# CHECK: Macro fuse: {{.*}}SH2ADD - LW +--- +name: sh2add_lw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LW %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3add_lw +# CHECK: Macro fuse: {{.*}}SH3ADD - LW +--- +name: sh3add_lw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LW %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1add_ld +# CHECK: Macro fuse: {{.*}}SH1ADD - LD +--- +name: sh1add_ld +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LD %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2add_ld +# CHECK: Macro fuse: {{.*}}SH2ADD - LD +--- +name: sh2add_ld +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LD %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3add_ld +# CHECK: Macro fuse: {{.*}}SH3ADD - LD +--- +name: sh3add_ld +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LD %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1add_lbu +# CHECK: Macro fuse: {{.*}}SH1ADD - LBU +--- +name: sh1add_lbu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LBU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2add_lbu +# CHECK: Macro fuse: {{.*}}SH2ADD - LBU +--- +name: sh2add_lbu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LBU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3add_lbu +# CHECK: Macro fuse: {{.*}}SH3ADD - LBU +--- +name: sh3add_lbu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LBU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1add_lhu +# CHECK: Macro fuse: {{.*}}SH1ADD - LHU +--- +name: sh1add_lhu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LHU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2add_lhu +# CHECK: Macro fuse: {{.*}}SH2ADD - LHU +--- +name: sh2add_lhu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LHU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3add_lhu +# CHECK: Macro fuse: {{.*}}SH3ADD - LHU +--- +name: sh3add_lhu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LHU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1add_lwu +# CHECK: Macro fuse: {{.*}}SH1ADD - LWU +--- +name: sh1add_lwu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LWU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2add_lwu +# CHECK: Macro fuse: {{.*}}SH2ADD - LWU +--- +name: sh2add_lwu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LWU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3add_lwu +# CHECK: Macro fuse: {{.*}}SH3ADD - LWU +--- +name: sh3add_lwu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LWU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1adduw_lb +# CHECK: Macro fuse: {{.*}}SH1ADD_UW - LB +--- +name: sh1adduw_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LB %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2adduw_lb +# CHECK: Macro fuse: {{.*}}SH2ADD_UW - LB +--- +name: sh2adduw_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LB %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3adduw_lb +# CHECK: Macro fuse: {{.*}}SH3ADD_UW - LB +--- +name: sh3adduw_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LB %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1adduw_lh +# CHECK: Macro fuse: {{.*}}SH1ADD_UW - LH +--- +name: sh1adduw_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LH %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2adduw_lh +# CHECK: Macro fuse: {{.*}}SH2ADD_UW - LH +--- +name: sh2adduw_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LH %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3adduw_lh +# CHECK: Macro fuse: {{.*}}SH3ADD_UW - LH +--- +name: sh3adduw_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LH %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1adduw_lw +# CHECK: Macro fuse: {{.*}}SH1ADD_UW - LW +--- +name: sh1adduw_lw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LW %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2adduw_lw +# CHECK: Macro fuse: {{.*}}SH2ADD_UW - LW +--- +name: sh2adduw_lw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LW %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3adduw_lw +# CHECK: Macro fuse: {{.*}}SH3ADD_UW - LW +--- +name: sh3adduw_lw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LW %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1adduw_ld +# CHECK: Macro fuse: {{.*}}SH1ADD_UW - LD +--- +name: sh1adduw_ld +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LD %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2adduw_ld +# CHECK: Macro fuse: {{.*}}SH2ADD_UW - LD +--- +name: sh2adduw_ld +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LD %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3adduw_ld +# CHECK: Macro fuse: {{.*}}SH3ADD_UW - LD +--- +name: sh3adduw_ld +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LD %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1adduw_lbu +# CHECK: Macro fuse: {{.*}}SH1ADD_UW - LBU +--- +name: sh1adduw_lbu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LBU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2adduw_lbu +# CHECK: Macro fuse: {{.*}}SH2ADD_UW - LBU +--- +name: sh2adduw_lbu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LBU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3adduw_lbu +# CHECK: Macro fuse: {{.*}}SH3ADD_UW - LBU +--- +name: sh3adduw_lbu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LBU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1adduw_lhu +# CHECK: Macro fuse: {{.*}}SH1ADD_UW - LHU +--- +name: sh1adduw_lhu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LHU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2adduw_lhu +# CHECK: Macro fuse: {{.*}}SH2ADD_UW - LHU +--- +name: sh2adduw_lhu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LHU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3adduw_lhu +# CHECK: Macro fuse: {{.*}}SH3ADD_UW - LHU +--- +name: sh3adduw_lhu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LHU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh1adduw_lwu +# CHECK: Macro fuse: {{.*}}SH1ADD_UW - LWU +--- +name: sh1adduw_lwu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH1ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LWU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh2adduw_lwu +# CHECK: Macro fuse: {{.*}}SH2ADD_UW - LWU +--- +name: sh2adduw_lwu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH2ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LWU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: sh3adduw_lwu +# CHECK: Macro fuse: {{.*}}SH3ADD_UW - LWU +--- +name: sh3adduw_lwu +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SH3ADD_UW %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = LWU %3, 8 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir new file mode 100644 index 0000000..e2a0c44 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -o - %s -mtriple=riscv64 -mattr=+c -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck %s +--- | + define void @foo(ptr noundef %ptr) #0 { + entry: + %0 = ptrtoint ptr %ptr to i64 + %1 = getelementptr inbounds i64, ptr %ptr, i64 100 + store i64 1, ptr %1, align 8 + %2 = getelementptr inbounds i64, ptr %ptr, i64 101 + store i64 %0, ptr %2, align 8 + %3 = getelementptr inbounds i64, ptr %ptr, i64 102 + store i64 2, ptr %3, align 8 + ret void + } + + attributes #0 = { minsize } + +... +--- +name: foo +alignment: 2 +tracksRegLiveness: true +liveins: + - { reg: '$x10' } +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: foo + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1 + ; CHECK-NEXT: $x12 = ADDI $x10, 768 + ; CHECK-NEXT: SD killed renamable $x11, $x12, 32 :: (store (s64) into %ir.1) + ; CHECK-NEXT: SD renamable $x10, $x12, 40 :: (store (s64) into %ir.2) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 2 + ; CHECK-NEXT: SD killed renamable $x11, killed $x12, 48 :: (store (s64) into %ir.3) + ; CHECK-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + SD killed renamable $x11, renamable $x10, 800 :: (store (s64) into %ir.1) + SD renamable $x10, renamable $x10, 808 :: (store (s64) into %ir.2) + renamable $x11 = ADDI $x0, 2 + SD killed renamable $x11, killed renamable $x10, 816 :: (store (s64) into %ir.3) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-rv64.mir new file mode 100644 index 0000000..ed740d5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-rv64.mir @@ -0,0 +1,341 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -o - %s -mtriple=riscv64 -mattr=+c -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck %s +--- | + + define void @store_common_value(ptr %a, ptr %b, ptr %c) #0 { + entry: + store i64 0, ptr %a, align 8 + store i64 0, ptr %b, align 8 + store i64 0, ptr %c, align 8 + ret void + } + + define void @store_common_ptr(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, ptr %p) #0 { + entry: + store volatile i64 1, ptr %p, align 8 + store volatile i64 3, ptr %p, align 8 + store volatile i64 5, ptr %p, align 8 + ret void + } + + define void @store_common_ptr_self(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, ptr %p) #0 { + entry: + %q = bitcast ptr %p to ptr + store volatile i64 1, ptr %p, align 8 + store volatile i64 3, ptr %p, align 8 + store volatile ptr %p, ptr %q, align 8 + ret void + } + + define void @load_common_ptr(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, ptr %p) #0 { + entry: + %g = load volatile i64, ptr %p, align 8 + %h = load volatile i64, ptr %p, align 8 + %i = load volatile i64, ptr %p, align 8 + ret void + } + + define void @store_large_offset(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i64, ptr %p, i64 100 + store volatile i64 1, ptr %0, align 8 + %1 = getelementptr inbounds i64, ptr %p, i64 101 + store volatile i64 3, ptr %1, align 8 + %2 = getelementptr inbounds i64, ptr %p, i64 102 + store volatile i64 5, ptr %2, align 8 + %3 = getelementptr inbounds i64, ptr %p, i64 103 + store volatile i64 7, ptr %3, align 8 + ret void + } + + define void @load_large_offset(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i64, ptr %p, i64 100 + %a = load volatile i64, ptr %0, align 8 + %1 = getelementptr inbounds i64, ptr %p, i64 101 + %b = load volatile i64, ptr %1, align 8 + %2 = getelementptr inbounds i64, ptr %p, i64 102 + %c = load volatile i64, ptr %2, align 8 + %3 = getelementptr inbounds i64, ptr %p, i64 103 + %d = load volatile i64, ptr %3, align 8 + ret void + } + + define void @store_common_value_no_opt(ptr %a) #0 { + entry: + store i64 0, ptr %a, align 8 + ret void + } + + define void @store_common_ptr_no_opt(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, ptr %p) #0 { + entry: + store volatile i64 1, ptr %p, align 8 + ret void + } + + define void @load_common_ptr_no_opt(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, ptr %p) #0 { + entry: + %g = load volatile i64, ptr %p, align 8 + ret void + } + + define void @store_large_offset_no_opt(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i64, ptr %p, i64 100 + store volatile i64 1, ptr %0, align 8 + %1 = getelementptr inbounds i64, ptr %p, i64 101 + store volatile i64 3, ptr %1, align 8 + ret void + } + + define void @load_large_offset_no_opt(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i64, ptr %p, i64 100 + %a = load volatile i64, ptr %0, align 8 + %1 = getelementptr inbounds i64, ptr %p, i64 101 + %b = load volatile i64, ptr %1, align 8 + ret void + } + + attributes #0 = { minsize "target-features"="+c" } + +... +--- +name: store_common_value +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: store_common_value + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x13 = ADDI $x0, 0 + ; CHECK-NEXT: SD $x13, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; CHECK-NEXT: SD $x13, killed renamable $x11, 0 :: (store (s64) into %ir.b) + ; CHECK-NEXT: SD $x13, killed renamable $x12, 0 :: (store (s64) into %ir.c) + ; CHECK-NEXT: PseudoRET + SD $x0, killed renamable $x10, 0 :: (store (s64) into %ir.a) + SD $x0, killed renamable $x11, 0 :: (store (s64) into %ir.b) + SD $x0, killed renamable $x12, 0 :: (store (s64) into %ir.c) + PseudoRET + +... +--- +name: store_common_ptr +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: store_common_ptr + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 1 + ; CHECK-NEXT: $x11 = ADDI $x16, 0 + ; CHECK-NEXT: SD killed renamable $x10, $x11, 0 :: (volatile store (s64) into %ir.p) + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 3 + ; CHECK-NEXT: SD killed renamable $x10, $x11, 0 :: (volatile store (s64) into %ir.p) + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 5 + ; CHECK-NEXT: SD killed renamable $x10, killed $x11, 0 :: (volatile store (s64) into %ir.p) + ; CHECK-NEXT: PseudoRET + renamable $x10 = ADDI $x0, 1 + SD killed renamable $x10, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + renamable $x10 = ADDI $x0, 3 + SD killed renamable $x10, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + renamable $x10 = ADDI $x0, 5 + SD killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + PseudoRET + +... +--- +name: store_common_ptr_self +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: store_common_ptr_self + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 1 + ; CHECK-NEXT: $x11 = ADDI $x16, 0 + ; CHECK-NEXT: SD killed renamable $x10, $x11, 0 :: (volatile store (s64) into %ir.p) + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 3 + ; CHECK-NEXT: SD killed renamable $x10, $x11, 0 :: (volatile store (s64) into %ir.p) + ; CHECK-NEXT: SD killed $x11, $x11, 0 :: (volatile store (s64) into %ir.q) + ; CHECK-NEXT: PseudoRET + renamable $x10 = ADDI $x0, 1 + SD killed renamable $x10, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + renamable $x10 = ADDI $x0, 3 + SD killed renamable $x10, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + SD killed renamable $x16, renamable $x16, 0 :: (volatile store (s64) into %ir.q) + PseudoRET + +... +--- +name: load_common_ptr +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_common_ptr + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ADDI $x16, 0 + ; CHECK-NEXT: dead renamable $x10 = LD $x11, 0 :: (volatile load (s64) from %ir.p) + ; CHECK-NEXT: dead renamable $x10 = LD $x11, 0 :: (volatile load (s64) from %ir.p) + ; CHECK-NEXT: dead renamable $x10 = LD killed $x11, 0 :: (volatile load (s64) from %ir.p) + ; CHECK-NEXT: PseudoRET + dead renamable $x10 = LD renamable $x16, 0 :: (volatile load (s64) from %ir.p) + dead renamable $x10 = LD renamable $x16, 0 :: (volatile load (s64) from %ir.p) + dead renamable $x10 = LD killed renamable $x16, 0 :: (volatile load (s64) from %ir.p) + PseudoRET + +... +--- +name: store_large_offset +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: store_large_offset + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1 + ; CHECK-NEXT: $x12 = ADDI $x10, 768 + ; CHECK-NEXT: SD killed renamable $x11, $x12, 32 :: (volatile store (s64) into %ir.0) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3 + ; CHECK-NEXT: SD killed renamable $x11, $x12, 40 :: (volatile store (s64) into %ir.1) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5 + ; CHECK-NEXT: SD killed renamable $x11, $x12, 48 :: (volatile store (s64) into %ir.2) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 7 + ; CHECK-NEXT: SD killed renamable $x11, killed $x12, 56 :: (volatile store (s64) into %ir.3) + ; CHECK-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + SD killed renamable $x11, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + renamable $x11 = ADDI $x0, 3 + SD killed renamable $x11, renamable $x10, 808 :: (volatile store (s64) into %ir.1) + renamable $x11 = ADDI $x0, 5 + SD killed renamable $x11, renamable $x10, 816 :: (volatile store (s64) into %ir.2) + renamable $x11 = ADDI $x0, 7 + SD killed renamable $x11, killed renamable $x10, 824 :: (volatile store (s64) into %ir.3) + PseudoRET + +... +--- +name: load_large_offset +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: load_large_offset + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x12 = ADDI $x10, 768 + ; CHECK-NEXT: dead renamable $x11 = LD $x12, 32 :: (volatile load (s64) from %ir.0) + ; CHECK-NEXT: dead renamable $x11 = LD $x12, 40 :: (volatile load (s64) from %ir.1) + ; CHECK-NEXT: dead renamable $x11 = LD $x12, 48 :: (volatile load (s64) from %ir.2) + ; CHECK-NEXT: dead renamable $x10 = LD killed $x12, 56 :: (volatile load (s64) from %ir.3) + ; CHECK-NEXT: PseudoRET + dead renamable $x11 = LD renamable $x10, 800 :: (volatile load (s64) from %ir.0) + dead renamable $x11 = LD renamable $x10, 808 :: (volatile load (s64) from %ir.1) + dead renamable $x11 = LD renamable $x10, 816 :: (volatile load (s64) from %ir.2) + dead renamable $x10 = LD killed renamable $x10, 824 :: (volatile load (s64) from %ir.3) + PseudoRET + +... +--- +name: store_common_value_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: store_common_value_no_opt + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SD $x0, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; CHECK-NEXT: PseudoRET + SD $x0, killed renamable $x10, 0 :: (store (s64) into %ir.a) + PseudoRET + +... +--- +name: store_common_ptr_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: store_common_ptr_no_opt + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 1 + ; CHECK-NEXT: SD killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; CHECK-NEXT: PseudoRET + renamable $x10 = ADDI $x0, 1 + SD killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + PseudoRET + +... +--- +name: load_common_ptr_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_common_ptr_no_opt + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead renamable $x10 = LD killed renamable $x16, 0 :: (volatile load (s64) from %ir.p) + ; CHECK-NEXT: PseudoRET + dead renamable $x10 = LD killed renamable $x16, 0 :: (volatile load (s64) from %ir.p) + PseudoRET + +... +--- +name: store_large_offset_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: store_large_offset_no_opt + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1 + ; CHECK-NEXT: SD killed renamable $x11, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3 + ; CHECK-NEXT: SD killed renamable $x11, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1) + ; CHECK-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + SD killed renamable $x11, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + renamable $x11 = ADDI $x0, 3 + SD killed renamable $x11, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1) + PseudoRET + +... +--- +name: load_large_offset_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: load_large_offset_no_opt + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead renamable $x11 = LD renamable $x10, 800 :: (volatile load (s64) from %ir.0) + ; CHECK-NEXT: dead renamable $x10 = LD killed renamable $x10, 808 :: (volatile load (s64) from %ir.1) + ; CHECK-NEXT: PseudoRET + dead renamable $x11 = LD renamable $x10, 800 :: (volatile load (s64) from %ir.0) + dead renamable $x10 = LD killed renamable $x10, 808 :: (volatile load (s64) from %ir.1) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-xqci.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-xqci.mir new file mode 100644 index 0000000..949aa89 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-xqci.mir @@ -0,0 +1,586 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+xqcilo,+xqcilia -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32XQCI %s +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zcb,+xqcilo,+xqcilia -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32XQCI_ZCB %s +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+xqcilo -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32XQCI_NOXQCILIA %s +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zcb,+xqcilo -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32XQCI_ZCB_NOXQCILIA %s + +--- | + + define void @load_large_offset_i32(ptr %p) #0 { ret void } + + define void @load_large_offset_s16(ptr %p) #0 { ret void } + + define void @load_large_offset_u16(ptr %p) #0 { ret void } + + define void @load_large_offset_u8(ptr %p) #0 { ret void } + + define void @load_large_offset_s8_no_opt(ptr %p) #0 { ret void } + + define void @store_large_offset_i32(ptr %p) #0 { ret void } + + define void @store_large_offset_i16(ptr %p) #0 { ret void } + + define void @store_large_offset_i8(ptr %p) #0 { ret void } + + define void @store_large_offset_no_opt(ptr %p) #0 { ret void } + + define void @store_large_offset_two_uses(ptr %p) #0 { ret void } + + attributes #0 = { minsize } + +... +--- +name: load_large_offset_i32 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32XQCI-LABEL: name: load_large_offset_i32 + ; RV32XQCI: liveins: $x10 + ; RV32XQCI-NEXT: {{ $}} + ; RV32XQCI-NEXT: $x12 = QC_E_ADDI $x10, 3968 + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LW $x12, 32 :: (load (s32)) + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LW $x12, 36 :: (load (s32)) + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LW $x12, 40 :: (load (s32)) + ; RV32XQCI-NEXT: dead renamable $x10 = QC_E_LW killed $x12, 44 :: (load (s32)) + ; RV32XQCI-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB-LABEL: name: load_large_offset_i32 + ; RV32XQCI_ZCB: liveins: $x10 + ; RV32XQCI_ZCB-NEXT: {{ $}} + ; RV32XQCI_ZCB-NEXT: $x12 = QC_E_ADDI $x10, 3968 + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LW $x12, 32 :: (load (s32)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LW $x12, 36 :: (load (s32)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LW $x12, 40 :: (load (s32)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x10 = QC_E_LW killed $x12, 44 :: (load (s32)) + ; RV32XQCI_ZCB-NEXT: PseudoRET + ; + ; RV32XQCI_NOXQCILIA-LABEL: name: load_large_offset_i32 + ; RV32XQCI_NOXQCILIA: liveins: $x10 + ; RV32XQCI_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LW renamable $x10, 4000 :: (load (s32)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LW renamable $x10, 4004 :: (load (s32)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LW renamable $x10, 4008 :: (load (s32)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x10 = QC_E_LW killed renamable $x10, 4012 :: (load (s32)) + ; RV32XQCI_NOXQCILIA-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB_NOXQCILIA-LABEL: name: load_large_offset_i32 + ; RV32XQCI_ZCB_NOXQCILIA: liveins: $x10 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LW renamable $x10, 4000 :: (load (s32)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LW renamable $x10, 4004 :: (load (s32)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LW renamable $x10, 4008 :: (load (s32)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x10 = QC_E_LW killed renamable $x10, 4012 :: (load (s32)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: PseudoRET + dead renamable $x11 = QC_E_LW renamable $x10, 4000 :: (load (s32)) + dead renamable $x11 = QC_E_LW renamable $x10, 4004 :: (load (s32)) + dead renamable $x11 = QC_E_LW renamable $x10, 4008 :: (load (s32)) + dead renamable $x10 = QC_E_LW killed renamable $x10, 4012 :: (load (s32)) + PseudoRET + +... +--- +name: load_large_offset_s16 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32XQCI-LABEL: name: load_large_offset_s16 + ; RV32XQCI: liveins: $x10 + ; RV32XQCI-NEXT: {{ $}} + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LH renamable $x10, 4000 :: (load (s16)) + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LH renamable $x10, 4000 :: (load (s16)) + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LH renamable $x10, 4002 :: (load (s16)) + ; RV32XQCI-NEXT: dead renamable $x10 = QC_E_LH killed renamable $x10, 4002 :: (load (s16)) + ; RV32XQCI-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB-LABEL: name: load_large_offset_s16 + ; RV32XQCI_ZCB: liveins: $x10 + ; RV32XQCI_ZCB-NEXT: {{ $}} + ; RV32XQCI_ZCB-NEXT: $x12 = QC_E_ADDI $x10, 4000 + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LH $x12, 0 :: (load (s16)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LH $x12, 0 :: (load (s16)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LH $x12, 2 :: (load (s16)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x10 = QC_E_LH killed $x12, 2 :: (load (s16)) + ; RV32XQCI_ZCB-NEXT: PseudoRET + ; + ; RV32XQCI_NOXQCILIA-LABEL: name: load_large_offset_s16 + ; RV32XQCI_NOXQCILIA: liveins: $x10 + ; RV32XQCI_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LH renamable $x10, 4000 :: (load (s16)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LH renamable $x10, 4000 :: (load (s16)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LH renamable $x10, 4002 :: (load (s16)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x10 = QC_E_LH killed renamable $x10, 4002 :: (load (s16)) + ; RV32XQCI_NOXQCILIA-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB_NOXQCILIA-LABEL: name: load_large_offset_s16 + ; RV32XQCI_ZCB_NOXQCILIA: liveins: $x10 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LH renamable $x10, 4000 :: (load (s16)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LH renamable $x10, 4000 :: (load (s16)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LH renamable $x10, 4002 :: (load (s16)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x10 = QC_E_LH killed renamable $x10, 4002 :: (load (s16)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: PseudoRET + dead renamable $x11 = QC_E_LH renamable $x10, 4000 :: (load (s16)) + dead renamable $x11 = QC_E_LH renamable $x10, 4000 :: (load (s16)) + dead renamable $x11 = QC_E_LH renamable $x10, 4002 :: (load (s16)) + dead renamable $x10 = QC_E_LH killed renamable $x10, 4002 :: (load (s16)) + PseudoRET + +... +--- +name: load_large_offset_u16 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32XQCI-LABEL: name: load_large_offset_u16 + ; RV32XQCI: liveins: $x10 + ; RV32XQCI-NEXT: {{ $}} + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LHU renamable $x10, 4000 :: (load (s16)) + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LHU renamable $x10, 4000 :: (load (s16)) + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LHU renamable $x10, 4002 :: (load (s16)) + ; RV32XQCI-NEXT: dead renamable $x10 = QC_E_LHU killed renamable $x10, 4002 :: (load (s16)) + ; RV32XQCI-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB-LABEL: name: load_large_offset_u16 + ; RV32XQCI_ZCB: liveins: $x10 + ; RV32XQCI_ZCB-NEXT: {{ $}} + ; RV32XQCI_ZCB-NEXT: $x12 = QC_E_ADDI $x10, 4000 + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LHU $x12, 0 :: (load (s16)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LHU $x12, 0 :: (load (s16)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LHU $x12, 2 :: (load (s16)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x10 = QC_E_LHU killed $x12, 2 :: (load (s16)) + ; RV32XQCI_ZCB-NEXT: PseudoRET + ; + ; RV32XQCI_NOXQCILIA-LABEL: name: load_large_offset_u16 + ; RV32XQCI_NOXQCILIA: liveins: $x10 + ; RV32XQCI_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LHU renamable $x10, 4000 :: (load (s16)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LHU renamable $x10, 4000 :: (load (s16)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LHU renamable $x10, 4002 :: (load (s16)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x10 = QC_E_LHU killed renamable $x10, 4002 :: (load (s16)) + ; RV32XQCI_NOXQCILIA-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB_NOXQCILIA-LABEL: name: load_large_offset_u16 + ; RV32XQCI_ZCB_NOXQCILIA: liveins: $x10 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LHU renamable $x10, 4000 :: (load (s16)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LHU renamable $x10, 4000 :: (load (s16)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LHU renamable $x10, 4002 :: (load (s16)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x10 = QC_E_LHU killed renamable $x10, 4002 :: (load (s16)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: PseudoRET + dead renamable $x11 = QC_E_LHU renamable $x10, 4000 :: (load (s16)) + dead renamable $x11 = QC_E_LHU renamable $x10, 4000 :: (load (s16)) + dead renamable $x11 = QC_E_LHU renamable $x10, 4002 :: (load (s16)) + dead renamable $x10 = QC_E_LHU killed renamable $x10, 4002 :: (load (s16)) + PseudoRET + +... +--- +name: load_large_offset_u8 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32XQCI-LABEL: name: load_large_offset_u8 + ; RV32XQCI: liveins: $x10 + ; RV32XQCI-NEXT: {{ $}} + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LBU renamable $x10, 4000 :: (load (s8)) + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LBU renamable $x10, 4001 :: (load (s8)) + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LBU renamable $x10, 4002 :: (load (s8)) + ; RV32XQCI-NEXT: dead renamable $x10 = QC_E_LBU killed renamable $x10, 4003 :: (load (s8)) + ; RV32XQCI-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB-LABEL: name: load_large_offset_u8 + ; RV32XQCI_ZCB: liveins: $x10 + ; RV32XQCI_ZCB-NEXT: {{ $}} + ; RV32XQCI_ZCB-NEXT: $x12 = QC_E_ADDI $x10, 4000 + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LBU $x12, 0 :: (load (s8)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LBU $x12, 1 :: (load (s8)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LBU $x12, 2 :: (load (s8)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x10 = QC_E_LBU killed $x12, 3 :: (load (s8)) + ; RV32XQCI_ZCB-NEXT: PseudoRET + ; + ; RV32XQCI_NOXQCILIA-LABEL: name: load_large_offset_u8 + ; RV32XQCI_NOXQCILIA: liveins: $x10 + ; RV32XQCI_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LBU renamable $x10, 4000 :: (load (s8)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LBU renamable $x10, 4001 :: (load (s8)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LBU renamable $x10, 4002 :: (load (s8)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x10 = QC_E_LBU killed renamable $x10, 4003 :: (load (s8)) + ; RV32XQCI_NOXQCILIA-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB_NOXQCILIA-LABEL: name: load_large_offset_u8 + ; RV32XQCI_ZCB_NOXQCILIA: liveins: $x10 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LBU renamable $x10, 4000 :: (load (s8)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LBU renamable $x10, 4001 :: (load (s8)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LBU renamable $x10, 4002 :: (load (s8)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x10 = QC_E_LBU killed renamable $x10, 4003 :: (load (s8)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: PseudoRET + dead renamable $x11 = QC_E_LBU renamable $x10, 4000 :: (load (s8)) + dead renamable $x11 = QC_E_LBU renamable $x10, 4001 :: (load (s8)) + dead renamable $x11 = QC_E_LBU renamable $x10, 4002 :: (load (s8)) + dead renamable $x10 = QC_E_LBU killed renamable $x10, 4003 :: (load (s8)) + PseudoRET + +... +--- +name: load_large_offset_s8_no_opt +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32XQCI-LABEL: name: load_large_offset_s8_no_opt + ; RV32XQCI: liveins: $x10 + ; RV32XQCI-NEXT: {{ $}} + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LB renamable $x10, 4000 :: (load (s8)) + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LB renamable $x10, 4001 :: (load (s8)) + ; RV32XQCI-NEXT: dead renamable $x11 = QC_E_LB renamable $x10, 4002 :: (load (s8)) + ; RV32XQCI-NEXT: dead renamable $x10 = QC_E_LB killed renamable $x10, 4003 :: (load (s8)) + ; RV32XQCI-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB-LABEL: name: load_large_offset_s8_no_opt + ; RV32XQCI_ZCB: liveins: $x10 + ; RV32XQCI_ZCB-NEXT: {{ $}} + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LB renamable $x10, 4000 :: (load (s8)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LB renamable $x10, 4001 :: (load (s8)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x11 = QC_E_LB renamable $x10, 4002 :: (load (s8)) + ; RV32XQCI_ZCB-NEXT: dead renamable $x10 = QC_E_LB killed renamable $x10, 4003 :: (load (s8)) + ; RV32XQCI_ZCB-NEXT: PseudoRET + ; + ; RV32XQCI_NOXQCILIA-LABEL: name: load_large_offset_s8_no_opt + ; RV32XQCI_NOXQCILIA: liveins: $x10 + ; RV32XQCI_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LB renamable $x10, 4000 :: (load (s8)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LB renamable $x10, 4001 :: (load (s8)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LB renamable $x10, 4002 :: (load (s8)) + ; RV32XQCI_NOXQCILIA-NEXT: dead renamable $x10 = QC_E_LB killed renamable $x10, 4003 :: (load (s8)) + ; RV32XQCI_NOXQCILIA-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB_NOXQCILIA-LABEL: name: load_large_offset_s8_no_opt + ; RV32XQCI_ZCB_NOXQCILIA: liveins: $x10 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LB renamable $x10, 4000 :: (load (s8)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LB renamable $x10, 4001 :: (load (s8)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x11 = QC_E_LB renamable $x10, 4002 :: (load (s8)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: dead renamable $x10 = QC_E_LB killed renamable $x10, 4003 :: (load (s8)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: PseudoRET + dead renamable $x11 = QC_E_LB renamable $x10, 4000 :: (load (s8)) + dead renamable $x11 = QC_E_LB renamable $x10, 4001 :: (load (s8)) + dead renamable $x11 = QC_E_LB renamable $x10, 4002 :: (load (s8)) + dead renamable $x10 = QC_E_LB killed renamable $x10, 4003 :: (load (s8)) + PseudoRET + +... +--- +name: store_large_offset_i32 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32XQCI-LABEL: name: store_large_offset_i32 + ; RV32XQCI: liveins: $x10 + ; RV32XQCI-NEXT: {{ $}} + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI-NEXT: $x12 = QC_E_ADDI $x10, 3968 + ; RV32XQCI-NEXT: QC_E_SW killed renamable $x11, $x12, 32 :: (volatile store (s32)) + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI-NEXT: QC_E_SW killed renamable $x11, $x12, 36 :: (volatile store (s32)) + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32XQCI-NEXT: QC_E_SW killed renamable $x11, $x12, 40 :: (volatile store (s32)) + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32XQCI-NEXT: QC_E_SW killed renamable $x11, killed $x12, 44 :: (volatile store (s32)) + ; RV32XQCI-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB-LABEL: name: store_large_offset_i32 + ; RV32XQCI_ZCB: liveins: $x10 + ; RV32XQCI_ZCB-NEXT: {{ $}} + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_ZCB-NEXT: $x12 = QC_E_ADDI $x10, 3968 + ; RV32XQCI_ZCB-NEXT: QC_E_SW killed renamable $x11, $x12, 32 :: (volatile store (s32)) + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI_ZCB-NEXT: QC_E_SW killed renamable $x11, $x12, 36 :: (volatile store (s32)) + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32XQCI_ZCB-NEXT: QC_E_SW killed renamable $x11, $x12, 40 :: (volatile store (s32)) + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32XQCI_ZCB-NEXT: QC_E_SW killed renamable $x11, killed $x12, 44 :: (volatile store (s32)) + ; RV32XQCI_ZCB-NEXT: PseudoRET + ; + ; RV32XQCI_NOXQCILIA-LABEL: name: store_large_offset_i32 + ; RV32XQCI_NOXQCILIA: liveins: $x10 + ; RV32XQCI_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, renamable $x10, 4000 :: (volatile store (s32)) + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, renamable $x10, 4004 :: (volatile store (s32)) + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, renamable $x10, 4008 :: (volatile store (s32)) + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, killed renamable $x10, 4012 :: (volatile store (s32)) + ; RV32XQCI_NOXQCILIA-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB_NOXQCILIA-LABEL: name: store_large_offset_i32 + ; RV32XQCI_ZCB_NOXQCILIA: liveins: $x10 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, renamable $x10, 4000 :: (volatile store (s32)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, renamable $x10, 4004 :: (volatile store (s32)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, renamable $x10, 4008 :: (volatile store (s32)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, killed renamable $x10, 4012 :: (volatile store (s32)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + QC_E_SW killed renamable $x11, renamable $x10, 4000 :: (volatile store (s32)) + renamable $x11 = ADDI $x0, 3 + QC_E_SW killed renamable $x11, renamable $x10, 4004 :: (volatile store (s32)) + renamable $x11 = ADDI $x0, 5 + QC_E_SW killed renamable $x11, renamable $x10, 4008 :: (volatile store (s32)) + renamable $x11 = ADDI $x0, 7 + QC_E_SW killed renamable $x11, killed renamable $x10, 4012 :: (volatile store (s32)) + PseudoRET + +... +--- +name: store_large_offset_i16 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32XQCI-LABEL: name: store_large_offset_i16 + ; RV32XQCI: liveins: $x10 + ; RV32XQCI-NEXT: {{ $}} + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI-NEXT: QC_E_SH killed renamable $x11, renamable $x10, 4000 :: (volatile store (s16)) + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI-NEXT: QC_E_SH killed renamable $x11, renamable $x10, 4000 :: (volatile store (s16)) + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32XQCI-NEXT: QC_E_SH killed renamable $x11, renamable $x10, 4002 :: (volatile store (s16)) + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32XQCI-NEXT: QC_E_SH killed renamable $x11, killed renamable $x10, 4002 :: (volatile store (s16)) + ; RV32XQCI-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB-LABEL: name: store_large_offset_i16 + ; RV32XQCI_ZCB: liveins: $x10 + ; RV32XQCI_ZCB-NEXT: {{ $}} + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_ZCB-NEXT: $x12 = QC_E_ADDI $x10, 4000 + ; RV32XQCI_ZCB-NEXT: QC_E_SH killed renamable $x11, $x12, 0 :: (volatile store (s16)) + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI_ZCB-NEXT: QC_E_SH killed renamable $x11, $x12, 0 :: (volatile store (s16)) + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32XQCI_ZCB-NEXT: QC_E_SH killed renamable $x11, $x12, 2 :: (volatile store (s16)) + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32XQCI_ZCB-NEXT: QC_E_SH killed renamable $x11, killed $x12, 2 :: (volatile store (s16)) + ; RV32XQCI_ZCB-NEXT: PseudoRET + ; + ; RV32XQCI_NOXQCILIA-LABEL: name: store_large_offset_i16 + ; RV32XQCI_NOXQCILIA: liveins: $x10 + ; RV32XQCI_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SH killed renamable $x11, renamable $x10, 4000 :: (volatile store (s16)) + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SH killed renamable $x11, renamable $x10, 4000 :: (volatile store (s16)) + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SH killed renamable $x11, renamable $x10, 4002 :: (volatile store (s16)) + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SH killed renamable $x11, killed renamable $x10, 4002 :: (volatile store (s16)) + ; RV32XQCI_NOXQCILIA-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB_NOXQCILIA-LABEL: name: store_large_offset_i16 + ; RV32XQCI_ZCB_NOXQCILIA: liveins: $x10 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SH killed renamable $x11, renamable $x10, 4000 :: (volatile store (s16)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SH killed renamable $x11, renamable $x10, 4000 :: (volatile store (s16)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SH killed renamable $x11, renamable $x10, 4002 :: (volatile store (s16)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SH killed renamable $x11, killed renamable $x10, 4002 :: (volatile store (s16)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + QC_E_SH killed renamable $x11, renamable $x10, 4000 :: (volatile store (s16)) + renamable $x11 = ADDI $x0, 3 + QC_E_SH killed renamable $x11, renamable $x10, 4000 :: (volatile store (s16)) + renamable $x11 = ADDI $x0, 5 + QC_E_SH killed renamable $x11, renamable $x10, 4002 :: (volatile store (s16)) + renamable $x11 = ADDI $x0, 7 + QC_E_SH killed renamable $x11, killed renamable $x10, 4002 :: (volatile store (s16)) + PseudoRET + +... +--- +name: store_large_offset_i8 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32XQCI-LABEL: name: store_large_offset_i8 + ; RV32XQCI: liveins: $x10 + ; RV32XQCI-NEXT: {{ $}} + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI-NEXT: QC_E_SB killed renamable $x11, renamable $x10, 4000 :: (volatile store (s8)) + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI-NEXT: QC_E_SB killed renamable $x11, renamable $x10, 4001 :: (volatile store (s8)) + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32XQCI-NEXT: QC_E_SB killed renamable $x11, renamable $x10, 4002 :: (volatile store (s8)) + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32XQCI-NEXT: QC_E_SB killed renamable $x11, killed renamable $x10, 4003 :: (volatile store (s8)) + ; RV32XQCI-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB-LABEL: name: store_large_offset_i8 + ; RV32XQCI_ZCB: liveins: $x10 + ; RV32XQCI_ZCB-NEXT: {{ $}} + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_ZCB-NEXT: $x12 = QC_E_ADDI $x10, 4000 + ; RV32XQCI_ZCB-NEXT: QC_E_SB killed renamable $x11, $x12, 0 :: (volatile store (s8)) + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI_ZCB-NEXT: QC_E_SB killed renamable $x11, $x12, 1 :: (volatile store (s8)) + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32XQCI_ZCB-NEXT: QC_E_SB killed renamable $x11, $x12, 2 :: (volatile store (s8)) + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32XQCI_ZCB-NEXT: QC_E_SB killed renamable $x11, killed $x12, 3 :: (volatile store (s8)) + ; RV32XQCI_ZCB-NEXT: PseudoRET + ; + ; RV32XQCI_NOXQCILIA-LABEL: name: store_large_offset_i8 + ; RV32XQCI_NOXQCILIA: liveins: $x10 + ; RV32XQCI_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SB killed renamable $x11, renamable $x10, 4000 :: (volatile store (s8)) + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SB killed renamable $x11, renamable $x10, 4001 :: (volatile store (s8)) + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SB killed renamable $x11, renamable $x10, 4002 :: (volatile store (s8)) + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SB killed renamable $x11, killed renamable $x10, 4003 :: (volatile store (s8)) + ; RV32XQCI_NOXQCILIA-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB_NOXQCILIA-LABEL: name: store_large_offset_i8 + ; RV32XQCI_ZCB_NOXQCILIA: liveins: $x10 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SB killed renamable $x11, renamable $x10, 4000 :: (volatile store (s8)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SB killed renamable $x11, renamable $x10, 4001 :: (volatile store (s8)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SB killed renamable $x11, renamable $x10, 4002 :: (volatile store (s8)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SB killed renamable $x11, killed renamable $x10, 4003 :: (volatile store (s8)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + QC_E_SB killed renamable $x11, renamable $x10, 4000 :: (volatile store (s8)) + renamable $x11 = ADDI $x0, 3 + QC_E_SB killed renamable $x11, renamable $x10, 4001 :: (volatile store (s8)) + renamable $x11 = ADDI $x0, 5 + QC_E_SB killed renamable $x11, renamable $x10, 4002 :: (volatile store (s8)) + renamable $x11 = ADDI $x0, 7 + QC_E_SB killed renamable $x11, killed renamable $x10, 4003 :: (volatile store (s8)) + PseudoRET + +... +--- +name: store_large_offset_no_opt +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32XQCI-LABEL: name: store_large_offset_no_opt + ; RV32XQCI: liveins: $x10 + ; RV32XQCI-NEXT: {{ $}} + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI-NEXT: QC_E_SW killed renamable $x11, renamable $x10, 4000 :: (volatile store (s32)) + ; RV32XQCI-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB-LABEL: name: store_large_offset_no_opt + ; RV32XQCI_ZCB: liveins: $x10 + ; RV32XQCI_ZCB-NEXT: {{ $}} + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_ZCB-NEXT: QC_E_SW killed renamable $x11, renamable $x10, 4000 :: (volatile store (s32)) + ; RV32XQCI_ZCB-NEXT: PseudoRET + ; + ; RV32XQCI_NOXQCILIA-LABEL: name: store_large_offset_no_opt + ; RV32XQCI_NOXQCILIA: liveins: $x10 + ; RV32XQCI_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, renamable $x10, 4000 :: (volatile store (s32)) + ; RV32XQCI_NOXQCILIA-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB_NOXQCILIA-LABEL: name: store_large_offset_no_opt + ; RV32XQCI_ZCB_NOXQCILIA: liveins: $x10 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, renamable $x10, 4000 :: (volatile store (s32)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + QC_E_SW killed renamable $x11, renamable $x10, 4000 :: (volatile store (s32)) + PseudoRET + +... +--- +name: store_large_offset_two_uses +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; RV32XQCI-LABEL: name: store_large_offset_two_uses + ; RV32XQCI: liveins: $x10 + ; RV32XQCI-NEXT: {{ $}} + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI-NEXT: $x12 = QC_E_ADDI $x10, 3968 + ; RV32XQCI-NEXT: QC_E_SW killed renamable $x11, $x12, 32 :: (volatile store (s32)) + ; RV32XQCI-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI-NEXT: QC_E_SW killed renamable $x11, killed $x12, 36 :: (volatile store (s32)) + ; RV32XQCI-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB-LABEL: name: store_large_offset_two_uses + ; RV32XQCI_ZCB: liveins: $x10 + ; RV32XQCI_ZCB-NEXT: {{ $}} + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_ZCB-NEXT: $x12 = QC_E_ADDI $x10, 3968 + ; RV32XQCI_ZCB-NEXT: QC_E_SW killed renamable $x11, $x12, 32 :: (volatile store (s32)) + ; RV32XQCI_ZCB-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI_ZCB-NEXT: QC_E_SW killed renamable $x11, killed $x12, 36 :: (volatile store (s32)) + ; RV32XQCI_ZCB-NEXT: PseudoRET + ; + ; RV32XQCI_NOXQCILIA-LABEL: name: store_large_offset_two_uses + ; RV32XQCI_NOXQCILIA: liveins: $x10 + ; RV32XQCI_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, renamable $x10, 4000 :: (volatile store (s32)) + ; RV32XQCI_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, killed renamable $x10, 4004 :: (volatile store (s32)) + ; RV32XQCI_NOXQCILIA-NEXT: PseudoRET + ; + ; RV32XQCI_ZCB_NOXQCILIA-LABEL: name: store_large_offset_two_uses + ; RV32XQCI_ZCB_NOXQCILIA: liveins: $x10 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: {{ $}} + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, renamable $x10, 4000 :: (volatile store (s32)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: QC_E_SW killed renamable $x11, killed renamable $x10, 4004 :: (volatile store (s32)) + ; RV32XQCI_ZCB_NOXQCILIA-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + QC_E_SW killed renamable $x11, renamable $x10, 4000 :: (volatile store (s32)) + renamable $x11 = ADDI $x0, 3 + QC_E_SW killed renamable $x11, killed renamable $x10, 4004 :: (volatile store (s32)) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-zbc-zhinx.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-zbc-zhinx.mir new file mode 100644 index 0000000..45fcc79 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-zbc-zhinx.mir @@ -0,0 +1,249 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zcb,+zhinx -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=CHECK %s +# RUN: llc -o - %s -mtriple=riscv64 -mattr=+zcb,+zhinx -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=CHECK %s + +--- | + define void @store_common_value_half(ptr %a, ptr %b, ptr %c) #0 { + entry: + store half 0.0, ptr %a, align 2 + store half 0.0, ptr %b, align 2 + store half 0.0, ptr %c, align 2 + ret void + } + + define void @store_common_ptr_half(ptr %p) #0 { + entry: + store volatile half 2.0, ptr %p, align 2 + store volatile half 32.0, ptr %p, align 2 + store volatile half 512.0, ptr %p, align 2 + ret void + } + + define void @load_common_ptr_half(ptr %p) #0 { + entry: + %0 = load volatile half, ptr %p, align 2 + %1 = load volatile half, ptr %p, align 2 + %2 = load volatile half, ptr %p, align 2 + ret void + } + + define void @store_large_offset_half(ptr %p) #0 { + entry: + %0 = getelementptr inbounds half, ptr %p, i32 100 + store volatile half 2.0, ptr %0, align 2 + %1 = getelementptr inbounds half, ptr %p, i32 101 + store volatile half 32.0, ptr %1, align 2 + %2 = getelementptr inbounds half, ptr %p, i32 102 + store volatile half 512.0, ptr %2, align 2 + %3 = getelementptr inbounds half, ptr %p, i32 103 + store volatile half 16384.0, ptr %3, align 2 + ret void + } + + define void @load_large_offset_half(ptr %p) #0 { + entry: + %0 = getelementptr inbounds half, ptr %p, i32 100 + %a = load volatile half, ptr %0, align 2 + %1 = getelementptr inbounds half, ptr %p, i32 100 + %b = load volatile half, ptr %1, align 2 + %2 = getelementptr inbounds half, ptr %p, i32 101 + %c = load volatile half, ptr %2, align 2 + %3 = getelementptr inbounds half, ptr %p, i32 101 + %d = load volatile half, ptr %3, align 2 + ret void + } + + define void @store_large_offset_no_opt_half(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i8, ptr %p, i8 100 + store volatile half 2.0, ptr %0, align 2 + %1 = getelementptr inbounds i8, ptr %p, i8 101 + store volatile half 32.0, ptr %1, align 2 + %2 = getelementptr inbounds i8, ptr %p, i8 104 + store volatile half 512.0, ptr %2, align 2 + ret void + } + + define void @load_large_offset_no_opt_half(ptr %p) #0 { + entry: + %0 = getelementptr inbounds half, ptr %p, i32 100 + %a = load volatile half, ptr %0, align 2 + %1 = getelementptr inbounds half, ptr %p, i32 101 + %c = load volatile half, ptr %1, align 2 + %2 = getelementptr inbounds half, ptr %p, i32 102 + %d = load volatile half, ptr %2, align 2 + ret void + } + + attributes #0 = { minsize } + +... +--- +name: store_common_value_half +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: store_common_value_half + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x13_h = PseudoMV_FPR16INX $x0_h + ; CHECK-NEXT: SH_INX $x13_h, killed renamable $x10, 0 :: (store (s16) into %ir.a) + ; CHECK-NEXT: SH_INX $x13_h, killed renamable $x11, 0 :: (store (s16) into %ir.b) + ; CHECK-NEXT: SH_INX $x13_h, killed renamable $x12, 0 :: (store (s16) into %ir.c) + ; CHECK-NEXT: PseudoRET + SH_INX $x0_h, killed renamable $x10, 0 :: (store (s16) into %ir.a) + SH_INX $x0_h, killed renamable $x11, 0 :: (store (s16) into %ir.b) + SH_INX $x0_h, killed renamable $x12, 0 :: (store (s16) into %ir.c) + PseudoRET + +... +--- +name: store_common_ptr_half +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: store_common_ptr_half + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x10 = LUI 4 + ; CHECK-NEXT: $x11 = ADDI $x16, 0 + ; CHECK-NEXT: SH_INX killed renamable $x10_h, $x11, 0 :: (volatile store (s16) into %ir.p) + ; CHECK-NEXT: renamable $x10 = LUI 5 + ; CHECK-NEXT: SH_INX killed renamable $x10_h, $x11, 0 :: (volatile store (s16) into %ir.p) + ; CHECK-NEXT: renamable $x10 = LUI 6 + ; CHECK-NEXT: SH_INX killed renamable $x10_h, killed $x11, 0 :: (volatile store (s16) into %ir.p) + ; CHECK-NEXT: PseudoRET + renamable $x10 = LUI 4 + SH_INX killed renamable $x10_h, renamable $x16, 0 :: (volatile store (s16) into %ir.p) + renamable $x10 = LUI 5 + SH_INX killed renamable $x10_h, renamable $x16, 0 :: (volatile store (s16) into %ir.p) + renamable $x10 = LUI 6 + SH_INX killed renamable $x10_h, killed renamable $x16, 0 :: (volatile store (s16) into %ir.p) + PseudoRET + +... +--- +name: load_common_ptr_half +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_common_ptr_half + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ADDI $x16, 0 + ; CHECK-NEXT: dead $x10_h = LH_INX $x11, 0 :: (volatile load (s16) from %ir.p) + ; CHECK-NEXT: dead $x10_h = LH_INX $x11, 0 :: (volatile load (s16) from %ir.p) + ; CHECK-NEXT: dead $x10_h = LH_INX killed $x11, 0 :: (volatile load (s16) from %ir.p) + ; CHECK-NEXT: PseudoRET + dead $x10_h = LH_INX renamable $x16, 0 :: (volatile load (s16) from %ir.p) + dead $x10_h = LH_INX renamable $x16, 0 :: (volatile load (s16) from %ir.p) + dead $x10_h = LH_INX killed renamable $x16, 0 :: (volatile load (s16) from %ir.p) + PseudoRET + +... +--- +name: store_large_offset_half +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: store_large_offset_half + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = LUI 4 + ; CHECK-NEXT: $x12 = ADDI $x10, 200 + ; CHECK-NEXT: SH_INX killed renamable $x11_h, $x12, 0 :: (volatile store (s16) into %ir.0) + ; CHECK-NEXT: renamable $x11 = LUI 5 + ; CHECK-NEXT: SH_INX killed renamable $x11_h, $x12, 0 :: (volatile store (s16) into %ir.1) + ; CHECK-NEXT: renamable $x11 = LUI 6 + ; CHECK-NEXT: SH_INX killed renamable $x11_h, $x12, 2 :: (volatile store (s16) into %ir.2) + ; CHECK-NEXT: renamable $x11 = LUI 7 + ; CHECK-NEXT: SH_INX killed renamable $x11_h, killed $x12, 2 :: (volatile store (s16) into %ir.3) + ; CHECK-NEXT: PseudoRET + renamable $x11 = LUI 4 + SH_INX killed renamable $x11_h, renamable $x10, 200 :: (volatile store (s16) into %ir.0) + renamable $x11 = LUI 5 + SH_INX killed renamable $x11_h, renamable $x10, 200 :: (volatile store (s16) into %ir.1) + renamable $x11 = LUI 6 + SH_INX killed renamable $x11_h, renamable $x10, 202 :: (volatile store (s16) into %ir.2) + renamable $x11 = LUI 7 + SH_INX killed renamable $x11_h, killed renamable $x10, 202 :: (volatile store (s16) into %ir.3) + PseudoRET + +... +--- +name: load_large_offset_half +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_large_offset_half + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ADDI $x16, 100 + ; CHECK-NEXT: dead $x10_h = LH_INX $x11, 0 :: (volatile load (s16) from %ir.0) + ; CHECK-NEXT: dead $x10_h = LH_INX $x11, 0 :: (volatile load (s16) from %ir.1) + ; CHECK-NEXT: dead $x10_h = LH_INX $x11, 2 :: (volatile load (s16) from %ir.2) + ; CHECK-NEXT: dead $x10_h = LH_INX killed $x11, 2 :: (volatile load (s16) from %ir.3) + ; CHECK-NEXT: PseudoRET + dead $x10_h = LH_INX renamable $x16, 100 :: (volatile load (s16) from %ir.0) + dead $x10_h = LH_INX renamable $x16, 100 :: (volatile load (s16) from %ir.1) + dead $x10_h = LH_INX renamable $x16, 102 :: (volatile load (s16) from %ir.2) + dead $x10_h = LH_INX killed renamable $x16, 102 :: (volatile load (s16) from %ir.3) + PseudoRET + +... +--- +name: store_large_offset_no_opt_half +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: store_large_offset_no_opt_half + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = LUI 4 + ; CHECK-NEXT: SH_INX killed renamable $x11_h, renamable $x16, 200 :: (volatile store (s16) into %ir.0) + ; CHECK-NEXT: renamable $x11 = LUI 5 + ; CHECK-NEXT: SH_INX killed renamable $x11_h, renamable $x16, 202 :: (volatile store (s16) into %ir.1) + ; CHECK-NEXT: renamable $x11 = LUI 6 + ; CHECK-NEXT: SH_INX killed renamable $x11_h, renamable $x16, 204 :: (volatile store (s16) into %ir.2) + ; CHECK-NEXT: PseudoRET + renamable $x11 = LUI 4 + SH_INX killed renamable $x11_h, renamable $x16, 200 :: (volatile store (s16) into %ir.0) + renamable $x11 = LUI 5 + SH_INX killed renamable $x11_h, renamable $x16, 202 :: (volatile store (s16) into %ir.1) + renamable $x11 = LUI 6 + SH_INX killed renamable $x11_h, renamable $x16, 204 :: (volatile store (s16) into %ir.2) + PseudoRET + +... +--- +name: load_large_offset_no_opt_half +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_large_offset_no_opt_half + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x10_h = LH_INX renamable $x16, 100 :: (volatile load (s8) from %ir.0) + ; CHECK-NEXT: dead $x10_h = LH_INX renamable $x16, 102 :: (volatile load (s8) from %ir.1) + ; CHECK-NEXT: dead $x10_h = LH_INX killed renamable $x16, 104 :: (volatile load (s8) from %ir.2) + ; CHECK-NEXT: PseudoRET + dead $x10_h = LH_INX renamable $x16, 100 :: (volatile load (s8) from %ir.0) + dead $x10_h = LH_INX renamable $x16, 102 :: (volatile load (s8) from %ir.1) + dead $x10_h = LH_INX killed renamable $x16, 104 :: (volatile load (s8) from %ir.2) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir new file mode 100644 index 0000000..d5da151 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir @@ -0,0 +1,584 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zcb -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=CHECK %s +# RUN: llc -o - %s -mtriple=riscv64 -mattr=+zcb -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=CHECK %s + +--- | + define void @store_common_value_i8(ptr %a, ptr %b, ptr %c) #0 { + entry: + store i8 0, ptr %a, align 1 + store i8 0, ptr %b, align 1 + store i8 0, ptr %c, align 1 + ret void + } + + define void @store_common_value_i16(ptr %a, ptr %b, ptr %c) #0 { + entry: + store i16 0, ptr %a, align 2 + store i16 0, ptr %b, align 2 + store i16 0, ptr %c, align 2 + ret void + } + + define void @store_common_ptr_i8(ptr %p) #0 { + entry: + store volatile i8 1, ptr %p, align 1 + store volatile i8 3, ptr %p, align 1 + store volatile i8 5, ptr %p, align 1 + ret void + } + + define void @store_common_ptr_i16(ptr %p) #0 { + entry: + store volatile i16 1, ptr %p, align 2 + store volatile i16 3, ptr %p, align 2 + store volatile i16 5, ptr %p, align 2 + ret void + } + + define void @load_common_ptr_i8(ptr %p) #0 { + entry: + %0 = load volatile i8, ptr %p, align 1 + %a = sext i8 %0 to i32 + %1 = load volatile i8, ptr %p, align 1 + %2 = load volatile i8, ptr %p, align 1 + ret void + } + + define void @load_common_ptr_s16(ptr %p) #0 { + entry: + %0 = load volatile i16, ptr %p, align 2 + %1 = load volatile i16, ptr %p, align 2 + %2 = load volatile i16, ptr %p, align 2 + ret void + } + + define void @load_common_ptr_u16(ptr %p) #0 { + entry: + %0 = load volatile i16, ptr %p, align 2 + %1 = load volatile i16, ptr %p, align 2 + %2 = load volatile i16, ptr %p, align 2 + ret void + } + + define void @store_large_offset_i8(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i8, ptr %p, i8 100 + store volatile i8 1, ptr %0, align 1 + %1 = getelementptr inbounds i8, ptr %p, i8 101 + store volatile i8 3, ptr %1, align 1 + %2 = getelementptr inbounds i8, ptr %p, i8 102 + store volatile i8 5, ptr %2, align 1 + %3 = getelementptr inbounds i8, ptr %p, i8 103 + store volatile i8 7, ptr %3, align 1 + ret void + } + + define void @store_large_offset_i16(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i16, ptr %p, i16 100 + store volatile i16 1, ptr %0, align 2 + %1 = getelementptr inbounds i16, ptr %p, i16 100 + store volatile i16 3, ptr %1, align 2 + %2 = getelementptr inbounds i16, ptr %p, i16 101 + store volatile i16 3, ptr %1, align 2 + %3 = getelementptr inbounds i16, ptr %p, i16 101 + store volatile i16 7, ptr %3, align 2 + ret void + } + + define void @load_large_offset_i8(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i8, ptr %p, i8 100 + %a = load volatile i8, ptr %0 + %1 = getelementptr inbounds i8, ptr %p, i8 101 + %b = load volatile i8, ptr %1 + %2 = getelementptr inbounds i8, ptr %p, i8 102 + %c = load volatile i8, ptr %2 + %3 = getelementptr inbounds i8, ptr %p, i8 103 + %d = load volatile i8, ptr %3 + ret void + } + + define void @load_large_offset_s16(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i16, ptr %p, i16 100 + %a = load volatile i16, ptr %0, align 2 + %1 = getelementptr inbounds i16, ptr %p, i16 100 + %b = load volatile i16, ptr %1, align 2 + %2 = getelementptr inbounds i16, ptr %p, i16 101 + %c = load volatile i16, ptr %2, align 2 + %3 = getelementptr inbounds i16, ptr %p, i16 101 + %d = load volatile i16, ptr %3, align 2 + ret void + } + + define void @load_large_offset_u16(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i16, ptr %p, i16 100 + %a = load volatile i16, ptr %0, align 2 + %1 = getelementptr inbounds i16, ptr %p, i16 100 + %b = load volatile i16, ptr %1, align 2 + %2 = getelementptr inbounds i16, ptr %p, i16 101 + %c = load volatile i16, ptr %2, align 2 + %3 = getelementptr inbounds i16, ptr %p, i16 101 + %d = load volatile i16, ptr %3, align 2 + ret void + } + + define void @store_large_offset_no_opt_i8(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i8, ptr %p, i8 100 + store volatile i8 1, ptr %0, align 1 + %1 = getelementptr inbounds i8, ptr %p, i8 101 + store volatile i8 3, ptr %1, align 1 + %2 = getelementptr inbounds i8, ptr %p, i8 104 + store volatile i8 5, ptr %2, align 1 + ret void + } + + define void @store_large_offset_no_opt_i16(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i16, ptr %p, i16 100 + store volatile i8 1, ptr %0, align 2 + %1 = getelementptr inbounds i16, ptr %p, i16 100 + store volatile i8 3, ptr %1, align 2 + %2 = getelementptr inbounds i16, ptr %p, i16 101 + store volatile i8 5, ptr %2, align 2 + ret void + } + + define void @load_large_offset_no_opt_i8(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i8, ptr %p, i8 100 + %a = load volatile i8, ptr %0 + %1 = getelementptr inbounds i8, ptr %p, i8 101 + %b = load volatile i8, ptr %1 + %2 = getelementptr inbounds i8, ptr %p, i8 103 + %c = load volatile i8, ptr %2 + ret void + } + + define void @load_large_offset_no_opt_s16(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i16, ptr %p, i16 100 + %a = load volatile i16, ptr %0, align 2 + %1 = getelementptr inbounds i16, ptr %p, i16 101 + %c = load volatile i16, ptr %1, align 2 + %2 = getelementptr inbounds i16, ptr %p, i16 102 + %d = load volatile i16, ptr %2, align 2 + ret void + } + + define void @load_large_offset_no_opt_u16(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i16, ptr %p, i16 100 + %a = load volatile i16, ptr %0, align 2 + %1 = getelementptr inbounds i16, ptr %p, i16 101 + %c = load volatile i16, ptr %1, align 2 + %2 = getelementptr inbounds i16, ptr %p, i16 102 + %d = load volatile i16, ptr %2, align 2 + ret void + } + attributes #0 = { minsize } + +... +--- +name: store_common_value_i8 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: store_common_value_i8 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x13 = ADDI $x0, 0 + ; CHECK-NEXT: SB $x13, killed renamable $x10, 0 :: (store (s8) into %ir.a) + ; CHECK-NEXT: SB $x13, killed renamable $x11, 0 :: (store (s8) into %ir.b) + ; CHECK-NEXT: SB $x13, killed renamable $x12, 0 :: (store (s8) into %ir.c) + ; CHECK-NEXT: PseudoRET + SB $x0, killed renamable $x10, 0 :: (store (s8) into %ir.a) + SB $x0, killed renamable $x11, 0 :: (store (s8) into %ir.b) + SB $x0, killed renamable $x12, 0 :: (store (s8) into %ir.c) + PseudoRET + +... +--- +name: store_common_value_i16 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: store_common_value_i16 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x13 = ADDI $x0, 0 + ; CHECK-NEXT: SH $x13, killed renamable $x10, 0 :: (store (s16) into %ir.a) + ; CHECK-NEXT: SH $x13, killed renamable $x11, 0 :: (store (s16) into %ir.b) + ; CHECK-NEXT: SH $x13, killed renamable $x12, 0 :: (store (s16) into %ir.c) + ; CHECK-NEXT: PseudoRET + SH $x0, killed renamable $x10, 0 :: (store (s16) into %ir.a) + SH $x0, killed renamable $x11, 0 :: (store (s16) into %ir.b) + SH $x0, killed renamable $x12, 0 :: (store (s16) into %ir.c) + PseudoRET + +... +--- +name: store_common_ptr_i8 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: store_common_ptr_i8 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 1 + ; CHECK-NEXT: $x11 = ADDI $x16, 0 + ; CHECK-NEXT: SB killed renamable $x10, $x11, 0 :: (volatile store (s8) into %ir.p) + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 3 + ; CHECK-NEXT: SB killed renamable $x10, $x11, 0 :: (volatile store (s8) into %ir.p) + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 5 + ; CHECK-NEXT: SB killed renamable $x10, killed $x11, 0 :: (volatile store (s8) into %ir.p) + ; CHECK-NEXT: PseudoRET + renamable $x10 = ADDI $x0, 1 + SB killed renamable $x10, renamable $x16, 0 :: (volatile store (s8) into %ir.p) + renamable $x10 = ADDI $x0, 3 + SB killed renamable $x10, renamable $x16, 0 :: (volatile store (s8) into %ir.p) + renamable $x10 = ADDI $x0, 5 + SB killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s8) into %ir.p) + PseudoRET + +... +--- +name: store_common_ptr_i16 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: store_common_ptr_i16 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 1 + ; CHECK-NEXT: $x11 = ADDI $x16, 0 + ; CHECK-NEXT: SH killed renamable $x10, $x11, 0 :: (volatile store (s16) into %ir.p) + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 3 + ; CHECK-NEXT: SH killed renamable $x10, $x11, 0 :: (volatile store (s16) into %ir.p) + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 5 + ; CHECK-NEXT: SH killed renamable $x10, killed $x11, 0 :: (volatile store (s16) into %ir.p) + ; CHECK-NEXT: PseudoRET + renamable $x10 = ADDI $x0, 1 + SH killed renamable $x10, renamable $x16, 0 :: (volatile store (s16) into %ir.p) + renamable $x10 = ADDI $x0, 3 + SH killed renamable $x10, renamable $x16, 0 :: (volatile store (s16) into %ir.p) + renamable $x10 = ADDI $x0, 5 + SH killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s16) into %ir.p) + PseudoRET + +... +--- +name: load_common_ptr_i8 +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_common_ptr_i8 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ADDI $x16, 0 + ; CHECK-NEXT: dead $x10 = LBU $x11, 0 :: (volatile load (s8) from %ir.p) + ; CHECK-NEXT: dead $x10 = LBU $x11, 0 :: (volatile load (s8) from %ir.p) + ; CHECK-NEXT: dead $x10 = LBU killed $x11, 0 :: (volatile load (s8) from %ir.p) + ; CHECK-NEXT: PseudoRET + dead $x10 = LBU renamable $x16, 0 :: (volatile load (s8) from %ir.p) + dead $x10 = LBU renamable $x16, 0 :: (volatile load (s8) from %ir.p) + dead $x10 = LBU killed renamable $x16, 0 :: (volatile load (s8) from %ir.p) + PseudoRET + +... +--- +name: load_common_ptr_s16 +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_common_ptr_s16 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ADDI $x16, 0 + ; CHECK-NEXT: dead $x10 = LH $x11, 0 :: (volatile load (s16) from %ir.p) + ; CHECK-NEXT: dead $x10 = LH $x11, 0 :: (volatile load (s16) from %ir.p) + ; CHECK-NEXT: dead $x10 = LH killed $x11, 0 :: (volatile load (s16) from %ir.p) + ; CHECK-NEXT: PseudoRET + dead $x10 = LH renamable $x16, 0 :: (volatile load (s16) from %ir.p) + dead $x10 = LH renamable $x16, 0 :: (volatile load (s16) from %ir.p) + dead $x10 = LH killed renamable $x16, 0 :: (volatile load (s16) from %ir.p) + PseudoRET + +... +--- +name: load_common_ptr_u16 +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_common_ptr_u16 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ADDI $x16, 0 + ; CHECK-NEXT: dead $x10 = LHU $x11, 0 :: (volatile load (s16) from %ir.p) + ; CHECK-NEXT: dead $x10 = LHU $x11, 0 :: (volatile load (s16) from %ir.p) + ; CHECK-NEXT: dead $x10 = LHU killed $x11, 0 :: (volatile load (s16) from %ir.p) + ; CHECK-NEXT: PseudoRET + dead $x10 = LHU renamable $x16, 0 :: (volatile load (s16) from %ir.p) + dead $x10 = LHU renamable $x16, 0 :: (volatile load (s16) from %ir.p) + dead $x10 = LHU killed renamable $x16, 0 :: (volatile load (s16) from %ir.p) + PseudoRET + +... +--- +name: store_large_offset_i8 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: store_large_offset_i8 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1 + ; CHECK-NEXT: $x12 = ADDI $x10, 100 + ; CHECK-NEXT: SB killed renamable $x11, $x12, 0 :: (volatile store (s8) into %ir.0) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3 + ; CHECK-NEXT: SB killed renamable $x11, $x12, 1 :: (volatile store (s8) into %ir.1) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5 + ; CHECK-NEXT: SB killed renamable $x11, $x12, 2 :: (volatile store (s8) into %ir.2) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 7 + ; CHECK-NEXT: SB killed renamable $x11, killed $x12, 3 :: (volatile store (s8) into %ir.3) + ; CHECK-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + SB killed renamable $x11, renamable $x10, 100 :: (volatile store (s8) into %ir.0) + renamable $x11 = ADDI $x0, 3 + SB killed renamable $x11, renamable $x10, 101 :: (volatile store (s8) into %ir.1) + renamable $x11 = ADDI $x0, 5 + SB killed renamable $x11, renamable $x10, 102 :: (volatile store (s8) into %ir.2) + renamable $x11 = ADDI $x0, 7 + SB killed renamable $x11, killed renamable $x10, 103 :: (volatile store (s8) into %ir.3) + PseudoRET + +... +--- +name: store_large_offset_i16 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: store_large_offset_i16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1 + ; CHECK-NEXT: $x12 = ADDI $x10, 200 + ; CHECK-NEXT: SH killed renamable $x11, $x12, 0 :: (volatile store (s16) into %ir.0) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3 + ; CHECK-NEXT: SH killed renamable $x11, $x12, 0 :: (volatile store (s16) into %ir.1) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5 + ; CHECK-NEXT: SH killed renamable $x11, $x12, 2 :: (volatile store (s16) into %ir.2) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 7 + ; CHECK-NEXT: SH killed renamable $x11, killed $x12, 2 :: (volatile store (s16) into %ir.3) + ; CHECK-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + SH killed renamable $x11, renamable $x10, 200 :: (volatile store (s16) into %ir.0) + renamable $x11 = ADDI $x0, 3 + SH killed renamable $x11, renamable $x10, 200 :: (volatile store (s16) into %ir.1) + renamable $x11 = ADDI $x0, 5 + SH killed renamable $x11, renamable $x10, 202 :: (volatile store (s16) into %ir.2) + renamable $x11 = ADDI $x0, 7 + SH killed renamable $x11, killed renamable $x10, 202 :: (volatile store (s16) into %ir.3) + PseudoRET + +... +--- +name: load_large_offset_i8 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_large_offset_i8 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ADDI $x16, 100 + ; CHECK-NEXT: dead $x10 = LBU $x11, 0 :: (volatile load (s8) from %ir.0) + ; CHECK-NEXT: dead $x10 = LBU $x11, 1 :: (volatile load (s8) from %ir.1) + ; CHECK-NEXT: dead $x10 = LBU $x11, 2 :: (volatile load (s8) from %ir.2) + ; CHECK-NEXT: dead $x10 = LBU killed $x11, 3 :: (volatile load (s8) from %ir.3) + ; CHECK-NEXT: PseudoRET + dead $x10 = LBU renamable $x16, 100 :: (volatile load (s8) from %ir.0) + dead $x10 = LBU renamable $x16, 101 :: (volatile load (s8) from %ir.1) + dead $x10 = LBU renamable $x16, 102 :: (volatile load (s8) from %ir.2) + dead $x10 = LBU killed renamable $x16, 103 :: (volatile load (s8) from %ir.3) + PseudoRET + +... +--- +name: load_large_offset_s16 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_large_offset_s16 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ADDI $x16, 100 + ; CHECK-NEXT: dead $x10 = LH $x11, 0 :: (volatile load (s16) from %ir.0) + ; CHECK-NEXT: dead $x10 = LH $x11, 0 :: (volatile load (s16) from %ir.1) + ; CHECK-NEXT: dead $x10 = LH $x11, 2 :: (volatile load (s16) from %ir.2) + ; CHECK-NEXT: dead $x10 = LH killed $x11, 2 :: (volatile load (s16) from %ir.3) + ; CHECK-NEXT: PseudoRET + dead $x10 = LH renamable $x16, 100 :: (volatile load (s16) from %ir.0) + dead $x10 = LH renamable $x16, 100 :: (volatile load (s16) from %ir.1) + dead $x10 = LH renamable $x16, 102 :: (volatile load (s16) from %ir.2) + dead $x10 = LH killed renamable $x16, 102 :: (volatile load (s16) from %ir.3) + PseudoRET + +... +--- +name: load_large_offset_u16 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_large_offset_u16 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = ADDI $x16, 100 + ; CHECK-NEXT: dead $x10 = LHU $x11, 0 :: (volatile load (s16) from %ir.0) + ; CHECK-NEXT: dead $x10 = LHU $x11, 0 :: (volatile load (s16) from %ir.1) + ; CHECK-NEXT: dead $x10 = LHU $x11, 2 :: (volatile load (s16) from %ir.2) + ; CHECK-NEXT: dead $x10 = LHU killed $x11, 2 :: (volatile load (s16) from %ir.3) + ; CHECK-NEXT: PseudoRET + dead $x10 = LHU renamable $x16, 100 :: (volatile load (s16) from %ir.0) + dead $x10 = LHU renamable $x16, 100 :: (volatile load (s16) from %ir.1) + dead $x10 = LHU renamable $x16, 102 :: (volatile load (s16) from %ir.2) + dead $x10 = LHU killed renamable $x16, 102 :: (volatile load (s16) from %ir.3) + PseudoRET + +... +--- +name: store_large_offset_no_opt_i8 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: store_large_offset_no_opt_i8 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1 + ; CHECK-NEXT: SB killed renamable $x11, renamable $x16, 100 :: (volatile store (s8) into %ir.0) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3 + ; CHECK-NEXT: SB killed renamable $x11, renamable $x16, 101 :: (volatile store (s8) into %ir.1) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5 + ; CHECK-NEXT: SB killed renamable $x11, renamable $x16, 104 :: (volatile store (s8) into %ir.2) + ; CHECK-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + SB killed renamable $x11, renamable $x16, 100 :: (volatile store (s8) into %ir.0) + renamable $x11 = ADDI $x0, 3 + SB killed renamable $x11, renamable $x16, 101 :: (volatile store (s8) into %ir.1) + renamable $x11 = ADDI $x0, 5 + SB killed renamable $x11, renamable $x16, 104 :: (volatile store (s8) into %ir.2) + PseudoRET + +... +--- +name: store_large_offset_no_opt_i16 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: store_large_offset_no_opt_i16 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1 + ; CHECK-NEXT: SH killed renamable $x11, renamable $x16, 200 :: (volatile store (s16) into %ir.0) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3 + ; CHECK-NEXT: SH killed renamable $x11, renamable $x16, 202 :: (volatile store (s16) into %ir.1) + ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5 + ; CHECK-NEXT: SH killed renamable $x11, renamable $x16, 204 :: (volatile store (s16) into %ir.2) + ; CHECK-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + SH killed renamable $x11, renamable $x16, 200 :: (volatile store (s16) into %ir.0) + renamable $x11 = ADDI $x0, 3 + SH killed renamable $x11, renamable $x16, 202 :: (volatile store (s16) into %ir.1) + renamable $x11 = ADDI $x0, 5 + SH killed renamable $x11, renamable $x16, 204 :: (volatile store (s16) into %ir.2) + PseudoRET + +... +--- +name: load_large_offset_no_opt_i8 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_large_offset_no_opt_i8 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x10 = LBU renamable $x16, 100 :: (volatile load (s8) from %ir.0) + ; CHECK-NEXT: dead $x10 = LBU renamable $x16, 101 :: (volatile load (s8) from %ir.1) + ; CHECK-NEXT: dead $x10 = LBU killed renamable $x16, 104 :: (volatile load (s8) from %ir.2) + ; CHECK-NEXT: PseudoRET + dead $x10 = LBU renamable $x16, 100 :: (volatile load (s8) from %ir.0) + dead $x10 = LBU renamable $x16, 101 :: (volatile load (s8) from %ir.1) + dead $x10 = LBU killed renamable $x16, 104 :: (volatile load (s8) from %ir.2) + PseudoRET + +... +--- +name: load_large_offset_no_opt_s16 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_large_offset_no_opt_s16 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x10 = LH renamable $x16, 100 :: (volatile load (s8) from %ir.0) + ; CHECK-NEXT: dead $x10 = LH renamable $x16, 102 :: (volatile load (s8) from %ir.1) + ; CHECK-NEXT: dead $x10 = LH killed renamable $x16, 104 :: (volatile load (s8) from %ir.2) + ; CHECK-NEXT: PseudoRET + dead $x10 = LH renamable $x16, 100 :: (volatile load (s8) from %ir.0) + dead $x10 = LH renamable $x16, 102 :: (volatile load (s8) from %ir.1) + dead $x10 = LH killed renamable $x16, 104 :: (volatile load (s8) from %ir.2) + PseudoRET + +... +--- +name: load_large_offset_no_opt_u16 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_large_offset_no_opt_u16 + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x10 = LHU renamable $x16, 100 :: (volatile load (s8) from %ir.0) + ; CHECK-NEXT: dead $x10 = LHU renamable $x16, 102 :: (volatile load (s8) from %ir.1) + ; CHECK-NEXT: dead $x10 = LHU killed renamable $x16, 104 :: (volatile load (s8) from %ir.2) + ; CHECK-NEXT: PseudoRET + dead $x10 = LHU renamable $x16, 100 :: (volatile load (s8) from %ir.0) + dead $x10 = LHU renamable $x16, 102 :: (volatile load (s8) from %ir.1) + dead $x10 = LHU killed renamable $x16, 104 :: (volatile load (s8) from %ir.2) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-zfinx.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-zfinx.mir new file mode 100644 index 0000000..d0223dc --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-zfinx.mir @@ -0,0 +1,296 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+c,+zfinx -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=CHECK %s +# RUN: llc -o - %s -mtriple=riscv64 -mattr=+c,+zfinx -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=CHECK %s + +--- | + + define void @store_common_value_float(ptr %a, ptr %b, ptr %c, float %d, float %e, float %f, float %g, float %h, float %i, float %j) #0 { + entry: + store float %j, ptr %a, align 4 + store float %j, ptr %b, align 4 + store float %j, ptr %c, align 4 + ret void + } + + define void @store_common_ptr_float(float %a, float %b, float %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, ptr %p) #0 { + entry: + store volatile float %a, ptr %p, align 4 + store volatile float %b, ptr %p, align 4 + store volatile float %c, ptr %p, align 4 + ret void + } + + define void @load_common_ptr_float(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) #0 { + entry: + %0 = load float, ptr %g, align 4 + %arrayidx1 = getelementptr inbounds float, ptr %g, i32 1 + %1 = load float, ptr %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds float, ptr %g, i32 2 + %2 = load float, ptr %arrayidx2, align 4 + tail call void @load_common_ptr_float_1(float %0, float %1, float %2) + ret void + } + + declare void @load_common_ptr_float_1(float, float, float) #0 + + define void @store_large_offset_float(ptr %p, float %a, float %b, float %c, float %d) #0 { + entry: + %0 = getelementptr inbounds float, ptr %p, i32 100 + store volatile float %a, ptr %0, align 4 + %1 = getelementptr inbounds float, ptr %p, i32 101 + store volatile float %b, ptr %1, align 4 + %2 = getelementptr inbounds float, ptr %p, i32 102 + store volatile float %c, ptr %2, align 4 + %3 = getelementptr inbounds float, ptr %p, i32 103 + store volatile float %d, ptr %3, align 4 + ret void + } + + define void @load_large_offset_float(ptr %p) #0 { + entry: + %arrayidx = getelementptr inbounds float, ptr %p, i32 100 + %0 = load float, ptr %arrayidx, align 4 + %arrayidx1 = getelementptr inbounds float, ptr %p, i32 101 + %1 = load float, ptr %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds float, ptr %p, i32 102 + %2 = load float, ptr %arrayidx2, align 4 + tail call void @load_large_offset_float_1(float %0, float %1, float %2) + ret void + } + + declare void @load_large_offset_float_1(float, float, float) #0 + + define void @store_common_value_float_no_opt(ptr %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h) #0 { + entry: + store float %h, ptr %a, align 4 + ret void + } + + define void @store_common_ptr_float_no_opt(float %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, ptr %p) #0 { + entry: + store volatile float %a, ptr %p, align 4 + ret void + } + + define float @load_common_ptr_float_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) #0 { + entry: + %0 = load float, ptr %g, align 4 + ret float %0 + } + + define void @store_large_offset_float_no_opt(ptr %p, float %a, float %b) #0 { + entry: + %0 = getelementptr inbounds float, ptr %p, i32 100 + store volatile float %a, ptr %0, align 4 + %1 = getelementptr inbounds float, ptr %p, i32 101 + store volatile float %b, ptr %1, align 4 + ret void + } + + define { float, float } @load_large_offset_float_no_opt(ptr %p) #0 { + entry: + %arrayidx = getelementptr inbounds float, ptr %p, i32 100 + %0 = load float, ptr %arrayidx, align 4 + %arrayidx1 = getelementptr inbounds float, ptr %p, i32 101 + %1 = load float, ptr %arrayidx1, align 4 + %2 = insertvalue { float, float } undef, float %0, 0 + %3 = insertvalue { float, float } %2, float %1, 1 + ret { float, float } %3 + } + + attributes #0 = { minsize } + +... +--- +name: store_common_value_float +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: store_common_value_float + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x13_w = PseudoMV_FPR32INX $x0_w + ; CHECK-NEXT: SW_INX $x13_w, killed renamable $x10, 0 :: (store (s32) into %ir.a) + ; CHECK-NEXT: SW_INX $x13_w, killed renamable $x11, 0 :: (store (s32) into %ir.b) + ; CHECK-NEXT: SW_INX killed $x13_w, killed renamable $x12, 0 :: (store (s32) into %ir.c) + ; CHECK-NEXT: PseudoRET + SW_INX $x0_w, killed renamable $x10, 0 :: (store (s32) into %ir.a) + SW_INX $x0_w, killed renamable $x11, 0 :: (store (s32) into %ir.b) + SW_INX killed $x0_w, killed renamable $x12, 0 :: (store (s32) into %ir.c) + PseudoRET + +... +--- +name: store_common_ptr_float +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10_w, $x11_w, $x12_w, $x16 + + ; CHECK-LABEL: name: store_common_ptr_float + ; CHECK: liveins: $x10_w, $x11_w, $x12_w, $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x13 = ADDI $x16, 0 + ; CHECK-NEXT: SW_INX killed renamable $x10_w, $x13, 0 :: (volatile store (s32) into %ir.p) + ; CHECK-NEXT: SW_INX killed renamable $x11_w, $x13, 0 :: (volatile store (s32) into %ir.p) + ; CHECK-NEXT: SW_INX killed renamable $x12_w, killed $x13, 0 :: (volatile store (s32) into %ir.p) + ; CHECK-NEXT: PseudoRET + SW_INX killed renamable $x10_w, renamable $x16, 0 :: (volatile store (s32) into %ir.p) + SW_INX killed renamable $x11_w, renamable $x16, 0 :: (volatile store (s32) into %ir.p) + SW_INX killed renamable $x12_w, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + PseudoRET + +... +--- +name: load_common_ptr_float +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_common_ptr_float + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x13 = ADDI $x16, 0 + ; CHECK-NEXT: renamable $x10_w = LW_INX $x13, 0 :: (load (s32) from %ir.g) + ; CHECK-NEXT: renamable $x11_w = LW_INX $x13, 4 :: (load (s32) from %ir.arrayidx1) + ; CHECK-NEXT: renamable $x12_w = LW_INX killed $x13, 8 :: (load (s32) from %ir.arrayidx2) + ; CHECK-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $x10_w, implicit $x11_w, implicit $x12_w + renamable $x10_w = LW_INX renamable $x16, 0 :: (load (s32) from %ir.g) + renamable $x11_w = LW_INX renamable $x16, 4 :: (load (s32) from %ir.arrayidx1) + renamable $x12_w = LW_INX killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2) + PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $x10_w, implicit $x11_w, implicit $x12_w + +... +--- +name: store_large_offset_float +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11_w, $x11_w, $x12_w, $x13_w + + ; CHECK-LABEL: name: store_large_offset_float + ; CHECK: liveins: $x10, $x11_w, $x11_w, $x12_w, $x13_w + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x14 = ADDI $x10, 384 + ; CHECK-NEXT: SW_INX killed renamable $x10_w, $x14, 16 :: (volatile store (s32) into %ir.0) + ; CHECK-NEXT: SW_INX killed renamable $x11_w, $x14, 20 :: (volatile store (s32) into %ir.1) + ; CHECK-NEXT: SW_INX killed renamable $x12_w, $x14, 24 :: (volatile store (s32) into %ir.2) + ; CHECK-NEXT: SW_INX killed renamable $x13_w, killed $x14, 28 :: (volatile store (s32) into %ir.3) + ; CHECK-NEXT: PseudoRET + SW_INX killed renamable $x10_w, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + SW_INX killed renamable $x11_w, renamable $x10, 404 :: (volatile store (s32) into %ir.1) + SW_INX killed renamable $x12_w, renamable $x10, 408 :: (volatile store (s32) into %ir.2) + SW_INX killed renamable $x13_w, killed renamable $x10, 412 :: (volatile store (s32) into %ir.3) + PseudoRET + +... +--- +name: load_large_offset_float +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: load_large_offset_float + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x14 = ADDI $x10, 384 + ; CHECK-NEXT: renamable $x11_w = LW_INX $x14, 16 :: (load (s32) from %ir.arrayidx) + ; CHECK-NEXT: renamable $x12_w = LW_INX $x14, 20 :: (load (s32) from %ir.arrayidx1) + ; CHECK-NEXT: renamable $x13_w = LW_INX killed $x14, 24 :: (load (s32) from %ir.arrayidx2) + ; CHECK-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $x11_w, implicit $x12_w, implicit $x12_w + renamable $x11_w = LW_INX renamable $x10, 400 :: (load (s32) from %ir.arrayidx) + renamable $x12_w = LW_INX renamable $x10, 404 :: (load (s32) from %ir.arrayidx1) + renamable $x13_w = LW_INX killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2) + PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $x11_w, implicit $x12_w, implicit $x12_w + +... +--- +name: store_common_value_float_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x16_w + + ; CHECK-LABEL: name: store_common_value_float_no_opt + ; CHECK: liveins: $x10, $x16_w + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SW_INX killed renamable $x16_w, killed renamable $x10, 0 :: (store (s32) into %ir.a) + ; CHECK-NEXT: PseudoRET + SW_INX killed renamable $x16_w, killed renamable $x10, 0 :: (store (s32) into %ir.a) + PseudoRET + +... +--- +name: store_common_ptr_float_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16, $x10_w + + ; CHECK-LABEL: name: store_common_ptr_float_no_opt + ; CHECK: liveins: $x16, $x10_w + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SW_INX killed renamable $x10_w, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + ; CHECK-NEXT: PseudoRET + SW_INX killed renamable $x10_w, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + PseudoRET + +... +--- +name: load_common_ptr_float_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; CHECK-LABEL: name: load_common_ptr_float_no_opt + ; CHECK: liveins: $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x10_w = LW_INX killed renamable $x16, 0 :: (load (s32) from %ir.g) + ; CHECK-NEXT: PseudoRET implicit $x10_w + renamable $x10_w = LW_INX killed renamable $x16, 0 :: (load (s32) from %ir.g) + PseudoRET implicit $x10_w + +... +--- +name: store_large_offset_float_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11_w, $x12_w + + ; CHECK-LABEL: name: store_large_offset_float_no_opt + ; CHECK: liveins: $x10, $x11_w, $x12_w + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SW_INX killed renamable $x11_w, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + ; CHECK-NEXT: SW_INX killed renamable $x12_w, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1) + ; CHECK-NEXT: PseudoRET + SW_INX killed renamable $x11_w, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + SW_INX killed renamable $x12_w, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1) + PseudoRET + +... +--- +name: load_large_offset_float_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: load_large_offset_float_no_opt + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x11_w = LW_INX renamable $x10, 400 :: (load (s32) from %ir.arrayidx) + ; CHECK-NEXT: renamable $x12_w = LW_INX killed renamable $x10, 404 :: (load (s32) from %ir.arrayidx1) + ; CHECK-NEXT: PseudoRET implicit $x11_w, implicit $x12_w + renamable $x11_w = LW_INX renamable $x10, 400 :: (load (s32) from %ir.arrayidx) + renamable $x12_w = LW_INX killed renamable $x10, 404 :: (load (s32) from %ir.arrayidx1) + PseudoRET implicit $x11_w, implicit $x12_w + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir new file mode 100644 index 0000000..0c22db2 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir @@ -0,0 +1,370 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zilsd,+zclsd,+zdinx -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32,RV32_NOP %s +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zilsd,+zclsd,+experimental-p -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32,RV32_P %s +--- | + define void @store_common_value_double(ptr %a, ptr %b, ptr %c, i32 %d, double %e, double %f) minsize { + entry: + store double %f, ptr %a, align 8 + store double %f, ptr %b, align 8 + store double %f, ptr %c, align 8 + ret void + } + + define void @store_common_value_double_zero(ptr %a, ptr %b, ptr %c) minsize { + entry: + store double 0.0, ptr %a, align 8 + store double 0.0, ptr %b, align 8 + store double 0.0, ptr %c, align 8 + ret void + } + + define void @store_common_ptr_double(double %a, double %b, double %d, ptr %p) minsize { + entry: + store volatile double %a, ptr %p, align 8 + store volatile double %b, ptr %p, align 8 + store volatile double %b, ptr %p, align 8 + ret void + } + + define void @load_common_ptr_double(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) minsize { + entry: + %0 = load double, ptr %g, align 8 + %arrayidx1 = getelementptr inbounds { double, double, i32 }, ptr %g, i32 0, i32 1 + %1 = load double, ptr %arrayidx1, align 8 + %arrayidx2 = getelementptr inbounds { double, double, i32 }, ptr %g, i32 0, i32 2 + %2 = load i32, ptr %arrayidx2, align 8 + tail call void @load_common_ptr_double_1(double %0, double %1, i32 %2) + ret void + } + + declare void @load_common_ptr_double_1(double, double, double) minsize + + define void @store_large_offset_double(ptr %p, i32 %dummy, double %a, double %b, double %c) minsize { + entry: + %0 = getelementptr inbounds double, ptr %p, i32 100 + store volatile double %a, ptr %0, align 8 + %1 = getelementptr inbounds double, ptr %p, i32 101 + store volatile double %b, ptr %1, align 8 + %2 = getelementptr inbounds double, ptr %p, i32 102 + store volatile double %b, ptr %2, align 8 + ret void + } + + define void @load_large_offset_double(i32 %a, i32 %b, i32 %c, i32 %d, ptr %p) minsize { + entry: + %arrayidx = getelementptr inbounds { [102 x double], i32 }, ptr %p, i32 0, i32 0, i32 100 + %0 = load double, ptr %arrayidx, align 8 + %arrayidx1 = getelementptr inbounds { [102 x double], i32 }, ptr %p, i32 0, i32 0, i32 101 + %1 = load double, ptr %arrayidx1, align 8 + %arrayidx2 = getelementptr inbounds { [102 x double], i32 }, ptr %p, i32 0, i32 1 + %2 = load i32, ptr %arrayidx2, align 8 + tail call void @load_large_offset_double_1(double %0, double %1, i32 %2) + ret void + } + + declare void @load_large_offset_double_1(double, double) minsize + + define void @store_common_value_double_no_opt(ptr %a, i32 %b, double %c, double %d, double %e) minsize { + entry: + store double %e, ptr %a, align 8 + ret void + } + + define void @store_common_value_double_no_opt2(ptr %a, i32 %b, double %c, double %d, double %e) minsize { + entry: + store volatile double %e, ptr %a, align 8 + store volatile double %e, ptr %a, align 8 + ret void + } + + define void @store_common_ptr_double_no_opt(double %a, i32 %b, i32 %c, i32 %d, i32 %e, ptr %p) minsize { + entry: + store volatile double %a, ptr %p, align 8 + ret void + } + + define double @load_common_ptr_double_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) minsize { + entry: + %0 = load double, ptr %g, align 8 + ret double %0 + } + + define void @store_large_offset_double_no_opt(ptr %p, double %a, double %b) minsize { + entry: + %0 = getelementptr inbounds double, ptr %p, i32 100 + store volatile double %a, ptr %0, align 8 + %1 = getelementptr inbounds double, ptr %p, i32 101 + store volatile double %b, ptr %1, align 8 + ret void + } + + define { double, double } @load_large_offset_double_no_opt(ptr %p) minsize { + entry: + %arrayidx = getelementptr inbounds double, ptr %p, i32 100 + %0 = load double, ptr %arrayidx, align 8 + %arrayidx1 = getelementptr inbounds double, ptr %p, i32 101 + %1 = load double, ptr %arrayidx1, align 8 + %2 = insertvalue { double, double } undef, double %0, 0 + %3 = insertvalue { double, double } %2, double %1, 1 + ret { double, double } %3 + } +... +--- +name: store_common_value_double +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12, $x16, $x17 + + ; RV32_NOP-LABEL: name: store_common_value_double + ; RV32_NOP: liveins: $x10, $x11, $x12, $x16, $x17 + ; RV32_NOP-NEXT: {{ $}} + ; RV32_NOP-NEXT: $x14_x15 = FSGNJ_D_IN32X $x16_x17, $x16_x17 + ; RV32_NOP-NEXT: SD_RV32 $x14_x15, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; RV32_NOP-NEXT: SD_RV32 $x14_x15, killed renamable $x11, 0 :: (store (s64) into %ir.b) + ; RV32_NOP-NEXT: SD_RV32 killed $x14_x15, killed renamable $x12, 0 :: (store (s64) into %ir.c) + ; RV32_NOP-NEXT: PseudoRET + ; + ; RV32_P-LABEL: name: store_common_value_double + ; RV32_P: liveins: $x10, $x11, $x12, $x16, $x17 + ; RV32_P-NEXT: {{ $}} + ; RV32_P-NEXT: $x14_x15 = PADD_DW $x16_x17, $x0_pair + ; RV32_P-NEXT: SD_RV32 $x14_x15, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; RV32_P-NEXT: SD_RV32 $x14_x15, killed renamable $x11, 0 :: (store (s64) into %ir.b) + ; RV32_P-NEXT: SD_RV32 killed $x14_x15, killed renamable $x12, 0 :: (store (s64) into %ir.c) + ; RV32_P-NEXT: PseudoRET + SD_RV32 renamable $x16_x17, killed renamable $x10, 0 :: (store (s64) into %ir.a) + SD_RV32 renamable $x16_x17, killed renamable $x11, 0 :: (store (s64) into %ir.b) + SD_RV32 killed renamable $x16_x17, killed renamable $x12, 0 :: (store (s64) into %ir.c) + PseudoRET + +... +--- +name: store_common_value_double_zero +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; RV32_NOP-LABEL: name: store_common_value_double_zero + ; RV32_NOP: liveins: $x10, $x11, $x12 + ; RV32_NOP-NEXT: {{ $}} + ; RV32_NOP-NEXT: $x14_x15 = FSGNJ_D_IN32X $x0_pair, $x0_pair + ; RV32_NOP-NEXT: SD_RV32 $x14_x15, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; RV32_NOP-NEXT: SD_RV32 $x14_x15, killed renamable $x11, 0 :: (store (s64) into %ir.b) + ; RV32_NOP-NEXT: SD_RV32 $x14_x15, killed renamable $x12, 0 :: (store (s64) into %ir.c) + ; RV32_NOP-NEXT: PseudoRET + ; + ; RV32_P-LABEL: name: store_common_value_double_zero + ; RV32_P: liveins: $x10, $x11, $x12 + ; RV32_P-NEXT: {{ $}} + ; RV32_P-NEXT: $x14_x15 = PADD_DW $x0_pair, $x0_pair + ; RV32_P-NEXT: SD_RV32 $x14_x15, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; RV32_P-NEXT: SD_RV32 $x14_x15, killed renamable $x11, 0 :: (store (s64) into %ir.b) + ; RV32_P-NEXT: SD_RV32 $x14_x15, killed renamable $x12, 0 :: (store (s64) into %ir.c) + ; RV32_P-NEXT: PseudoRET + SD_RV32 $x0_pair, killed renamable $x10, 0 :: (store (s64) into %ir.a) + SD_RV32 $x0_pair, killed renamable $x11, 0 :: (store (s64) into %ir.b) + SD_RV32 $x0_pair, killed renamable $x12, 0 :: (store (s64) into %ir.c) + PseudoRET + +... +--- +name: store_common_ptr_double +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16 + + ; RV32-LABEL: name: store_common_ptr_double + ; RV32: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: $x14 = ADDI $x16, 0 + ; RV32-NEXT: SD_RV32 killed renamable $x10_x11, $x14, 0 :: (volatile store (s64) into %ir.p) + ; RV32-NEXT: SD_RV32 renamable $x12_x13, $x14, 0 :: (volatile store (s64) into %ir.p) + ; RV32-NEXT: SD_RV32 killed renamable $x12_x13, killed $x14, 0 :: (volatile store (s64) into %ir.p) + ; RV32-NEXT: PseudoRET + SD_RV32 killed renamable $x10_x11, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + SD_RV32 renamable $x12_x13, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + SD_RV32 killed renamable $x12_x13, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + PseudoRET + +... +--- +name: load_common_ptr_double +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; RV32-LABEL: name: load_common_ptr_double + ; RV32: liveins: $x16 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: $x15 = ADDI $x16, 0 + ; RV32-NEXT: renamable $x10_x11 = LD_RV32 $x15, 0 :: (load (s64) from %ir.g) + ; RV32-NEXT: renamable $x12_x13 = LD_RV32 $x15, 8 :: (load (s64) from %ir.arrayidx1) + ; RV32-NEXT: renamable $x14 = LW killed $x15, 16 :: (load (s32) from %ir.arrayidx2, align 8) + ; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14 + renamable $x10_x11 = LD_RV32 renamable $x16, 0 :: (load (s64) from %ir.g) + renamable $x12_x13 = LD_RV32 renamable $x16, 8 :: (load (s64) from %ir.arrayidx1) + renamable $x14 = LW killed renamable $x16, 16 :: (load (s32) from %ir.arrayidx2, align 8) + PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14 + +... +--- +name: store_large_offset_double +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x12, $x13, $x14, $x15 + + ; RV32-LABEL: name: store_large_offset_double + ; RV32: liveins: $x10, $x12, $x13, $x14, $x15 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: $x11 = ADDI $x10, 768 + ; RV32-NEXT: SD_RV32 killed renamable $x12_x13, $x11, 32 :: (volatile store (s64) into %ir.0) + ; RV32-NEXT: SD_RV32 renamable $x14_x15, $x11, 40 :: (volatile store (s64) into %ir.1) + ; RV32-NEXT: SD_RV32 killed renamable $x14_x15, killed $x11, 48 :: (volatile store (s64) into %ir.2) + ; RV32-NEXT: PseudoRET + SD_RV32 killed renamable $x12_x13, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + SD_RV32 renamable $x14_x15, renamable $x10, 808 :: (volatile store (s64) into %ir.1) + SD_RV32 killed renamable $x14_x15, killed renamable $x10, 816 :: (volatile store (s64) into %ir.2) + PseudoRET + +... +--- +name: load_large_offset_double +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x14 + + ; RV32-LABEL: name: load_large_offset_double + ; RV32: liveins: $x14 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: $x15 = ADDI $x14, 768 + ; RV32-NEXT: renamable $x10_x11 = LD_RV32 $x15, 32 :: (load (s64) from %ir.arrayidx) + ; RV32-NEXT: renamable $x12_x13 = LD_RV32 $x15, 40 :: (load (s64) from %ir.arrayidx1) + ; RV32-NEXT: renamable $x14 = LW killed $x15, 48 :: (load (s32) from %ir.arrayidx2, align 8) + ; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14 + renamable $x10_x11 = LD_RV32 renamable $x14, 800 :: (load (s64) from %ir.arrayidx) + renamable $x12_x13 = LD_RV32 renamable $x14, 808 :: (load (s64) from %ir.arrayidx1) + renamable $x14 = LW killed renamable $x14, 816 :: (load (s32) from %ir.arrayidx2, align 8) + PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14 +... +--- +name: store_common_value_double_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x16, $x17 + + ; RV32-LABEL: name: store_common_value_double_no_opt + ; RV32: liveins: $x10, $x16, $x17 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; RV32-NEXT: PseudoRET + SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (store (s64) into %ir.a) + PseudoRET + +... +--- +name: store_common_value_double_no_opt2 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x16, $x17 + + ; RV32-LABEL: name: store_common_value_double_no_opt2 + ; RV32: liveins: $x10, $x16, $x17 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: SD_RV32 renamable $x16_x17, renamable $x10, 0 :: (volatile store (s64) into %ir.a) + ; RV32-NEXT: SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (volatile store (s64) into %ir.a) + ; RV32-NEXT: PseudoRET + SD_RV32 renamable $x16_x17, renamable $x10, 0 :: (volatile store (s64) into %ir.a) + SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (volatile store (s64) into %ir.a) + PseudoRET + +... +--- +name: store_common_ptr_double_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x16 + + ; RV32-LABEL: name: store_common_ptr_double_no_opt + ; RV32: liveins: $x10, $x11, $x16 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: SD_RV32 killed renamable $x10_x11, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; RV32-NEXT: PseudoRET + SD_RV32 killed renamable $x10_x11, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + PseudoRET + +... +--- +name: load_common_ptr_double_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; RV32-LABEL: name: load_common_ptr_double_no_opt + ; RV32: liveins: $x16 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: renamable $x10_x11 = LD_RV32 killed renamable $x16, 0 :: (load (s64) from %ir.g) + ; RV32-NEXT: PseudoRET implicit $x10, implicit $x11 + renamable $x10_x11 = LD_RV32 killed renamable $x16, 0 :: (load (s64) from %ir.g) + PseudoRET implicit $x10, implicit $x11 + +... +--- +name: store_large_offset_double_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12, $x13, $x14 + + ; RV32-LABEL: name: store_large_offset_double_no_opt + ; RV32: liveins: $x10, $x11, $x12, $x13, $x14 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: $x15 = ADDI $x14, 0 + ; RV32-NEXT: $x17 = ADDI $x12, 0 + ; RV32-NEXT: $x16 = ADDI $x11, 0 + ; RV32-NEXT: SD_RV32 killed renamable $x16_x17, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + ; RV32-NEXT: $x14 = ADDI $x13, 0 + ; RV32-NEXT: SD_RV32 killed renamable $x14_x15, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1) + ; RV32-NEXT: PseudoRET + $x15 = ADDI $x14, 0 + $x17 = ADDI $x12, 0 + $x16 = ADDI $x11, 0 + SD_RV32 killed renamable $x16_x17, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + $x14 = ADDI $x13, 0 + SD_RV32 killed renamable $x14_x15, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1) + PseudoRET + +... +--- +name: load_large_offset_double_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32-LABEL: name: load_large_offset_double_no_opt + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: renamable $x14_x15 = LD_RV32 renamable $x10, 800 :: (load (s64) from %ir.arrayidx) + ; RV32-NEXT: renamable $x12_x13 = LD_RV32 killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1) + ; RV32-NEXT: $x10 = ADDI renamable $x14, 0 + ; RV32-NEXT: $x11 = ADDI killed renamable $x15, 0 + ; RV32-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12, implicit $x13 + renamable $x14_x15 = LD_RV32 renamable $x10, 800 :: (load (s64) from %ir.arrayidx) + renamable $x12_x13 = LD_RV32 killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1) + $x10 = ADDI renamable $x14, 0 + $x11 = ADDI killed renamable $x15, 0 + PseudoRET implicit $x10, implicit $x11, implicit $x12, implicit $x13 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible.mir new file mode 100644 index 0000000..03da38a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/make-compressible.mir @@ -0,0 +1,1380 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+c,+f,+d -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32,RV32C %s +# RUN: llc -o - %s -mtriple=riscv64 -mattr=+c,+f,+d -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV64,RV64C %s +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+d,+zcf -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32,RV32ZCF %s +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+d,+zca -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32,RV32ZCA %s +# RUN: llc -o - %s -mtriple=riscv64 -mattr=+d,+zca -simplify-mir \ +# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV64,RV64ZCA %s +--- | + + define void @store_common_value(ptr %a, ptr %b, ptr %c) #0 { + entry: + store i32 0, ptr %a, align 4 + store i32 0, ptr %b, align 4 + store i32 0, ptr %c, align 4 + ret void + } + + define void @store_common_value_float(ptr %a, ptr %b, ptr %c, float %d, float %e, float %f, float %g, float %h, float %i, float %j) #0 { + entry: + store float %j, ptr %a, align 4 + store float %j, ptr %b, align 4 + store float %j, ptr %c, align 4 + ret void + } + + define void @store_common_value_double(ptr %a, ptr %b, ptr %c, double %d, double %e, double %f, double %g, double %h, double %i, double %j) #0 { + entry: + store double %j, ptr %a, align 8 + store double %j, ptr %b, align 8 + store double %j, ptr %c, align 8 + ret void + } + + define void @store_common_ptr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %p) #0 { + entry: + store volatile i32 1, ptr %p, align 4 + store volatile i32 3, ptr %p, align 4 + store volatile i32 5, ptr %p, align 4 + ret void + } + + define void @store_common_ptr_self(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %p) #0 { + entry: + %q = bitcast ptr %p to ptr + store volatile i32 1, ptr %p, align 4 + store volatile i32 3, ptr %p, align 4 + store volatile ptr %p, ptr %q, align 4 + ret void + } + + define void @store_common_ptr_float(float %a, float %b, float %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, ptr %p) #0 { + entry: + store volatile float %a, ptr %p, align 4 + store volatile float %b, ptr %p, align 4 + store volatile float %c, ptr %p, align 4 + ret void + } + + define void @store_common_ptr_double(double %a, double %b, double %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, ptr %p) #0 { + entry: + store volatile double %a, ptr %p, align 8 + store volatile double %b, ptr %p, align 8 + store volatile double %c, ptr %p, align 8 + ret void + } + + define void @load_common_ptr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %p) #0 { + entry: + %g = load volatile i32, ptr %p, align 4 + %h = load volatile i32, ptr %p, align 4 + %i = load volatile i32, ptr %p, align 4 + ret void + } + + define void @load_common_ptr_float(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) #0 { + entry: + %0 = load float, ptr %g, align 4 + %arrayidx1 = getelementptr inbounds float, ptr %g, i32 1 + %1 = load float, ptr %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds float, ptr %g, i32 2 + %2 = load float, ptr %arrayidx2, align 4 + tail call void @load_common_ptr_float_1(float %0, float %1, float %2) + ret void + } + + declare void @load_common_ptr_float_1(float, float, float) #0 + + define void @load_common_ptr_double(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) #0 { + entry: + %0 = load double, ptr %g, align 8 + %arrayidx1 = getelementptr inbounds double, ptr %g, i32 1 + %1 = load double, ptr %arrayidx1, align 8 + %arrayidx2 = getelementptr inbounds double, ptr %g, i32 2 + %2 = load double, ptr %arrayidx2, align 8 + tail call void @load_common_ptr_double_1(double %0, double %1, double %2) + ret void + } + + declare void @load_common_ptr_double_1(double, double, double) #0 + + define void @store_large_offset(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i32, ptr %p, i32 100 + store volatile i32 1, ptr %0, align 4 + %1 = getelementptr inbounds i32, ptr %p, i32 101 + store volatile i32 3, ptr %1, align 4 + %2 = getelementptr inbounds i32, ptr %p, i32 102 + store volatile i32 5, ptr %2, align 4 + %3 = getelementptr inbounds i32, ptr %p, i32 103 + store volatile i32 7, ptr %3, align 4 + ret void + } + + define void @store_large_offset_float(ptr %p, float %a, float %b, float %c, float %d) #0 { + entry: + %0 = getelementptr inbounds float, ptr %p, i32 100 + store volatile float %a, ptr %0, align 4 + %1 = getelementptr inbounds float, ptr %p, i32 101 + store volatile float %b, ptr %1, align 4 + %2 = getelementptr inbounds float, ptr %p, i32 102 + store volatile float %c, ptr %2, align 4 + %3 = getelementptr inbounds float, ptr %p, i32 103 + store volatile float %d, ptr %3, align 4 + ret void + } + + define void @store_large_offset_double(ptr %p, double %a, double %b, double %c, double %d) #0 { + entry: + %0 = getelementptr inbounds double, ptr %p, i32 100 + store volatile double %a, ptr %0, align 8 + %1 = getelementptr inbounds double, ptr %p, i32 101 + store volatile double %b, ptr %1, align 8 + %2 = getelementptr inbounds double, ptr %p, i32 102 + store volatile double %c, ptr %2, align 8 + %3 = getelementptr inbounds double, ptr %p, i32 103 + store volatile double %d, ptr %3, align 8 + ret void + } + + define void @load_large_offset(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i32, ptr %p, i32 100 + %a = load volatile i32, ptr %0, align 4 + %1 = getelementptr inbounds i32, ptr %p, i32 101 + %b = load volatile i32, ptr %1, align 4 + %2 = getelementptr inbounds i32, ptr %p, i32 102 + %c = load volatile i32, ptr %2, align 4 + %3 = getelementptr inbounds i32, ptr %p, i32 103 + %d = load volatile i32, ptr %3, align 4 + ret void + } + + define void @load_large_offset_float(ptr %p) #0 { + entry: + %arrayidx = getelementptr inbounds float, ptr %p, i32 100 + %0 = load float, ptr %arrayidx, align 4 + %arrayidx1 = getelementptr inbounds float, ptr %p, i32 101 + %1 = load float, ptr %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds float, ptr %p, i32 102 + %2 = load float, ptr %arrayidx2, align 4 + tail call void @load_large_offset_float_1(float %0, float %1, float %2) + ret void + } + + declare void @load_large_offset_float_1(float, float, float) #0 + + define void @load_large_offset_double(ptr %p) #0 { + entry: + %arrayidx = getelementptr inbounds double, ptr %p, i32 100 + %0 = load double, ptr %arrayidx, align 8 + %arrayidx1 = getelementptr inbounds double, ptr %p, i32 101 + %1 = load double, ptr %arrayidx1, align 8 + %arrayidx2 = getelementptr inbounds double, ptr %p, i32 102 + %2 = load double, ptr %arrayidx2, align 8 + tail call void @load_large_offset_double_1(double %0, double %1, double %2) + ret void + } + + declare void @load_large_offset_double_1(double, double, double) #0 + + define void @store_common_value_no_opt(ptr %a) #0 { + entry: + store i32 0, ptr %a, align 4 + ret void + } + + define void @store_common_value_float_no_opt(ptr %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h) #0 { + entry: + store float %h, ptr %a, align 4 + ret void + } + + define void @store_common_value_double_no_opt(ptr %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h) #0 { + entry: + store double %h, ptr %a, align 8 + ret void + } + + define void @store_common_ptr_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %p) #0 { + entry: + store volatile i32 1, ptr %p, align 4 + ret void + } + + define void @store_common_ptr_float_no_opt(float %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, ptr %p) #0 { + entry: + store volatile float %a, ptr %p, align 4 + ret void + } + + define void @store_common_ptr_double_no_opt(double %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, ptr %p) #0 { + entry: + store volatile double %a, ptr %p, align 8 + ret void + } + + define void @load_common_ptr_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %p) #0 { + entry: + %g = load volatile i32, ptr %p, align 4 + ret void + } + + define float @load_common_ptr_float_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) #0 { + entry: + %0 = load float, ptr %g, align 4 + ret float %0 + } + + define double @load_common_ptr_double_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) #0 { + entry: + %0 = load double, ptr %g, align 8 + ret double %0 + } + + define void @store_large_offset_no_opt(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i32, ptr %p, i32 100 + store volatile i32 1, ptr %0, align 4 + %1 = getelementptr inbounds i32, ptr %p, i32 101 + store volatile i32 3, ptr %1, align 4 + ret void + } + + define void @store_large_offset_float_no_opt(ptr %p, float %a, float %b) #0 { + entry: + %0 = getelementptr inbounds float, ptr %p, i32 100 + store volatile float %a, ptr %0, align 4 + %1 = getelementptr inbounds float, ptr %p, i32 101 + store volatile float %b, ptr %1, align 4 + ret void + } + + define void @store_large_offset_double_no_opt(ptr %p, double %a, double %b) #0 { + entry: + %0 = getelementptr inbounds double, ptr %p, i32 100 + store volatile double %a, ptr %0, align 8 + %1 = getelementptr inbounds double, ptr %p, i32 101 + store volatile double %b, ptr %1, align 8 + ret void + } + + define void @load_large_offset_no_opt(ptr %p) #0 { + entry: + %0 = getelementptr inbounds i32, ptr %p, i32 100 + %a = load volatile i32, ptr %0, align 4 + %1 = getelementptr inbounds i32, ptr %p, i32 101 + %b = load volatile i32, ptr %1, align 4 + ret void + } + + define { float, float } @load_large_offset_float_no_opt(ptr %p) #0 { + entry: + %arrayidx = getelementptr inbounds float, ptr %p, i32 100 + %0 = load float, ptr %arrayidx, align 4 + %arrayidx1 = getelementptr inbounds float, ptr %p, i32 101 + %1 = load float, ptr %arrayidx1, align 4 + %2 = insertvalue { float, float } undef, float %0, 0 + %3 = insertvalue { float, float } %2, float %1, 1 + ret { float, float } %3 + } + + define { double, double } @load_large_offset_double_no_opt(ptr %p) #0 { + entry: + %arrayidx = getelementptr inbounds double, ptr %p, i32 100 + %0 = load double, ptr %arrayidx, align 8 + %arrayidx1 = getelementptr inbounds double, ptr %p, i32 101 + %1 = load double, ptr %arrayidx1, align 8 + %2 = insertvalue { double, double } undef, double %0, 0 + %3 = insertvalue { double, double } %2, double %1, 1 + ret { double, double } %3 + } + + attributes #0 = { minsize } + +... +--- +name: store_common_value +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; RV32-LABEL: name: store_common_value + ; RV32: liveins: $x10, $x11, $x12 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: $x13 = ADDI $x0, 0 + ; RV32-NEXT: SW $x13, killed renamable $x10, 0 :: (store (s32) into %ir.a) + ; RV32-NEXT: SW $x13, killed renamable $x11, 0 :: (store (s32) into %ir.b) + ; RV32-NEXT: SW $x13, killed renamable $x12, 0 :: (store (s32) into %ir.c) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_common_value + ; RV64: liveins: $x10, $x11, $x12 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: $x13 = ADDI $x0, 0 + ; RV64-NEXT: SW $x13, killed renamable $x10, 0 :: (store (s32) into %ir.a) + ; RV64-NEXT: SW $x13, killed renamable $x11, 0 :: (store (s32) into %ir.b) + ; RV64-NEXT: SW $x13, killed renamable $x12, 0 :: (store (s32) into %ir.c) + ; RV64-NEXT: PseudoRET + SW $x0, killed renamable $x10, 0 :: (store (s32) into %ir.a) + SW $x0, killed renamable $x11, 0 :: (store (s32) into %ir.b) + SW $x0, killed renamable $x12, 0 :: (store (s32) into %ir.c) + PseudoRET + +... +--- +name: store_common_value_float +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12, $f16_f + + ; RV32C-LABEL: name: store_common_value_float + ; RV32C: liveins: $x10, $x11, $x12, $f16_f + ; RV32C-NEXT: {{ $}} + ; RV32C-NEXT: $f15_f = FSGNJ_S $f16_f, $f16_f + ; RV32C-NEXT: FSW $f15_f, killed renamable $x10, 0 :: (store (s32) into %ir.a) + ; RV32C-NEXT: FSW $f15_f, killed renamable $x11, 0 :: (store (s32) into %ir.b) + ; RV32C-NEXT: FSW killed $f15_f, killed renamable $x12, 0 :: (store (s32) into %ir.c) + ; RV32C-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_common_value_float + ; RV64: liveins: $x10, $x11, $x12, $f16_f + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: FSW renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a) + ; RV64-NEXT: FSW renamable $f16_f, killed renamable $x11, 0 :: (store (s32) into %ir.b) + ; RV64-NEXT: FSW killed renamable $f16_f, killed renamable $x12, 0 :: (store (s32) into %ir.c) + ; RV64-NEXT: PseudoRET + ; + ; RV32ZCF-LABEL: name: store_common_value_float + ; RV32ZCF: liveins: $x10, $x11, $x12, $f16_f + ; RV32ZCF-NEXT: {{ $}} + ; RV32ZCF-NEXT: $f15_f = FSGNJ_S $f16_f, $f16_f + ; RV32ZCF-NEXT: FSW $f15_f, killed renamable $x10, 0 :: (store (s32) into %ir.a) + ; RV32ZCF-NEXT: FSW $f15_f, killed renamable $x11, 0 :: (store (s32) into %ir.b) + ; RV32ZCF-NEXT: FSW killed $f15_f, killed renamable $x12, 0 :: (store (s32) into %ir.c) + ; RV32ZCF-NEXT: PseudoRET + ; + ; RV32ZCA-LABEL: name: store_common_value_float + ; RV32ZCA: liveins: $x10, $x11, $x12, $f16_f + ; RV32ZCA-NEXT: {{ $}} + ; RV32ZCA-NEXT: FSW renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a) + ; RV32ZCA-NEXT: FSW renamable $f16_f, killed renamable $x11, 0 :: (store (s32) into %ir.b) + ; RV32ZCA-NEXT: FSW killed renamable $f16_f, killed renamable $x12, 0 :: (store (s32) into %ir.c) + ; RV32ZCA-NEXT: PseudoRET + FSW renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a) + FSW renamable $f16_f, killed renamable $x11, 0 :: (store (s32) into %ir.b) + FSW killed renamable $f16_f, killed renamable $x12, 0 :: (store (s32) into %ir.c) + PseudoRET + +... +--- +name: store_common_value_double +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12, $f16_d + + ; RV32C-LABEL: name: store_common_value_double + ; RV32C: liveins: $x10, $x11, $x12, $f16_d + ; RV32C-NEXT: {{ $}} + ; RV32C-NEXT: $f15_d = FSGNJ_D $f16_d, $f16_d + ; RV32C-NEXT: FSD $f15_d, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; RV32C-NEXT: FSD $f15_d, killed renamable $x11, 0 :: (store (s64) into %ir.b) + ; RV32C-NEXT: FSD killed $f15_d, killed renamable $x12, 0 :: (store (s64) into %ir.c) + ; RV32C-NEXT: PseudoRET + ; + ; RV64C-LABEL: name: store_common_value_double + ; RV64C: liveins: $x10, $x11, $x12, $f16_d + ; RV64C-NEXT: {{ $}} + ; RV64C-NEXT: $f15_d = FSGNJ_D $f16_d, $f16_d + ; RV64C-NEXT: FSD $f15_d, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; RV64C-NEXT: FSD $f15_d, killed renamable $x11, 0 :: (store (s64) into %ir.b) + ; RV64C-NEXT: FSD killed $f15_d, killed renamable $x12, 0 :: (store (s64) into %ir.c) + ; RV64C-NEXT: PseudoRET + ; + ; RV32ZCF-LABEL: name: store_common_value_double + ; RV32ZCF: liveins: $x10, $x11, $x12, $f16_d + ; RV32ZCF-NEXT: {{ $}} + ; RV32ZCF-NEXT: FSD renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; RV32ZCF-NEXT: FSD renamable $f16_d, killed renamable $x11, 0 :: (store (s64) into %ir.b) + ; RV32ZCF-NEXT: FSD killed renamable $f16_d, killed renamable $x12, 0 :: (store (s64) into %ir.c) + ; RV32ZCF-NEXT: PseudoRET + ; + ; RV32ZCA-LABEL: name: store_common_value_double + ; RV32ZCA: liveins: $x10, $x11, $x12, $f16_d + ; RV32ZCA-NEXT: {{ $}} + ; RV32ZCA-NEXT: FSD renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; RV32ZCA-NEXT: FSD renamable $f16_d, killed renamable $x11, 0 :: (store (s64) into %ir.b) + ; RV32ZCA-NEXT: FSD killed renamable $f16_d, killed renamable $x12, 0 :: (store (s64) into %ir.c) + ; RV32ZCA-NEXT: PseudoRET + ; + ; RV64ZCA-LABEL: name: store_common_value_double + ; RV64ZCA: liveins: $x10, $x11, $x12, $f16_d + ; RV64ZCA-NEXT: {{ $}} + ; RV64ZCA-NEXT: FSD renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; RV64ZCA-NEXT: FSD renamable $f16_d, killed renamable $x11, 0 :: (store (s64) into %ir.b) + ; RV64ZCA-NEXT: FSD killed renamable $f16_d, killed renamable $x12, 0 :: (store (s64) into %ir.c) + ; RV64ZCA-NEXT: PseudoRET + FSD renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a) + FSD renamable $f16_d, killed renamable $x11, 0 :: (store (s64) into %ir.b) + FSD killed renamable $f16_d, killed renamable $x12, 0 :: (store (s64) into %ir.c) + PseudoRET + +... +--- +name: store_common_ptr +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; RV32-LABEL: name: store_common_ptr + ; RV32: liveins: $x16 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: renamable $x10 = ADDI $x0, 1 + ; RV32-NEXT: $x11 = ADDI $x16, 0 + ; RV32-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p) + ; RV32-NEXT: renamable $x10 = ADDI $x0, 3 + ; RV32-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p) + ; RV32-NEXT: renamable $x10 = ADDI $x0, 5 + ; RV32-NEXT: SW killed renamable $x10, killed $x11, 0 :: (volatile store (s32) into %ir.p) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_common_ptr + ; RV64: liveins: $x16 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: renamable $x10 = ADDI $x0, 1 + ; RV64-NEXT: $x11 = ADDI $x16, 0 + ; RV64-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p) + ; RV64-NEXT: renamable $x10 = ADDI $x0, 3 + ; RV64-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p) + ; RV64-NEXT: renamable $x10 = ADDI $x0, 5 + ; RV64-NEXT: SW killed renamable $x10, killed $x11, 0 :: (volatile store (s32) into %ir.p) + ; RV64-NEXT: PseudoRET + renamable $x10 = ADDI $x0, 1 + SW killed renamable $x10, renamable $x16, 0 :: (volatile store (s32) into %ir.p) + renamable $x10 = ADDI $x0, 3 + SW killed renamable $x10, renamable $x16, 0 :: (volatile store (s32) into %ir.p) + renamable $x10 = ADDI $x0, 5 + SW killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + PseudoRET + +... +--- +name: store_common_ptr_self +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; RV32-LABEL: name: store_common_ptr_self + ; RV32: liveins: $x16 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: renamable $x10 = ADDI $x0, 1 + ; RV32-NEXT: $x11 = ADDI $x16, 0 + ; RV32-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p) + ; RV32-NEXT: renamable $x10 = ADDI $x0, 3 + ; RV32-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p) + ; RV32-NEXT: SW killed $x11, $x11, 0 :: (volatile store (s32) into %ir.q) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_common_ptr_self + ; RV64: liveins: $x16 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: renamable $x10 = ADDI $x0, 1 + ; RV64-NEXT: $x11 = ADDI $x16, 0 + ; RV64-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p) + ; RV64-NEXT: renamable $x10 = ADDI $x0, 3 + ; RV64-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p) + ; RV64-NEXT: SW killed $x11, $x11, 0 :: (volatile store (s32) into %ir.q) + ; RV64-NEXT: PseudoRET + renamable $x10 = ADDI $x0, 1 + SW killed renamable $x10, renamable $x16, 0 :: (volatile store (s32) into %ir.p) + renamable $x10 = ADDI $x0, 3 + SW killed renamable $x10, renamable $x16, 0 :: (volatile store (s32) into %ir.p) + SW killed renamable $x16, renamable $x16, 0 :: (volatile store (s32) into %ir.q) + PseudoRET + +... +--- +name: store_common_ptr_float +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16, $f10_f, $f11_f, $f12_f + + ; RV32C-LABEL: name: store_common_ptr_float + ; RV32C: liveins: $x16, $f10_f, $f11_f, $f12_f + ; RV32C-NEXT: {{ $}} + ; RV32C-NEXT: $x10 = ADDI $x16, 0 + ; RV32C-NEXT: FSW killed renamable $f10_f, $x10, 0 :: (volatile store (s32) into %ir.p) + ; RV32C-NEXT: FSW killed renamable $f11_f, $x10, 0 :: (volatile store (s32) into %ir.p) + ; RV32C-NEXT: FSW killed renamable $f12_f, killed $x10, 0 :: (volatile store (s32) into %ir.p) + ; RV32C-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_common_ptr_float + ; RV64: liveins: $x16, $f10_f, $f11_f, $f12_f + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: FSW killed renamable $f10_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p) + ; RV64-NEXT: FSW killed renamable $f11_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p) + ; RV64-NEXT: FSW killed renamable $f12_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + ; RV64-NEXT: PseudoRET + ; + ; RV32ZCF-LABEL: name: store_common_ptr_float + ; RV32ZCF: liveins: $x16, $f10_f, $f11_f, $f12_f + ; RV32ZCF-NEXT: {{ $}} + ; RV32ZCF-NEXT: $x10 = ADDI $x16, 0 + ; RV32ZCF-NEXT: FSW killed renamable $f10_f, $x10, 0 :: (volatile store (s32) into %ir.p) + ; RV32ZCF-NEXT: FSW killed renamable $f11_f, $x10, 0 :: (volatile store (s32) into %ir.p) + ; RV32ZCF-NEXT: FSW killed renamable $f12_f, killed $x10, 0 :: (volatile store (s32) into %ir.p) + ; RV32ZCF-NEXT: PseudoRET + ; + ; RV32ZCA-LABEL: name: store_common_ptr_float + ; RV32ZCA: liveins: $x16, $f10_f, $f11_f, $f12_f + ; RV32ZCA-NEXT: {{ $}} + ; RV32ZCA-NEXT: FSW killed renamable $f10_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p) + ; RV32ZCA-NEXT: FSW killed renamable $f11_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p) + ; RV32ZCA-NEXT: FSW killed renamable $f12_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + ; RV32ZCA-NEXT: PseudoRET + FSW killed renamable $f10_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p) + FSW killed renamable $f11_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p) + FSW killed renamable $f12_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + PseudoRET + +... +--- +name: store_common_ptr_double +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16, $f10_d, $f11_d, $f12_d + + ; RV32C-LABEL: name: store_common_ptr_double + ; RV32C: liveins: $x16, $f10_d, $f11_d, $f12_d + ; RV32C-NEXT: {{ $}} + ; RV32C-NEXT: $x10 = ADDI $x16, 0 + ; RV32C-NEXT: FSD killed renamable $f10_d, $x10, 0 :: (volatile store (s64) into %ir.p) + ; RV32C-NEXT: FSD killed renamable $f11_d, $x10, 0 :: (volatile store (s64) into %ir.p) + ; RV32C-NEXT: FSD killed renamable $f12_d, killed $x10, 0 :: (volatile store (s64) into %ir.p) + ; RV32C-NEXT: PseudoRET + ; + ; RV64C-LABEL: name: store_common_ptr_double + ; RV64C: liveins: $x16, $f10_d, $f11_d, $f12_d + ; RV64C-NEXT: {{ $}} + ; RV64C-NEXT: $x10 = ADDI $x16, 0 + ; RV64C-NEXT: FSD killed renamable $f10_d, $x10, 0 :: (volatile store (s64) into %ir.p) + ; RV64C-NEXT: FSD killed renamable $f11_d, $x10, 0 :: (volatile store (s64) into %ir.p) + ; RV64C-NEXT: FSD killed renamable $f12_d, killed $x10, 0 :: (volatile store (s64) into %ir.p) + ; RV64C-NEXT: PseudoRET + ; + ; RV32ZCF-LABEL: name: store_common_ptr_double + ; RV32ZCF: liveins: $x16, $f10_d, $f11_d, $f12_d + ; RV32ZCF-NEXT: {{ $}} + ; RV32ZCF-NEXT: FSD killed renamable $f10_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; RV32ZCF-NEXT: FSD killed renamable $f11_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; RV32ZCF-NEXT: FSD killed renamable $f12_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; RV32ZCF-NEXT: PseudoRET + ; + ; RV32ZCA-LABEL: name: store_common_ptr_double + ; RV32ZCA: liveins: $x16, $f10_d, $f11_d, $f12_d + ; RV32ZCA-NEXT: {{ $}} + ; RV32ZCA-NEXT: FSD killed renamable $f10_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; RV32ZCA-NEXT: FSD killed renamable $f11_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; RV32ZCA-NEXT: FSD killed renamable $f12_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; RV32ZCA-NEXT: PseudoRET + ; + ; RV64ZCA-LABEL: name: store_common_ptr_double + ; RV64ZCA: liveins: $x16, $f10_d, $f11_d, $f12_d + ; RV64ZCA-NEXT: {{ $}} + ; RV64ZCA-NEXT: FSD killed renamable $f10_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; RV64ZCA-NEXT: FSD killed renamable $f11_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; RV64ZCA-NEXT: FSD killed renamable $f12_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; RV64ZCA-NEXT: PseudoRET + FSD killed renamable $f10_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + FSD killed renamable $f11_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p) + FSD killed renamable $f12_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + PseudoRET + +... +--- +name: load_common_ptr +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; RV32-LABEL: name: load_common_ptr + ; RV32: liveins: $x16 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: $x11 = ADDI $x16, 0 + ; RV32-NEXT: dead renamable $x10 = LW $x11, 0 :: (volatile load (s32) from %ir.p) + ; RV32-NEXT: dead renamable $x10 = LW $x11, 0 :: (volatile load (s32) from %ir.p) + ; RV32-NEXT: dead renamable $x10 = LW killed $x11, 0 :: (volatile load (s32) from %ir.p) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: load_common_ptr + ; RV64: liveins: $x16 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: $x11 = ADDI $x16, 0 + ; RV64-NEXT: dead renamable $x10 = LW $x11, 0 :: (volatile load (s32) from %ir.p) + ; RV64-NEXT: dead renamable $x10 = LW $x11, 0 :: (volatile load (s32) from %ir.p) + ; RV64-NEXT: dead renamable $x10 = LW killed $x11, 0 :: (volatile load (s32) from %ir.p) + ; RV64-NEXT: PseudoRET + dead renamable $x10 = LW renamable $x16, 0 :: (volatile load (s32) from %ir.p) + dead renamable $x10 = LW renamable $x16, 0 :: (volatile load (s32) from %ir.p) + dead renamable $x10 = LW killed renamable $x16, 0 :: (volatile load (s32) from %ir.p) + PseudoRET + +... +--- +name: load_common_ptr_float +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; RV32C-LABEL: name: load_common_ptr_float + ; RV32C: liveins: $x16 + ; RV32C-NEXT: {{ $}} + ; RV32C-NEXT: $x10 = ADDI $x16, 0 + ; RV32C-NEXT: renamable $f10_f = FLW $x10, 0 :: (load (s32) from %ir.g) + ; RV32C-NEXT: renamable $f11_f = FLW $x10, 4 :: (load (s32) from %ir.arrayidx1) + ; RV32C-NEXT: renamable $f12_f = FLW killed $x10, 8 :: (load (s32) from %ir.arrayidx2) + ; RV32C-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + ; + ; RV64-LABEL: name: load_common_ptr_float + ; RV64: liveins: $x16 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: renamable $f10_f = FLW renamable $x16, 0 :: (load (s32) from %ir.g) + ; RV64-NEXT: renamable $f11_f = FLW renamable $x16, 4 :: (load (s32) from %ir.arrayidx1) + ; RV64-NEXT: renamable $f12_f = FLW killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2) + ; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + ; + ; RV32ZCF-LABEL: name: load_common_ptr_float + ; RV32ZCF: liveins: $x16 + ; RV32ZCF-NEXT: {{ $}} + ; RV32ZCF-NEXT: $x10 = ADDI $x16, 0 + ; RV32ZCF-NEXT: renamable $f10_f = FLW $x10, 0 :: (load (s32) from %ir.g) + ; RV32ZCF-NEXT: renamable $f11_f = FLW $x10, 4 :: (load (s32) from %ir.arrayidx1) + ; RV32ZCF-NEXT: renamable $f12_f = FLW killed $x10, 8 :: (load (s32) from %ir.arrayidx2) + ; RV32ZCF-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + ; + ; RV32ZCA-LABEL: name: load_common_ptr_float + ; RV32ZCA: liveins: $x16 + ; RV32ZCA-NEXT: {{ $}} + ; RV32ZCA-NEXT: renamable $f10_f = FLW renamable $x16, 0 :: (load (s32) from %ir.g) + ; RV32ZCA-NEXT: renamable $f11_f = FLW renamable $x16, 4 :: (load (s32) from %ir.arrayidx1) + ; RV32ZCA-NEXT: renamable $f12_f = FLW killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2) + ; RV32ZCA-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + renamable $f10_f = FLW renamable $x16, 0 :: (load (s32) from %ir.g) + renamable $f11_f = FLW renamable $x16, 4 :: (load (s32) from %ir.arrayidx1) + renamable $f12_f = FLW killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2) + PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + +... +--- +name: load_common_ptr_double +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; RV32C-LABEL: name: load_common_ptr_double + ; RV32C: liveins: $x16 + ; RV32C-NEXT: {{ $}} + ; RV32C-NEXT: $x10 = ADDI $x16, 0 + ; RV32C-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g) + ; RV32C-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1) + ; RV32C-NEXT: renamable $f12_d = FLD killed $x10, 16 :: (load (s64) from %ir.arrayidx2) + ; RV32C-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + ; + ; RV64C-LABEL: name: load_common_ptr_double + ; RV64C: liveins: $x16 + ; RV64C-NEXT: {{ $}} + ; RV64C-NEXT: $x10 = ADDI $x16, 0 + ; RV64C-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g) + ; RV64C-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1) + ; RV64C-NEXT: renamable $f12_d = FLD killed $x10, 16 :: (load (s64) from %ir.arrayidx2) + ; RV64C-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + ; + ; RV32ZCF-LABEL: name: load_common_ptr_double + ; RV32ZCF: liveins: $x16 + ; RV32ZCF-NEXT: {{ $}} + ; RV32ZCF-NEXT: renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g) + ; RV32ZCF-NEXT: renamable $f11_d = FLD renamable $x16, 8 :: (load (s64) from %ir.arrayidx1) + ; RV32ZCF-NEXT: renamable $f12_d = FLD killed renamable $x16, 16 :: (load (s64) from %ir.arrayidx2) + ; RV32ZCF-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + ; + ; RV32ZCA-LABEL: name: load_common_ptr_double + ; RV32ZCA: liveins: $x16 + ; RV32ZCA-NEXT: {{ $}} + ; RV32ZCA-NEXT: renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g) + ; RV32ZCA-NEXT: renamable $f11_d = FLD renamable $x16, 8 :: (load (s64) from %ir.arrayidx1) + ; RV32ZCA-NEXT: renamable $f12_d = FLD killed renamable $x16, 16 :: (load (s64) from %ir.arrayidx2) + ; RV32ZCA-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + ; + ; RV64ZCA-LABEL: name: load_common_ptr_double + ; RV64ZCA: liveins: $x16 + ; RV64ZCA-NEXT: {{ $}} + ; RV64ZCA-NEXT: renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g) + ; RV64ZCA-NEXT: renamable $f11_d = FLD renamable $x16, 8 :: (load (s64) from %ir.arrayidx1) + ; RV64ZCA-NEXT: renamable $f12_d = FLD killed renamable $x16, 16 :: (load (s64) from %ir.arrayidx2) + ; RV64ZCA-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g) + renamable $f11_d = FLD renamable $x16, 8 :: (load (s64) from %ir.arrayidx1) + renamable $f12_d = FLD killed renamable $x16, 16 :: (load (s64) from %ir.arrayidx2) + PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + +... +--- +name: store_large_offset +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32-LABEL: name: store_large_offset + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32-NEXT: $x12 = ADDI $x10, 384 + ; RV32-NEXT: SW killed renamable $x11, $x12, 16 :: (volatile store (s32) into %ir.0) + ; RV32-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32-NEXT: SW killed renamable $x11, $x12, 20 :: (volatile store (s32) into %ir.1) + ; RV32-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV32-NEXT: SW killed renamable $x11, $x12, 24 :: (volatile store (s32) into %ir.2) + ; RV32-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV32-NEXT: SW killed renamable $x11, killed $x12, 28 :: (volatile store (s32) into %ir.3) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_large_offset + ; RV64: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV64-NEXT: $x12 = ADDI $x10, 384 + ; RV64-NEXT: SW killed renamable $x11, $x12, 16 :: (volatile store (s32) into %ir.0) + ; RV64-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV64-NEXT: SW killed renamable $x11, $x12, 20 :: (volatile store (s32) into %ir.1) + ; RV64-NEXT: renamable $x11 = ADDI $x0, 5 + ; RV64-NEXT: SW killed renamable $x11, $x12, 24 :: (volatile store (s32) into %ir.2) + ; RV64-NEXT: renamable $x11 = ADDI $x0, 7 + ; RV64-NEXT: SW killed renamable $x11, killed $x12, 28 :: (volatile store (s32) into %ir.3) + ; RV64-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + SW killed renamable $x11, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + renamable $x11 = ADDI $x0, 3 + SW killed renamable $x11, renamable $x10, 404 :: (volatile store (s32) into %ir.1) + renamable $x11 = ADDI $x0, 5 + SW killed renamable $x11, renamable $x10, 408 :: (volatile store (s32) into %ir.2) + renamable $x11 = ADDI $x0, 7 + SW killed renamable $x11, killed renamable $x10, 412 :: (volatile store (s32) into %ir.3) + PseudoRET + +... +--- +name: store_large_offset_float +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f + + ; RV32C-LABEL: name: store_large_offset_float + ; RV32C: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f + ; RV32C-NEXT: {{ $}} + ; RV32C-NEXT: $x11 = ADDI $x10, 384 + ; RV32C-NEXT: FSW killed renamable $f10_f, $x11, 16 :: (volatile store (s32) into %ir.0) + ; RV32C-NEXT: FSW killed renamable $f11_f, $x11, 20 :: (volatile store (s32) into %ir.1) + ; RV32C-NEXT: FSW killed renamable $f12_f, $x11, 24 :: (volatile store (s32) into %ir.2) + ; RV32C-NEXT: FSW killed renamable $f13_f, killed $x11, 28 :: (volatile store (s32) into %ir.3) + ; RV32C-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_large_offset_float + ; RV64: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + ; RV64-NEXT: FSW killed renamable $f11_f, renamable $x10, 404 :: (volatile store (s32) into %ir.1) + ; RV64-NEXT: FSW killed renamable $f12_f, renamable $x10, 408 :: (volatile store (s32) into %ir.2) + ; RV64-NEXT: FSW killed renamable $f13_f, killed renamable $x10, 412 :: (volatile store (s32) into %ir.3) + ; RV64-NEXT: PseudoRET + ; + ; RV32ZCF-LABEL: name: store_large_offset_float + ; RV32ZCF: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f + ; RV32ZCF-NEXT: {{ $}} + ; RV32ZCF-NEXT: $x11 = ADDI $x10, 384 + ; RV32ZCF-NEXT: FSW killed renamable $f10_f, $x11, 16 :: (volatile store (s32) into %ir.0) + ; RV32ZCF-NEXT: FSW killed renamable $f11_f, $x11, 20 :: (volatile store (s32) into %ir.1) + ; RV32ZCF-NEXT: FSW killed renamable $f12_f, $x11, 24 :: (volatile store (s32) into %ir.2) + ; RV32ZCF-NEXT: FSW killed renamable $f13_f, killed $x11, 28 :: (volatile store (s32) into %ir.3) + ; RV32ZCF-NEXT: PseudoRET + ; + ; RV32ZCA-LABEL: name: store_large_offset_float + ; RV32ZCA: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f + ; RV32ZCA-NEXT: {{ $}} + ; RV32ZCA-NEXT: FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + ; RV32ZCA-NEXT: FSW killed renamable $f11_f, renamable $x10, 404 :: (volatile store (s32) into %ir.1) + ; RV32ZCA-NEXT: FSW killed renamable $f12_f, renamable $x10, 408 :: (volatile store (s32) into %ir.2) + ; RV32ZCA-NEXT: FSW killed renamable $f13_f, killed renamable $x10, 412 :: (volatile store (s32) into %ir.3) + ; RV32ZCA-NEXT: PseudoRET + FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + FSW killed renamable $f11_f, renamable $x10, 404 :: (volatile store (s32) into %ir.1) + FSW killed renamable $f12_f, renamable $x10, 408 :: (volatile store (s32) into %ir.2) + FSW killed renamable $f13_f, killed renamable $x10, 412 :: (volatile store (s32) into %ir.3) + PseudoRET + +... +--- +name: store_large_offset_double +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d + + ; RV32C-LABEL: name: store_large_offset_double + ; RV32C: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d + ; RV32C-NEXT: {{ $}} + ; RV32C-NEXT: $x11 = ADDI $x10, 768 + ; RV32C-NEXT: FSD killed renamable $f10_d, $x11, 32 :: (volatile store (s64) into %ir.0) + ; RV32C-NEXT: FSD killed renamable $f11_d, $x11, 40 :: (volatile store (s64) into %ir.1) + ; RV32C-NEXT: FSD killed renamable $f12_d, $x11, 48 :: (volatile store (s64) into %ir.2) + ; RV32C-NEXT: FSD killed renamable $f13_d, killed $x11, 56 :: (volatile store (s64) into %ir.3) + ; RV32C-NEXT: PseudoRET + ; + ; RV64C-LABEL: name: store_large_offset_double + ; RV64C: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d + ; RV64C-NEXT: {{ $}} + ; RV64C-NEXT: $x11 = ADDI $x10, 768 + ; RV64C-NEXT: FSD killed renamable $f10_d, $x11, 32 :: (volatile store (s64) into %ir.0) + ; RV64C-NEXT: FSD killed renamable $f11_d, $x11, 40 :: (volatile store (s64) into %ir.1) + ; RV64C-NEXT: FSD killed renamable $f12_d, $x11, 48 :: (volatile store (s64) into %ir.2) + ; RV64C-NEXT: FSD killed renamable $f13_d, killed $x11, 56 :: (volatile store (s64) into %ir.3) + ; RV64C-NEXT: PseudoRET + ; + ; RV32ZCF-LABEL: name: store_large_offset_double + ; RV32ZCF: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d + ; RV32ZCF-NEXT: {{ $}} + ; RV32ZCF-NEXT: FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + ; RV32ZCF-NEXT: FSD killed renamable $f11_d, renamable $x10, 808 :: (volatile store (s64) into %ir.1) + ; RV32ZCF-NEXT: FSD killed renamable $f12_d, renamable $x10, 816 :: (volatile store (s64) into %ir.2) + ; RV32ZCF-NEXT: FSD killed renamable $f13_d, killed renamable $x10, 824 :: (volatile store (s64) into %ir.3) + ; RV32ZCF-NEXT: PseudoRET + ; + ; RV32ZCA-LABEL: name: store_large_offset_double + ; RV32ZCA: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d + ; RV32ZCA-NEXT: {{ $}} + ; RV32ZCA-NEXT: FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + ; RV32ZCA-NEXT: FSD killed renamable $f11_d, renamable $x10, 808 :: (volatile store (s64) into %ir.1) + ; RV32ZCA-NEXT: FSD killed renamable $f12_d, renamable $x10, 816 :: (volatile store (s64) into %ir.2) + ; RV32ZCA-NEXT: FSD killed renamable $f13_d, killed renamable $x10, 824 :: (volatile store (s64) into %ir.3) + ; RV32ZCA-NEXT: PseudoRET + ; + ; RV64ZCA-LABEL: name: store_large_offset_double + ; RV64ZCA: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d + ; RV64ZCA-NEXT: {{ $}} + ; RV64ZCA-NEXT: FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + ; RV64ZCA-NEXT: FSD killed renamable $f11_d, renamable $x10, 808 :: (volatile store (s64) into %ir.1) + ; RV64ZCA-NEXT: FSD killed renamable $f12_d, renamable $x10, 816 :: (volatile store (s64) into %ir.2) + ; RV64ZCA-NEXT: FSD killed renamable $f13_d, killed renamable $x10, 824 :: (volatile store (s64) into %ir.3) + ; RV64ZCA-NEXT: PseudoRET + FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + FSD killed renamable $f11_d, renamable $x10, 808 :: (volatile store (s64) into %ir.1) + FSD killed renamable $f12_d, renamable $x10, 816 :: (volatile store (s64) into %ir.2) + FSD killed renamable $f13_d, killed renamable $x10, 824 :: (volatile store (s64) into %ir.3) + PseudoRET + +... +--- +name: load_large_offset +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32-LABEL: name: load_large_offset + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: $x12 = ADDI $x10, 384 + ; RV32-NEXT: dead renamable $x11 = LW $x12, 16 :: (volatile load (s32) from %ir.0) + ; RV32-NEXT: dead renamable $x11 = LW $x12, 20 :: (volatile load (s32) from %ir.1) + ; RV32-NEXT: dead renamable $x11 = LW $x12, 24 :: (volatile load (s32) from %ir.2) + ; RV32-NEXT: dead renamable $x10 = LW killed $x12, 28 :: (volatile load (s32) from %ir.3) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: load_large_offset + ; RV64: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: $x12 = ADDI $x10, 384 + ; RV64-NEXT: dead renamable $x11 = LW $x12, 16 :: (volatile load (s32) from %ir.0) + ; RV64-NEXT: dead renamable $x11 = LW $x12, 20 :: (volatile load (s32) from %ir.1) + ; RV64-NEXT: dead renamable $x11 = LW $x12, 24 :: (volatile load (s32) from %ir.2) + ; RV64-NEXT: dead renamable $x10 = LW killed $x12, 28 :: (volatile load (s32) from %ir.3) + ; RV64-NEXT: PseudoRET + dead renamable $x11 = LW renamable $x10, 400 :: (volatile load (s32) from %ir.0) + dead renamable $x11 = LW renamable $x10, 404 :: (volatile load (s32) from %ir.1) + dead renamable $x11 = LW renamable $x10, 408 :: (volatile load (s32) from %ir.2) + dead renamable $x10 = LW killed renamable $x10, 412 :: (volatile load (s32) from %ir.3) + PseudoRET + +... +--- +name: load_large_offset_float +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32C-LABEL: name: load_large_offset_float + ; RV32C: liveins: $x10 + ; RV32C-NEXT: {{ $}} + ; RV32C-NEXT: $x11 = ADDI $x10, 384 + ; RV32C-NEXT: renamable $f10_f = FLW $x11, 16 :: (load (s32) from %ir.arrayidx) + ; RV32C-NEXT: renamable $f11_f = FLW $x11, 20 :: (load (s32) from %ir.arrayidx1) + ; RV32C-NEXT: renamable $f12_f = FLW killed $x11, 24 :: (load (s32) from %ir.arrayidx2) + ; RV32C-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + ; + ; RV64-LABEL: name: load_large_offset_float + ; RV64: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx) + ; RV64-NEXT: renamable $f11_f = FLW renamable $x10, 404 :: (load (s32) from %ir.arrayidx1) + ; RV64-NEXT: renamable $f12_f = FLW killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2) + ; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + ; + ; RV32ZCF-LABEL: name: load_large_offset_float + ; RV32ZCF: liveins: $x10 + ; RV32ZCF-NEXT: {{ $}} + ; RV32ZCF-NEXT: $x11 = ADDI $x10, 384 + ; RV32ZCF-NEXT: renamable $f10_f = FLW $x11, 16 :: (load (s32) from %ir.arrayidx) + ; RV32ZCF-NEXT: renamable $f11_f = FLW $x11, 20 :: (load (s32) from %ir.arrayidx1) + ; RV32ZCF-NEXT: renamable $f12_f = FLW killed $x11, 24 :: (load (s32) from %ir.arrayidx2) + ; RV32ZCF-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + ; + ; RV32ZCA-LABEL: name: load_large_offset_float + ; RV32ZCA: liveins: $x10 + ; RV32ZCA-NEXT: {{ $}} + ; RV32ZCA-NEXT: renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx) + ; RV32ZCA-NEXT: renamable $f11_f = FLW renamable $x10, 404 :: (load (s32) from %ir.arrayidx1) + ; RV32ZCA-NEXT: renamable $f12_f = FLW killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2) + ; RV32ZCA-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx) + renamable $f11_f = FLW renamable $x10, 404 :: (load (s32) from %ir.arrayidx1) + renamable $f12_f = FLW killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2) + PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f + +... +--- +name: load_large_offset_double +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32C-LABEL: name: load_large_offset_double + ; RV32C: liveins: $x10 + ; RV32C-NEXT: {{ $}} + ; RV32C-NEXT: $x11 = ADDI $x10, 768 + ; RV32C-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx) + ; RV32C-NEXT: renamable $f11_d = FLD $x11, 40 :: (load (s64) from %ir.arrayidx1) + ; RV32C-NEXT: renamable $f12_d = FLD killed $x11, 48 :: (load (s64) from %ir.arrayidx2) + ; RV32C-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + ; + ; RV64C-LABEL: name: load_large_offset_double + ; RV64C: liveins: $x10 + ; RV64C-NEXT: {{ $}} + ; RV64C-NEXT: $x11 = ADDI $x10, 768 + ; RV64C-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx) + ; RV64C-NEXT: renamable $f11_d = FLD $x11, 40 :: (load (s64) from %ir.arrayidx1) + ; RV64C-NEXT: renamable $f12_d = FLD killed $x11, 48 :: (load (s64) from %ir.arrayidx2) + ; RV64C-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + ; + ; RV32ZCF-LABEL: name: load_large_offset_double + ; RV32ZCF: liveins: $x10 + ; RV32ZCF-NEXT: {{ $}} + ; RV32ZCF-NEXT: renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx) + ; RV32ZCF-NEXT: renamable $f11_d = FLD renamable $x10, 808 :: (load (s64) from %ir.arrayidx1) + ; RV32ZCF-NEXT: renamable $f12_d = FLD killed renamable $x10, 816 :: (load (s64) from %ir.arrayidx2) + ; RV32ZCF-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + ; + ; RV32ZCA-LABEL: name: load_large_offset_double + ; RV32ZCA: liveins: $x10 + ; RV32ZCA-NEXT: {{ $}} + ; RV32ZCA-NEXT: renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx) + ; RV32ZCA-NEXT: renamable $f11_d = FLD renamable $x10, 808 :: (load (s64) from %ir.arrayidx1) + ; RV32ZCA-NEXT: renamable $f12_d = FLD killed renamable $x10, 816 :: (load (s64) from %ir.arrayidx2) + ; RV32ZCA-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + ; + ; RV64ZCA-LABEL: name: load_large_offset_double + ; RV64ZCA: liveins: $x10 + ; RV64ZCA-NEXT: {{ $}} + ; RV64ZCA-NEXT: renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx) + ; RV64ZCA-NEXT: renamable $f11_d = FLD renamable $x10, 808 :: (load (s64) from %ir.arrayidx1) + ; RV64ZCA-NEXT: renamable $f12_d = FLD killed renamable $x10, 816 :: (load (s64) from %ir.arrayidx2) + ; RV64ZCA-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx) + renamable $f11_d = FLD renamable $x10, 808 :: (load (s64) from %ir.arrayidx1) + renamable $f12_d = FLD killed renamable $x10, 816 :: (load (s64) from %ir.arrayidx2) + PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d + +... +--- +name: store_common_value_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32-LABEL: name: store_common_value_no_opt + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: SW $x0, killed renamable $x10, 0 :: (store (s32) into %ir.a) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_common_value_no_opt + ; RV64: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: SW $x0, killed renamable $x10, 0 :: (store (s32) into %ir.a) + ; RV64-NEXT: PseudoRET + SW $x0, killed renamable $x10, 0 :: (store (s32) into %ir.a) + PseudoRET + +... +--- +name: store_common_value_float_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f16_f + + ; RV32-LABEL: name: store_common_value_float_no_opt + ; RV32: liveins: $x10, $f16_f + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: FSW killed renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_common_value_float_no_opt + ; RV64: liveins: $x10, $f16_f + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: FSW killed renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a) + ; RV64-NEXT: PseudoRET + FSW killed renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a) + PseudoRET + +... +--- +name: store_common_value_double_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f16_d + + ; RV32-LABEL: name: store_common_value_double_no_opt + ; RV32: liveins: $x10, $f16_d + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: FSD killed renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_common_value_double_no_opt + ; RV64: liveins: $x10, $f16_d + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: FSD killed renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a) + ; RV64-NEXT: PseudoRET + FSD killed renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a) + PseudoRET + +... +--- +name: store_common_ptr_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; RV32-LABEL: name: store_common_ptr_no_opt + ; RV32: liveins: $x16 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: renamable $x10 = ADDI $x0, 1 + ; RV32-NEXT: SW killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_common_ptr_no_opt + ; RV64: liveins: $x16 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: renamable $x10 = ADDI $x0, 1 + ; RV64-NEXT: SW killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + ; RV64-NEXT: PseudoRET + renamable $x10 = ADDI $x0, 1 + SW killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + PseudoRET + +... +--- +name: store_common_ptr_float_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16, $f10_f + + ; RV32-LABEL: name: store_common_ptr_float_no_opt + ; RV32: liveins: $x16, $f10_f + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: FSW killed renamable $f10_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_common_ptr_float_no_opt + ; RV64: liveins: $x16, $f10_f + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: FSW killed renamable $f10_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + ; RV64-NEXT: PseudoRET + FSW killed renamable $f10_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p) + PseudoRET + +... +--- +name: store_common_ptr_double_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16, $f10_d + + ; RV32-LABEL: name: store_common_ptr_double_no_opt + ; RV32: liveins: $x16, $f10_d + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: FSD killed renamable $f10_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_common_ptr_double_no_opt + ; RV64: liveins: $x16, $f10_d + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: FSD killed renamable $f10_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + ; RV64-NEXT: PseudoRET + FSD killed renamable $f10_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p) + PseudoRET + +... +--- +name: load_common_ptr_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; RV32-LABEL: name: load_common_ptr_no_opt + ; RV32: liveins: $x16 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: dead renamable $x10 = LW killed renamable $x16, 0 :: (volatile load (s32) from %ir.p) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: load_common_ptr_no_opt + ; RV64: liveins: $x16 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: dead renamable $x10 = LW killed renamable $x16, 0 :: (volatile load (s32) from %ir.p) + ; RV64-NEXT: PseudoRET + dead renamable $x10 = LW killed renamable $x16, 0 :: (volatile load (s32) from %ir.p) + PseudoRET + +... +--- +name: load_common_ptr_float_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; RV32-LABEL: name: load_common_ptr_float_no_opt + ; RV32: liveins: $x16 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: renamable $f10_f = FLW killed renamable $x16, 0 :: (load (s32) from %ir.g) + ; RV32-NEXT: PseudoRET implicit $f10_f + ; + ; RV64-LABEL: name: load_common_ptr_float_no_opt + ; RV64: liveins: $x16 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: renamable $f10_f = FLW killed renamable $x16, 0 :: (load (s32) from %ir.g) + ; RV64-NEXT: PseudoRET implicit $f10_f + renamable $f10_f = FLW killed renamable $x16, 0 :: (load (s32) from %ir.g) + PseudoRET implicit $f10_f + +... +--- +name: load_common_ptr_double_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x16 + + ; RV32-LABEL: name: load_common_ptr_double_no_opt + ; RV32: liveins: $x16 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: renamable $f10_d = FLD killed renamable $x16, 0 :: (load (s64) from %ir.g) + ; RV32-NEXT: PseudoRET implicit $f10_d + ; + ; RV64-LABEL: name: load_common_ptr_double_no_opt + ; RV64: liveins: $x16 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: renamable $f10_d = FLD killed renamable $x16, 0 :: (load (s64) from %ir.g) + ; RV64-NEXT: PseudoRET implicit $f10_d + renamable $f10_d = FLD killed renamable $x16, 0 :: (load (s64) from %ir.g) + PseudoRET implicit $f10_d + +... +--- +name: store_large_offset_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32-LABEL: name: store_large_offset_no_opt + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV32-NEXT: SW killed renamable $x11, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + ; RV32-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV32-NEXT: SW killed renamable $x11, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_large_offset_no_opt + ; RV64: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: renamable $x11 = ADDI $x0, 1 + ; RV64-NEXT: SW killed renamable $x11, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + ; RV64-NEXT: renamable $x11 = ADDI $x0, 3 + ; RV64-NEXT: SW killed renamable $x11, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1) + ; RV64-NEXT: PseudoRET + renamable $x11 = ADDI $x0, 1 + SW killed renamable $x11, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + renamable $x11 = ADDI $x0, 3 + SW killed renamable $x11, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1) + PseudoRET + +... +--- +name: store_large_offset_float_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_f, $f11_f + + ; RV32-LABEL: name: store_large_offset_float_no_opt + ; RV32: liveins: $x10, $f10_f, $f11_f + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + ; RV32-NEXT: FSW killed renamable $f11_f, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_large_offset_float_no_opt + ; RV64: liveins: $x10, $f10_f, $f11_f + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + ; RV64-NEXT: FSW killed renamable $f11_f, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1) + ; RV64-NEXT: PseudoRET + FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0) + FSW killed renamable $f11_f, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1) + PseudoRET + +... +--- +name: store_large_offset_double_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $f10_d, $f11_d + + ; RV32-LABEL: name: store_large_offset_double_no_opt + ; RV32: liveins: $x10, $f10_d, $f11_d + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + ; RV32-NEXT: FSD killed renamable $f11_d, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: store_large_offset_double_no_opt + ; RV64: liveins: $x10, $f10_d, $f11_d + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + ; RV64-NEXT: FSD killed renamable $f11_d, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1) + ; RV64-NEXT: PseudoRET + FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0) + FSD killed renamable $f11_d, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1) + PseudoRET + +... +--- +name: load_large_offset_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32-LABEL: name: load_large_offset_no_opt + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: dead renamable $x11 = LW renamable $x10, 400 :: (volatile load (s32) from %ir.0) + ; RV32-NEXT: dead renamable $x10 = LW killed renamable $x10, 404 :: (volatile load (s32) from %ir.1) + ; RV32-NEXT: PseudoRET + ; + ; RV64-LABEL: name: load_large_offset_no_opt + ; RV64: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: dead renamable $x11 = LW renamable $x10, 400 :: (volatile load (s32) from %ir.0) + ; RV64-NEXT: dead renamable $x10 = LW killed renamable $x10, 404 :: (volatile load (s32) from %ir.1) + ; RV64-NEXT: PseudoRET + dead renamable $x11 = LW renamable $x10, 400 :: (volatile load (s32) from %ir.0) + dead renamable $x10 = LW killed renamable $x10, 404 :: (volatile load (s32) from %ir.1) + PseudoRET + +... +--- +name: load_large_offset_float_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32-LABEL: name: load_large_offset_float_no_opt + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx) + ; RV32-NEXT: renamable $f11_f = FLW killed renamable $x10, 404 :: (load (s32) from %ir.arrayidx1) + ; RV32-NEXT: PseudoRET implicit $f10_f, implicit $f11_f + ; + ; RV64-LABEL: name: load_large_offset_float_no_opt + ; RV64: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx) + ; RV64-NEXT: renamable $f11_f = FLW killed renamable $x10, 404 :: (load (s32) from %ir.arrayidx1) + ; RV64-NEXT: PseudoRET implicit $f10_f, implicit $f11_f + renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx) + renamable $f11_f = FLW killed renamable $x10, 404 :: (load (s32) from %ir.arrayidx1) + PseudoRET implicit $f10_f, implicit $f11_f + +... +--- +name: load_large_offset_double_no_opt +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32-LABEL: name: load_large_offset_double_no_opt + ; RV32: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx) + ; RV32-NEXT: renamable $f11_d = FLD killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1) + ; RV32-NEXT: PseudoRET implicit $f10_d, implicit $f11_d + ; + ; RV64-LABEL: name: load_large_offset_double_no_opt + ; RV64: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx) + ; RV64-NEXT: renamable $f11_d = FLD killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1) + ; RV64-NEXT: PseudoRET implicit $f10_d, implicit $f11_d + renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx) + renamable $f11_d = FLD killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1) + PseudoRET implicit $f10_d, implicit $f11_d + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/misched-mem-clustering.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/misched-mem-clustering.mir new file mode 100644 index 0000000..01960f9 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/misched-mem-clustering.mir @@ -0,0 +1,89 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -x mir -mcpu=sifive-p470 -verify-misched -enable-post-misched=false \ +# RUN: -mattr=+disable-postmisched-load-clustering \ +# RUN: -mattr=+disable-postmisched-store-clustering -debug-only=machine-scheduler \ +# RUN: -start-before=machine-scheduler -stop-after=postmisched -misched-regpressure=false -o - 2>&1 < %s \ +# RUN: | FileCheck -check-prefix=NOPOSTMISCHED %s +# RUN: llc -mtriple=riscv64 -x mir -mcpu=sifive-p470 -mattr=+use-postra-scheduler -verify-misched -enable-post-misched=true \ +# RUN: -mattr=+disable-postmisched-load-clustering \ +# RUN: -mattr=+disable-postmisched-store-clustering -debug-only=machine-scheduler \ +# RUN: -start-before=machine-scheduler -stop-after=postmisched -misched-regpressure=false -o - 2>&1 < %s \ +# RUN: | FileCheck -check-prefix=NOCLUSTER %s +# RUN: llc -mtriple=riscv64 -x mir -mcpu=sifive-p470 -mattr=+use-postra-scheduler -verify-misched -enable-post-misched=true \ +# RUN: -debug-only=machine-scheduler \ +# RUN: -start-before=machine-scheduler -stop-after=postmisched -misched-regpressure=false -o - 2>&1 < %s \ +# RUN: | FileCheck -check-prefix=MEMCLUSTER %s + +# REQUIRES: asserts + +... +--- +name: mem_clustering_1 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x6, $x10, $x14, $x15, $x16, $x17 + ; NOPOSTMISCHED-LABEL: name: mem_clustering_1 + ; NOPOSTMISCHED: liveins: $x6, $x10, $x14, $x15, $x16, $x17 + ; NOPOSTMISCHED-NEXT: {{ $}} + ; NOPOSTMISCHED-NEXT: renamable $x5 = LW renamable $x15, 0 :: (load (s32)) + ; NOPOSTMISCHED-NEXT: renamable $x7 = LW renamable $x15, 8 :: (load (s32)) + ; NOPOSTMISCHED-NEXT: renamable $x28 = LW renamable $x15, 16 :: (load (s32)) + ; NOPOSTMISCHED-NEXT: renamable $x29 = LW renamable $x15, 24 :: (load (s32)) + ; NOPOSTMISCHED-NEXT: renamable $x11 = ADDW renamable $x6, killed renamable $x5 + ; NOPOSTMISCHED-NEXT: renamable $x13 = ADDW killed renamable $x7, killed renamable $x28 + ; NOPOSTMISCHED-NEXT: renamable $x11 = ADDW killed renamable $x11, killed renamable $x13 + ; NOPOSTMISCHED-NEXT: renamable $x6 = ADDW killed renamable $x11, killed renamable $x29 + ; NOPOSTMISCHED-NEXT: SW renamable $x14, renamable $x15, 0 :: (store (s32)) + ; NOPOSTMISCHED-NEXT: SW renamable $x14, renamable $x15, 8 :: (store (s32)) + ; NOPOSTMISCHED-NEXT: SW renamable $x14, renamable $x15, 16 :: (store (s32)) + ; NOPOSTMISCHED-NEXT: SW renamable $x14, renamable $x15, 24 :: (store (s32)) + ; NOPOSTMISCHED-NEXT: PseudoRET + ; + ; NOCLUSTER-LABEL: name: mem_clustering_1 + ; NOCLUSTER: liveins: $x6, $x10, $x14, $x15, $x16, $x17 + ; NOCLUSTER-NEXT: {{ $}} + ; NOCLUSTER-NEXT: renamable $x5 = LW renamable $x15, 0 :: (load (s32)) + ; NOCLUSTER-NEXT: SW renamable $x14, renamable $x15, 0 :: (store (s32)) + ; NOCLUSTER-NEXT: renamable $x11 = ADDW killed renamable $x6, killed renamable $x5 + ; NOCLUSTER-NEXT: renamable $x7 = LW renamable $x15, 8 :: (load (s32)) + ; NOCLUSTER-NEXT: renamable $x28 = LW renamable $x15, 16 :: (load (s32)) + ; NOCLUSTER-NEXT: renamable $x29 = LW renamable $x15, 24 :: (load (s32)) + ; NOCLUSTER-NEXT: renamable $x13 = ADDW killed renamable $x7, killed renamable $x28 + ; NOCLUSTER-NEXT: SW renamable $x14, renamable $x15, 8 :: (store (s32)) + ; NOCLUSTER-NEXT: SW renamable $x14, renamable $x15, 16 :: (store (s32)) + ; NOCLUSTER-NEXT: SW killed renamable $x14, killed renamable $x15, 24 :: (store (s32)) + ; NOCLUSTER-NEXT: renamable $x11 = ADDW killed renamable $x11, killed renamable $x13 + ; NOCLUSTER-NEXT: renamable $x6 = ADDW killed renamable $x11, killed renamable $x29 + ; NOCLUSTER-NEXT: PseudoRET + ; + ; MEMCLUSTER-LABEL: name: mem_clustering_1 + ; MEMCLUSTER: liveins: $x6, $x10, $x14, $x15, $x16, $x17 + ; MEMCLUSTER-NEXT: {{ $}} + ; MEMCLUSTER-NEXT: renamable $x5 = LW renamable $x15, 0 :: (load (s32)) + ; MEMCLUSTER-NEXT: renamable $x7 = LW renamable $x15, 8 :: (load (s32)) + ; MEMCLUSTER-NEXT: renamable $x28 = LW renamable $x15, 16 :: (load (s32)) + ; MEMCLUSTER-NEXT: renamable $x29 = LW renamable $x15, 24 :: (load (s32)) + ; MEMCLUSTER-NEXT: SW renamable $x14, renamable $x15, 0 :: (store (s32)) + ; MEMCLUSTER-NEXT: SW renamable $x14, renamable $x15, 8 :: (store (s32)) + ; MEMCLUSTER-NEXT: SW renamable $x14, renamable $x15, 16 :: (store (s32)) + ; MEMCLUSTER-NEXT: SW killed renamable $x14, killed renamable $x15, 24 :: (store (s32)) + ; MEMCLUSTER-NEXT: renamable $x11 = ADDW killed renamable $x6, killed renamable $x5 + ; MEMCLUSTER-NEXT: renamable $x13 = ADDW killed renamable $x7, killed renamable $x28 + ; MEMCLUSTER-NEXT: renamable $x11 = ADDW killed renamable $x11, killed renamable $x13 + ; MEMCLUSTER-NEXT: renamable $x6 = ADDW killed renamable $x11, killed renamable $x29 + ; MEMCLUSTER-NEXT: PseudoRET + renamable $x5 = LW renamable $x15, 0 :: (load (s32)) + renamable $x7 = LW renamable $x15, 8 :: (load (s32)) + renamable $x28 = LW renamable $x15, 16 :: (load (s32)) + renamable $x29 = LW renamable $x15, 24 :: (load (s32)) + renamable $x11 = ADDW killed renamable $x6, killed renamable $x5 + renamable $x13 = ADDW killed renamable $x7, killed renamable $x28 + renamable $x11 = ADDW killed renamable $x11, killed renamable $x13 + renamable $x6 = ADDW killed renamable $x11, killed renamable $x29 + SW renamable $x14, renamable $x15, 0 :: (store (s32)) + SW renamable $x14, renamable $x15, 8 :: (store (s32)) + SW renamable $x14, renamable $x15, 16 :: (store (s32)) + SW renamable $x14, renamable $x15, 24 :: (store (s32)) + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/misched-postra-direction.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/misched-postra-direction.mir new file mode 100644 index 0000000..e4b934c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/misched-postra-direction.mir @@ -0,0 +1,82 @@ +# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -run-pass=postmisched \ +# RUN: -enable-post-misched -debug-only=machine-scheduler \ +# RUN: -misched-dump-schedule-trace -misched-postra-direction=topdown \ +# RUN: -o - %s 2>&1 | FileCheck --check-prefix=TOPDOWN %s +# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -run-pass=postmisched \ +# RUN: -enable-post-misched -debug-only=machine-scheduler \ +# RUN: -misched-dump-schedule-trace -misched-postra-direction=bottomup \ +# RUN: -o - %s 2>&1 | FileCheck --check-prefix=BOTTOMUP %s +# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -run-pass=postmisched \ +# RUN: -enable-post-misched -debug-only=machine-scheduler \ +# RUN: -misched-dump-schedule-trace -misched-postra-direction=bidirectional \ +# RUN: -o - %s 2>&1 | FileCheck --check-prefix=BIDIRECTIONAL %s + +# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -passes=postmisched \ +# RUN: -enable-post-misched -debug-only=machine-scheduler \ +# RUN: -misched-dump-schedule-trace -misched-postra-direction=topdown \ +# RUN: -o - %s 2>&1 | FileCheck --check-prefix=TOPDOWN %s +# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -passes=postmisched \ +# RUN: -enable-post-misched -debug-only=machine-scheduler \ +# RUN: -misched-dump-schedule-trace -misched-postra-direction=bottomup \ +# RUN: -o - %s 2>&1 | FileCheck --check-prefix=BOTTOMUP %s +# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -passes=postmisched \ +# RUN: -enable-post-misched -debug-only=machine-scheduler \ +# RUN: -misched-dump-schedule-trace -misched-postra-direction=bidirectional \ +# RUN: -o - %s 2>&1 | FileCheck --check-prefix=BIDIRECTIONAL %s + +# REQUIRES: asserts + +--- +name: test +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + renamable $x12 = MUL renamable $x11, renamable $x10 + renamable $x13 = ADD renamable $x11, renamable $x10 + renamable $x14 = DIVW killed renamable $x12, killed renamable $x13 + PseudoRET implicit $x14 +... + +# TOPDOWN: *** Final schedule for %bb.0 *** +# TOPDOWN-NEXT: * Schedule table (TopDown): +# TOPDOWN-NEXT: i: issue +# TOPDOWN-NEXT: x: resource booked +# TOPDOWN-NEXT: Cycle | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | +# TOPDOWN-NEXT: SU(0) | i | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# TOPDOWN-NEXT: SiFive7PipeAB | x | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# TOPDOWN-NEXT: SiFive7PipeB | x | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# TOPDOWN-NEXT: SU(1) | i | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# TOPDOWN-NEXT: SiFive7PipeAB | x | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# TOPDOWN-NEXT: SU(2) | | | | i | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# TOPDOWN-NEXT: SiFive7PipeAB | | | | x | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# TOPDOWN-NEXT: SiFive7PipeB | | | | x | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# TOPDOWN-NEXT: SiFive7IDiv | | | | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | +# TOPDOWN-NEXT: SU(0): renamable $x12 = MUL renamable $x11, renamable $x10 +# TOPDOWN-NEXT: SU(1): renamable $x13 = ADD renamable $x11, renamable $x10 +# TOPDOWN-NEXT: SU(2): renamable $x14 = DIVW renamable $x12, renamable $x13 + +# BOTTOMUP: *** Final schedule for %bb.0 *** +# BOTTOMUP-NEXT: * Schedule table (BottomUp): +# BOTTOMUP-NEXT: i: issue +# BOTTOMUP-NEXT: x: resource booked +# BOTTOMUP-NEXT: Cycle | 37 | 36 | 35 | 34 | 33 | 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | +# BOTTOMUP-NEXT: SU(1) | i | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# BOTTOMUP-NEXT: SiFive7PipeAB | x | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# BOTTOMUP-NEXT: SU(0) | i | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# BOTTOMUP-NEXT: SiFive7PipeAB | x | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# BOTTOMUP-NEXT: SiFive7PipeB | x | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# BOTTOMUP-NEXT: SU(2) | | | | i | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# BOTTOMUP-NEXT: SiFive7PipeAB | | | | x | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# BOTTOMUP-NEXT: SiFive7PipeB | | | | x | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +# BOTTOMUP-NEXT: SiFive7IDiv | | | | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | x | +# BOTTOMUP-NEXT: SU(1): renamable $x13 = ADD renamable $x11, renamable $x10 +# BOTTOMUP-NEXT: SU(0): renamable $x12 = MUL renamable $x11, renamable $x10 +# BOTTOMUP-NEXT: SU(2): renamable $x14 = DIVW renamable $x12, renamable $x13 + +# BIDIRECTIONAL: *** Final schedule for %bb.0 *** +# BIDIRECTIONAL-NEXT: * Schedule table (Bidirectional): not implemented +# BIDIRECTIONAL-NEXT: SU(1): renamable $x13 = ADD renamable $x11, renamable $x10 +# BIDIRECTIONAL-NEXT: SU(0): renamable $x12 = MUL renamable $x11, renamable $x10 +# BIDIRECTIONAL-NEXT: SU(2): renamable $x14 = DIVW renamable $x12, renamable $x13 diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/move-merge-zdinx-mvsa-regression.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/move-merge-zdinx-mvsa-regression.mir new file mode 100644 index 0000000..6dc8904 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/move-merge-zdinx-mvsa-regression.mir @@ -0,0 +1,28 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=riscv32 -mattr=+zcmp,+zdinx -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck %s --check-prefix=CHECK-ZCMP +# RUN: llc -mtriple=riscv32 -mattr=+xqccmp,+zdinx -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck %s --check-prefix=CHECK-XQCCMP + +--- +name: no_mismerge_mvsa_with_zdinx +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12 + ; CHECK-ZCMP-LABEL: name: no_mismerge_mvsa_with_zdinx + ; CHECK-ZCMP: liveins: $x10, $x11, $x12 + ; CHECK-ZCMP-NEXT: {{ $}} + ; CHECK-ZCMP-NEXT: $x18 = ADDI $x12, 0 + ; CHECK-ZCMP-NEXT: $x9, $x19 = CM_MVSA01 implicit $x10, implicit $x11 + ; CHECK-ZCMP-NEXT: PseudoRET + ; + ; CHECK-XQCCMP-LABEL: name: no_mismerge_mvsa_with_zdinx + ; CHECK-XQCCMP: liveins: $x10, $x11, $x12 + ; CHECK-XQCCMP-NEXT: {{ $}} + ; CHECK-XQCCMP-NEXT: $x18 = ADDI $x12, 0 + ; CHECK-XQCCMP-NEXT: $x9, $x19 = QC_CM_MVSA01 implicit $x10, implicit $x11 + ; CHECK-XQCCMP-NEXT: PseudoRET + $x18 = ADDI $x12, 0 + $x9 = ADDI $x10, 0 + $x19 = ADDI $x11, 0 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir new file mode 100644 index 0000000..55545fa --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir @@ -0,0 +1,247 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s + +--- +name: merge_sextw_removed +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: merge_sextw_removed + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[ADDW1:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]] + ; CHECK-NEXT: [[ADDW2:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[MERGE:%[0-9]+]]:gpr = MERGE [[ADDW]], [[ADDW1]], [[ADDW2]] + ; CHECK-NEXT: $x10 = COPY [[MERGE]] + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + ; ADDW produces sign-extended results + %3:gpr = ADDW %0, %1 + %4:gpr = ADDW %1, %2 + %5:gpr = ADDW %0, %2 + %6:gpr = MERGE %3, %4, %5 + %7:gpr = ADDIW %6, 0 + $x10 = COPY %7 + PseudoRET +... +--- +name: mvm_sextw_removed +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: mvm_sextw_removed + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[ADDW1:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]] + ; CHECK-NEXT: [[ADDW2:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[MVM:%[0-9]+]]:gpr = MVM [[ADDW]], [[ADDW1]], [[ADDW2]] + ; CHECK-NEXT: $x10 = COPY [[MVM]] + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %3:gpr = ADDW %0, %1 + %4:gpr = ADDW %1, %2 + %5:gpr = ADDW %0, %2 + %6:gpr = MVM %3, %4, %5 + %7:gpr = ADDIW %6, 0 + $x10 = COPY %7 + PseudoRET +... +--- +name: mvmn_sextw_removed +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: mvmn_sextw_removed + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[ADDW1:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]] + ; CHECK-NEXT: [[ADDW2:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY2]] + ; CHECK-NEXT: [[MVMN:%[0-9]+]]:gpr = MVMN [[ADDW]], [[ADDW1]], [[ADDW2]] + ; CHECK-NEXT: $x10 = COPY [[MVMN]] + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %3:gpr = ADDW %0, %1 + %4:gpr = ADDW %1, %2 + %5:gpr = ADDW %0, %2 + %6:gpr = MVMN %3, %4, %5 + %7:gpr = ADDIW %6, 0 + $x10 = COPY %7 + PseudoRET +... +--- +name: merge_sextw_not_removed +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: merge_sextw_not_removed + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[MERGE:%[0-9]+]]:gpr = MERGE [[COPY]], [[COPY1]], [[COPY2]] + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[MERGE]], 0 + ; CHECK-NEXT: $x10 = COPY [[ADDIW]] + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %3:gpr = MERGE %0, %1, %2 + %4:gpr = ADDIW %3, 0 + $x10 = COPY %4 + PseudoRET +... +--- +name: sati_rv64_sextw_removed_imm16 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: sati_rv64_sextw_removed_imm16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SATI_RV64_:%[0-9]+]]:gpr = SATI_RV64 [[COPY]], 16, implicit-def $vxsat + ; CHECK-NEXT: $x10 = COPY [[SATI_RV64_]] + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; SATI_RV64 with imm=16 saturates to [-2^15, 2^15-1], which is sign-extended + %1:gpr = SATI_RV64 %0, 16, implicit-def $vxsat + %2:gpr = ADDIW %1, 0 + $x10 = COPY %2 + PseudoRET +... +--- +name: sati_rv64_sextw_removed_imm32 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: sati_rv64_sextw_removed_imm32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SATI_RV64_:%[0-9]+]]:gpr = SATI_RV64 [[COPY]], 32, implicit-def $vxsat + ; CHECK-NEXT: $x10 = COPY [[SATI_RV64_]] + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; SATI_RV64 with imm=32 saturates to [-2^31, 2^31-1], which is sign-extended + %1:gpr = SATI_RV64 %0, 32, implicit-def $vxsat + %2:gpr = ADDIW %1, 0 + $x10 = COPY %2 + PseudoRET +... +--- +name: sati_rv64_sextw_not_removed_imm33 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: sati_rv64_sextw_not_removed_imm33 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[SATI_RV64_:%[0-9]+]]:gpr = SATI_RV64 [[COPY]], 33, implicit-def $vxsat + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[SATI_RV64_]], 0 + ; CHECK-NEXT: $x10 = COPY [[ADDIW]] + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; SATI_RV64 with imm=33 saturates to [-2^32, 2^32-1], which is NOT sign-extended from bit 31 + %1:gpr = SATI_RV64 %0, 33, implicit-def $vxsat + %2:gpr = ADDIW %1, 0 + $x10 = COPY %2 + PseudoRET +... +--- +name: usati_rv64_sextw_removed_imm16 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: usati_rv64_sextw_removed_imm16 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[USATI_RV64_:%[0-9]+]]:gpr = USATI_RV64 [[COPY]], 16, implicit-def $vxsat + ; CHECK-NEXT: $x10 = COPY [[USATI_RV64_]] + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; USATI_RV64 with imm=16 saturates to [0, 2^16-1], which is sign-extended (bit 31 is 0) + %1:gpr = USATI_RV64 %0, 16, implicit-def $vxsat + %2:gpr = ADDIW %1, 0 + $x10 = COPY %2 + PseudoRET +... +--- +name: usati_rv64_sextw_removed_imm31 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: usati_rv64_sextw_removed_imm31 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[USATI_RV64_:%[0-9]+]]:gpr = USATI_RV64 [[COPY]], 31, implicit-def $vxsat + ; CHECK-NEXT: $x10 = COPY [[USATI_RV64_]] + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; USATI_RV64 with imm=31 saturates to [0, 2^31-1], which is sign-extended (bit 31 is 0) + %1:gpr = USATI_RV64 %0, 31, implicit-def $vxsat + %2:gpr = ADDIW %1, 0 + $x10 = COPY %2 + PseudoRET +... +--- +name: usati_rv64_sextw_not_removed_imm32 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: usati_rv64_sextw_not_removed_imm32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[USATI_RV64_:%[0-9]+]]:gpr = USATI_RV64 [[COPY]], 32, implicit-def $vxsat + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[USATI_RV64_]], 0 + ; CHECK-NEXT: $x10 = COPY [[ADDIW]] + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; USATI_RV64 with imm=32 saturates to [0, 2^32-1], which is NOT sign-extended from bit 31 + %1:gpr = USATI_RV64 %0, 32, implicit-def $vxsat + %2:gpr = ADDIW %1, 0 + $x10 = COPY %2 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/opt-w-instrs.mir new file mode 100644 index 0000000..7aef3cb --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/opt-w-instrs.mir @@ -0,0 +1,269 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa,+v,+xtheadmempair' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s + +--- +name: fcvtmod_w_d +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; CHECK-LABEL: name: fcvtmod_w_d + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10 + ; CHECK-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1 + ; CHECK-NEXT: $x10 = COPY [[FCVTMOD_W_D]] + ; CHECK-NEXT: PseudoRET + %0:fpr64 = COPY $x10 + + %1:gpr = nofpexcept FCVTMOD_W_D %0, 1 + %2:gpr = ADDIW %1, 0 + $x10 = COPY %2 + PseudoRET +... + +--- +name: physreg +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: physreg + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0 + ; CHECK-NEXT: $x10 = COPY [[ADDIW]] + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = ADDIW %0, 0 + $x10 = COPY %1 + PseudoRET +... +--- + name: vfirst + tracksRegLiveness: true + body: | + bb.0.entry: + liveins: $x10, $v8 + + ; CHECK-LABEL: name: vfirst + ; CHECK: liveins: $x10, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[PseudoVFIRST_M_B1_:%[0-9]+]]:gpr = PseudoVFIRST_M_B1 [[COPY]], [[COPY1]] /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $x11 = COPY [[PseudoVFIRST_M_B1_]] + ; CHECK-NEXT: PseudoRET + %0:vr = COPY $v8 + %1:gprnox0 = COPY $x10 + + %2:gpr = PseudoVFIRST_M_B1 %0:vr, %1:gprnox0, 0 + %3:gpr = ADDIW %2, 0 + $x11 = COPY %3 + PseudoRET +... +--- + name: vcpop + tracksRegLiveness: true + body: | + bb.0.entry: + liveins: $x10, $v8 + + ; CHECK-LABEL: name: vcpop + ; CHECK: liveins: $x10, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[COPY]], [[COPY1]] /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $x11 = COPY [[PseudoVCPOP_M_B1_]] + ; CHECK-NEXT: PseudoRET + %0:vr = COPY $v8 + %1:gprnox0 = COPY $x10 + + %2:gpr = PseudoVCPOP_M_B1 %0:vr, %1:gprnox0, 0 + %3:gpr = ADDIW %2, 0 + $x11 = COPY %3 + PseudoRET +... +--- + name: th_lwd + tracksRegLiveness: true + body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: th_lwd + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: early-clobber %1:gpr, early-clobber %2:gpr = TH_LWD [[COPY]], 2, 3 + ; CHECK-NEXT: $x10 = COPY %1 + ; CHECK-NEXT: $x11 = COPY %2 + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + early-clobber %1:gpr, early-clobber %2:gpr = TH_LWD %0, 2, 3 + %3:gpr = ADDIW %1, 0 + %4:gpr = ADDIW %2, 0 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... +--- +name: movgprnox0_1 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12, $x13 + ; CHECK-LABEL: name: movgprnox0_1 + ; CHECK: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprnox0 = COPY $x13 + ; CHECK-NEXT: [[PseudoCCMOVGPRNoX0_:%[0-9]+]]:gprnox0 = PseudoCCMOVGPRNoX0 [[COPY2]], [[COPY3]], 1, [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[PseudoCCMOVGPRNoX0_]], 0 + ; CHECK-NEXT: $x10 = COPY [[ADDIW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %3:gpr = COPY $x13 + %4:gprnox0 = ADDIW %2, 0 + %5:gprnox0 = ADDIW %3, 0 + %6:gprnox0 = PseudoCCMOVGPRNoX0 %4, %5, 1, %0, %1 + %7:gpr = ADDIW %6, 0 + $x10 = COPY %7 + PseudoRET implicit $x10 + +... +--- +name: movgprnox0_2 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12, $x13 + ; CHECK-LABEL: name: movgprnox0_2 + ; CHECK: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13 + ; CHECK-NEXT: [[SRAIW:%[0-9]+]]:gprnox0 = SRAIW [[COPY2]], 0 + ; CHECK-NEXT: [[SRAIW1:%[0-9]+]]:gprnox0 = SRAIW [[COPY3]], 0 + ; CHECK-NEXT: [[PseudoCCMOVGPRNoX0_:%[0-9]+]]:gprnox0 = PseudoCCMOVGPRNoX0 [[SRAIW]], [[SRAIW1]], 1, [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[PseudoCCMOVGPRNoX0_]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %3:gpr = COPY $x13 + %4:gprnox0 = SRAIW %2, 0 + %5:gprnox0 = SRAIW %3, 0 + %6:gprnox0 = PseudoCCMOVGPRNoX0 %4, %5, 1, %0, %1 + %7:gpr = ADDIW %6, 0 + $x10 = COPY %7 + PseudoRET implicit $x10 + +... +--- +name: lui_addi_1 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: lui_addi_1 + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0 + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 11 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI killed [[LUI]], -1756 + ; CHECK-NEXT: BEQ killed [[ADDIW]], [[ADDI]], %bb.2 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW $x0, 0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[ADDI]], %bb.0, [[LW]], %bb.1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprtcnonx7 = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY1]] + ; CHECK-NEXT: $x11 = COPY [[PHI]] + ; CHECK-NEXT: PseudoTAILIndirect [[COPY1]], csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11 + bb.0: + liveins: $x10 + + %2:gpr = COPY $x10 + %4:gpr = ADDIW %2, 0 + %5:gpr = LUI 11 + %3:gpr = ADDI killed %5, -1756 + BEQ killed %4, %3, %bb.2 + PseudoBR %bb.1 + + bb.1: + %0:gpr = LW $x0, 0 + + bb.2: + %1:gpr = PHI %3, %bb.0, %0, %bb.1 + %6:gpr = ADDIW %1, 0 + %7:gprtcnonx7 = COPY $x0 + $x10 = COPY %7 + $x11 = COPY %6 + PseudoTAILIndirect %7, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11 +... +--- +# The sext.w was erroneously removed in an earlier broken version of the patch +# for RISCVOptWInstrs that added lui/addi handling. +name: lui_addi_2 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: lui_addi_2 + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524289 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -2048 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: [[LWU:%[0-9]+]]:gpr = LWU $x0, 0 :: (load (s32) from `ptr null`) + ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[LWU]], [[ADDI]] + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW killed [[AND]], 0 + ; CHECK-NEXT: $x10 = COPY [[ADDIW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[ADDIW]] + ; CHECK-NEXT: %call_target_dummy:gprjalrnonx7 = COPY $x0 + ; CHECK-NEXT: PseudoCALLIndirect %call_target_dummy, csr_ilp32_lp64, implicit-def $x1, implicit $x10 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + ; CHECK-NEXT: $x10 = COPY [[LWU]] + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0.entry: + %13:gpr = LUI 524289 + %14:gpr = ADDI %13, -2048 + + bb.1: + %1:gpr = LWU $x0, 0 :: (load (s32) from `ptr null`) + %15:gpr = AND %1, %14 + %16:gpr = ADDIW killed %15, 0 + + $x10 = COPY %16 + PseudoRET implicit $x10 + + bb.2: + ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2 + $x10 = COPY %16 + %call_target_dummy:gprjalrnonx7 = COPY $x0 + PseudoCALLIndirect %call_target_dummy, csr_ilp32_lp64, implicit-def $x1, implicit $x10 + ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 + + $x10 = COPY %1 + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir new file mode 100644 index 0000000..5f6f3bf --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir @@ -0,0 +1,81 @@ +# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +# REQUIRES: asserts +# RUN: llc -mtriple riscv64 -start-before=prologepilog -o - \ +# RUN: -verify-machineinstrs %s | FileCheck %s +# +# RUN: llc -mtriple riscv64 -start-before=prologepilog -o /dev/null \ +# RUN: -debug-only=prologepilog -verify-machineinstrs %s 2>&1 \ +# RUN: | FileCheck --check-prefix=DEBUG %s +# +# DEBUG: Adjusting emergency spill slots! +# DEBUG: Adjusting offset of emergency spill slot #4 from -4112 to -8192 + +# FIXME: The code generated here is incorrect. It stores a0 to 0(sp) before +# sub sp, sp, a0 but restores it after sub sp, sp, a0. We may need to implement +# the target hook saveScavengerRegister to solve it. + +--- | + ; ModuleID = 'reduced.ll' + source_filename = "frame_layout-1253b1.cpp" + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" + target triple = "riscv64" + + ; Function Attrs: nounwind + define weak_odr dso_local void @foo(ptr %ay) nounwind { + ; CHECK-LABEL: foo: + ; CHECK: # %bb.0: # %entry + ; CHECK-NEXT: addi sp, sp, -2032 + ; CHECK-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill + ; CHECK-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill + ; CHECK-NEXT: addi s0, sp, 2032 + ; CHECK-NEXT: sd a0, 0(sp) # 8-byte Folded Spill + ; CHECK-NEXT: lui a0, 2 + ; CHECK-NEXT: addi a0, a0, -2032 + ; CHECK-NEXT: sub sp, sp, a0 + ; CHECK-NEXT: srli a0, sp, 12 + ; CHECK-NEXT: slli sp, a0, 12 + ; CHECK-NEXT: ld a0, 0(sp) # 8-byte Folded Reload + ; CHECK-NEXT: sd a1, 0(sp) # 8-byte Folded Spill + ; CHECK-NEXT: lui a1, 1 + ; CHECK-NEXT: add a1, sp, a1 + ; CHECK-NEXT: sd a0, -8(a1) + ; CHECK-NEXT: ld a1, 0(sp) # 8-byte Folded Reload + ; CHECK-NEXT: call foo + ; CHECK-NEXT: addi sp, s0, -2032 + ; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload + ; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload + ; CHECK-NEXT: addi sp, sp, 2032 + ; CHECK-NEXT: ret + entry: + ret void + } + + +... +--- +name: foo +alignment: 2 +tracksRegLiveness: false +frameInfo: + maxAlignment: 4096 +stack: + - { id: 0, size: 8, alignment: 4096 } + - { id: 1, type: spill-slot, size: 8, alignment: 8 } +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x31 + + ; This is to store something to the (non-emergency) spill slot %stack.1. + SD $x10, %stack.1, 0 + ; This is here just to make all the eligible registers live at this point. + ; This way when we replace the frame index %stack.1 with its actual address + ; we have to allocate a virtual register to compute it. + ; A later run of the the register scavenger won't find an available register + ; either so it will have to spill one to the emergency spill slot. + PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31 + PseudoRET + +... +## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +# DEBUG: {{.*}} diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/postra-copy-expand.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/postra-copy-expand.mir new file mode 100644 index 0000000..e5b8565 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/postra-copy-expand.mir @@ -0,0 +1,24 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=postrapseudos %s -o - | FileCheck %s + +--- +name: copy +isSSA: false +noVRegs: true +liveins: + - { reg: '$v0', virtual-reg: '' } +body: | + bb.0: + liveins: $v0 + + ; CHECK-LABEL: name: copy + ; CHECK: liveins: $v0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2, implicit $vtype, implicit $v14_v15_v16_v17_v18 + ; CHECK-NEXT: $v22m2 = VMV2R_V $v16m2, implicit $vtype, implicit $v14_v15_v16_v17_v18 + ; CHECK-NEXT: $v24 = VMV1R_V $v18, implicit $vtype, implicit $v14_v15_v16_v17_v18, implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v0 + renamable $v20_v21_v22_v23_v24 = COPY renamable $v14_v15_v16_v17_v18, implicit $vtype + PseudoRET implicit $v0 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/pr153598.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/pr153598.mir new file mode 100644 index 0000000..ef28908 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/pr153598.mir @@ -0,0 +1,25 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv32 -mattr=+zcmp -run-pass=riscv-move-merge -verify-machineinstrs %s -o - | FileCheck %s +--- +name: mov-merge +tracksRegLiveness: true +frameInfo: + maxCallFrameSize: 0 +body: | + bb.0.entry: + liveins: $x8, $x9 + ; CHECK-LABEL: name: mov-merge + ; CHECK: liveins: $x8, $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x12 = ADDI $x0, -3 + ; CHECK-NEXT: SW renamable $x9, $x2, 56 + ; CHECK-NEXT: CM_MVA01S killed renamable $x9, renamable $x8, implicit-def $x10, implicit-def $x11 + ; CHECK-NEXT: SW renamable $x8, $x2, 60 + ; CHECK-NEXT: PseudoRET + $x12 = ADDI $x0, -3 + SW renamable $x9, $x2, 56 + $x10 = ADDI killed renamable $x9, 0 + SW renamable $x8, $x2, 60 + $x11 = ADDI killed renamable $x8, 0 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/pr53662.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/pr53662.mir new file mode 100644 index 0000000..dccad40 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/pr53662.mir @@ -0,0 +1,40 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=prologepilog -o - %s | FileCheck %s +--- | + define void @b() { + entry: + unreachable + } + +... +--- +name: b +frameInfo: + savePoint: + - point: '%bb.0' + restorePoint: + - point: '%bb.1' +body: | + ; CHECK-LABEL: name: b + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: DBG_VALUE $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: PseudoRET implicit killed $x10 + bb.0 : + PseudoBR %bb.1 + + bb.1: + DBG_VALUE $noreg + + bb.2: + PseudoRET implicit killed $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/pr80052.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/pr80052.mir new file mode 100644 index 0000000..e0d8df0 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/pr80052.mir @@ -0,0 +1,116 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc %s -mtriple=riscv64 -run-pass=greedy,virtregrewriter,stack-slot-coloring -o - | FileCheck %s + +--- +name: foo +alignment: 4 +tracksRegLiveness: true +frameInfo: + maxAlignment: 4 + localFrameSize: 4 +stack: + - { id: 0, size: 1, alignment: 4, local-offset: -4 } +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + ; To trick stack-slot-colouring to run its dead-store-elimination phase, + ; which is at fault, we need the register allocator to run, and spill in two + ; places that can have their slots merged. Achieve this by volatile-loading + ; data into all allocatable GPRs except $x31. Then, volatile storing them + ; later, leaving regalloc only $x31 to play with in the middle. + $x1 = LW %stack.0, 0 :: (volatile load (s32)) + $x5 = LW %stack.0, 0 :: (volatile load (s32)) + $x6 = LW %stack.0, 0 :: (volatile load (s32)) + $x7 = LW %stack.0, 0 :: (volatile load (s32)) + $x8 = LW %stack.0, 0 :: (volatile load (s32)) + $x9 = LW %stack.0, 0 :: (volatile load (s32)) + $x10 = LW %stack.0, 0 :: (volatile load (s32)) + $x11 = LW %stack.0, 0 :: (volatile load (s32)) + $x12 = LW %stack.0, 0 :: (volatile load (s32)) + $x13 = LW %stack.0, 0 :: (volatile load (s32)) + $x14 = LW %stack.0, 0 :: (volatile load (s32)) + $x15 = LW %stack.0, 0 :: (volatile load (s32)) + $x16 = LW %stack.0, 0 :: (volatile load (s32)) + $x17 = LW %stack.0, 0 :: (volatile load (s32)) + $x18 = LW %stack.0, 0 :: (volatile load (s32)) + $x19 = LW %stack.0, 0 :: (volatile load (s32)) + $x20 = LW %stack.0, 0 :: (volatile load (s32)) + $x21 = LW %stack.0, 0 :: (volatile load (s32)) + $x22 = LW %stack.0, 0 :: (volatile load (s32)) + $x23 = LW %stack.0, 0 :: (volatile load (s32)) + $x24 = LW %stack.0, 0 :: (volatile load (s32)) + $x25 = LW %stack.0, 0 :: (volatile load (s32)) + $x26 = LW %stack.0, 0 :: (volatile load (s32)) + $x27 = LW %stack.0, 0 :: (volatile load (s32)) + $x28 = LW %stack.0, 0 :: (volatile load (s32)) + $x29 = LW %stack.0, 0 :: (volatile load (s32)) + $x30 = LW %stack.0, 0 :: (volatile load (s32)) + + ; Force the first spill. + %0:gpr = LW %stack.0, 0 :: (volatile load (s32)) + %1:gpr = LW %stack.0, 0 :: (volatile load (s32)) + SW %1, %stack.0, 0 :: (volatile store (s32)) + SW %0, %stack.0, 0 :: (volatile store (s32)) + + ; CHECK: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32)) + ; CHECK-NEXT: SD killed renamable $x31, %stack.1, 0 :: (store (s64) into %stack.1) + ; CHECK-NEXT: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32)) + ; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32)) + ; CHECK-NEXT: renamable $x31 = LD %stack.1, 0 :: (load (s64) from %stack.1) + ; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32)) + + ; stack-slot-coloring doesn't know that a write to $x0 is discarded. + dead $x0 = LW %stack.0, 0 :: (volatile load (s32)) + ; This stores 0 rather than the result of the preceding load since $x0 + ; is special. + ; We don't want this store to be deleted. + SW $x0, %stack.0, 0 :: (volatile store (s32)) + + ; CHECK-NEXT: dead $x0 = LW %stack.0, 0 :: (volatile load (s32)) + ; CHECK-NEXT: SW $x0, %stack.0, 0 :: (volatile store (s32)) + + ; Force a second spill + %2:gpr = LW %stack.0, 0 :: (volatile load (s32)) + %3:gpr = LW %stack.0, 0 :: (volatile load (s32)) + SW %3, %stack.0, 0 :: (volatile store (s32)) + SW %2, %stack.0, 0 :: (volatile store (s32)) + + ; CHECK-NEXT: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32)) + ; CHECK-NEXT: SD killed renamable $x31, %stack.1, 0 :: (store (s64) into %stack.1) + ; CHECK-NEXT: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32)) + ; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32)) + ; CHECK-NEXT: renamable $x31 = LD %stack.1, 0 :: (load (s64) from %stack.1) + ; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32)) + + SW $x1, %stack.0, 0 :: (volatile store (s32)) + SW $x5, %stack.0, 0 :: (volatile store (s32)) + SW $x6, %stack.0, 0 :: (volatile store (s32)) + SW $x7, %stack.0, 0 :: (volatile store (s32)) + SW $x8, %stack.0, 0 :: (volatile store (s32)) + SW $x9, %stack.0, 0 :: (volatile store (s32)) + SW $x10, %stack.0, 0 :: (volatile store (s32)) + SW $x11, %stack.0, 0 :: (volatile store (s32)) + SW $x12, %stack.0, 0 :: (volatile store (s32)) + SW $x13, %stack.0, 0 :: (volatile store (s32)) + SW $x14, %stack.0, 0 :: (volatile store (s32)) + SW $x15, %stack.0, 0 :: (volatile store (s32)) + SW $x16, %stack.0, 0 :: (volatile store (s32)) + SW $x17, %stack.0, 0 :: (volatile store (s32)) + SW $x18, %stack.0, 0 :: (volatile store (s32)) + SW $x19, %stack.0, 0 :: (volatile store (s32)) + SW $x20, %stack.0, 0 :: (volatile store (s32)) + SW $x21, %stack.0, 0 :: (volatile store (s32)) + SW $x22, %stack.0, 0 :: (volatile store (s32)) + SW $x23, %stack.0, 0 :: (volatile store (s32)) + SW $x24, %stack.0, 0 :: (volatile store (s32)) + SW $x25, %stack.0, 0 :: (volatile store (s32)) + SW $x26, %stack.0, 0 :: (volatile store (s32)) + SW $x27, %stack.0, 0 :: (volatile store (s32)) + SW $x28, %stack.0, 0 :: (volatile store (s32)) + SW $x29, %stack.0, 0 :: (volatile store (s32)) + SW $x30, %stack.0, 0 :: (volatile store (s32)) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/prefer-w-inst.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/prefer-w-inst.mir new file mode 100644 index 0000000..f534567 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/prefer-w-inst.mir @@ -0,0 +1,295 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc %s -mtriple=riscv64 -run-pass=riscv-opt-w-instrs -verify-machineinstrs \ +# RUN: -mattr=+m -o - | FileCheck %s -check-prefixes=NO-PREFER-W-INST +# RUN: llc %s -mtriple=riscv64 -run-pass=riscv-opt-w-instrs -verify-machineinstrs \ +# RUN: -mattr=+m,+prefer-w-inst -o - | FileCheck %s -check-prefixes=PREFER-W-INST + +--- +name: addi +body: | + bb.0.entry: + liveins: $x10, $x11 + ; NO-PREFER-W-INST-LABEL: name: addi + ; NO-PREFER-W-INST: liveins: $x10, $x11 + ; NO-PREFER-W-INST-NEXT: {{ $}} + ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; NO-PREFER-W-INST-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 1 + ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[ADDI]], 1 + ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; NO-PREFER-W-INST-NEXT: PseudoRET + ; + ; PREFER-W-INST-LABEL: name: addi + ; PREFER-W-INST: liveins: $x10, $x11 + ; PREFER-W-INST-NEXT: {{ $}} + ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 1 + ; PREFER-W-INST-NEXT: [[ADDIW1:%[0-9]+]]:gpr = ADDIW [[ADDIW]], 1 + ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW1]] + ; PREFER-W-INST-NEXT: PseudoRET + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADDI %1, 1 + %4:gpr = ADDIW %3, 1 + $x10 = COPY %4 + PseudoRET +... + +--- +name: add +body: | + bb.0.entry: + liveins: $x10, $x11 + ; NO-PREFER-W-INST-LABEL: name: add + ; NO-PREFER-W-INST: liveins: $x10, $x11 + ; NO-PREFER-W-INST-NEXT: {{ $}} + ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; NO-PREFER-W-INST-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]] + ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[ADD]], 1 + ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; NO-PREFER-W-INST-NEXT: PseudoRET + ; + ; PREFER-W-INST-LABEL: name: add + ; PREFER-W-INST: liveins: $x10, $x11 + ; PREFER-W-INST-NEXT: {{ $}} + ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; PREFER-W-INST-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]] + ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[ADDW]], 1 + ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; PREFER-W-INST-NEXT: PseudoRET + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ADD %1, %2 + %4:gpr = ADDIW %3, 1 + $x10 = COPY %4 + PseudoRET +... + +--- +name: sub +body: | + bb.0.entry: + liveins: $x10, $x11 + ; NO-PREFER-W-INST-LABEL: name: sub + ; NO-PREFER-W-INST: liveins: $x10, $x11 + ; NO-PREFER-W-INST-NEXT: {{ $}} + ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; NO-PREFER-W-INST-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY1]] + ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[SUB]], 1 + ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; NO-PREFER-W-INST-NEXT: PseudoRET + ; + ; PREFER-W-INST-LABEL: name: sub + ; PREFER-W-INST: liveins: $x10, $x11 + ; PREFER-W-INST-NEXT: {{ $}} + ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; PREFER-W-INST-NEXT: [[SUBW:%[0-9]+]]:gpr = SUBW [[COPY]], [[COPY1]] + ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[SUBW]], 1 + ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; PREFER-W-INST-NEXT: PseudoRET + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SUB %1, %2 + %4:gpr = ADDIW %3, 1 + $x10 = COPY %4 + PseudoRET +... + +--- +name: mul +body: | + bb.0.entry: + liveins: $x10, $x11 + ; NO-PREFER-W-INST-LABEL: name: mul + ; NO-PREFER-W-INST: liveins: $x10, $x11 + ; NO-PREFER-W-INST-NEXT: {{ $}} + ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; NO-PREFER-W-INST-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY1]] + ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[MUL]], 1 + ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; NO-PREFER-W-INST-NEXT: PseudoRET + ; + ; PREFER-W-INST-LABEL: name: mul + ; PREFER-W-INST: liveins: $x10, $x11 + ; PREFER-W-INST-NEXT: {{ $}} + ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; PREFER-W-INST-NEXT: [[MULW:%[0-9]+]]:gpr = MULW [[COPY]], [[COPY1]] + ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[MULW]], 1 + ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; PREFER-W-INST-NEXT: PseudoRET + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = MUL %1, %2 + %4:gpr = ADDIW %3, 1 + $x10 = COPY %4 + PseudoRET +... + + +--- +name: slli_31 +body: | + bb.0.entry: + liveins: $x10, $x11 + ; NO-PREFER-W-INST-LABEL: name: slli_31 + ; NO-PREFER-W-INST: liveins: $x10, $x11 + ; NO-PREFER-W-INST-NEXT: {{ $}} + ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; NO-PREFER-W-INST-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 31 + ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[SLLI]], 1 + ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; NO-PREFER-W-INST-NEXT: PseudoRET + ; + ; PREFER-W-INST-LABEL: name: slli_31 + ; PREFER-W-INST: liveins: $x10, $x11 + ; PREFER-W-INST-NEXT: {{ $}} + ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; PREFER-W-INST-NEXT: [[SLLIW:%[0-9]+]]:gpr = SLLIW [[COPY]], 31 + ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[SLLIW]], 1 + ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; PREFER-W-INST-NEXT: PseudoRET + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SLLI %1, 31 + %4:gpr = ADDIW %3, 1 + $x10 = COPY %4 + PseudoRET +... + +--- +name: slli_32 +body: | + bb.0.entry: + liveins: $x10, $x11 + ; NO-PREFER-W-INST-LABEL: name: slli_32 + ; NO-PREFER-W-INST: liveins: $x10, $x11 + ; NO-PREFER-W-INST-NEXT: {{ $}} + ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; NO-PREFER-W-INST-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 32 + ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[SLLI]], 1 + ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; NO-PREFER-W-INST-NEXT: PseudoRET + ; + ; PREFER-W-INST-LABEL: name: slli_32 + ; PREFER-W-INST: liveins: $x10, $x11 + ; PREFER-W-INST-NEXT: {{ $}} + ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; PREFER-W-INST-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 32 + ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[SLLI]], 1 + ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; PREFER-W-INST-NEXT: PseudoRET + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = SLLI %1, 32 + %4:gpr = ADDIW %3, 1 + $x10 = COPY %4 + PseudoRET +... + +--- +name: ld +body: | + bb.0.entry: + liveins: $x10, $x11 + ; NO-PREFER-W-INST-LABEL: name: ld + ; NO-PREFER-W-INST: liveins: $x10, $x11 + ; NO-PREFER-W-INST-NEXT: {{ $}} + ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; NO-PREFER-W-INST-NEXT: [[LD:%[0-9]+]]:gpr = LD [[COPY]], 0 :: (load (s64)) + ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LD]], 1 + ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; NO-PREFER-W-INST-NEXT: PseudoRET + ; + ; PREFER-W-INST-LABEL: name: ld + ; PREFER-W-INST: liveins: $x10, $x11 + ; PREFER-W-INST-NEXT: {{ $}} + ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; PREFER-W-INST-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s64)) + ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LW]], 1 + ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; PREFER-W-INST-NEXT: PseudoRET + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = LD %1, 0 :: (load (s64)) + %4:gpr = ADDIW %3, 1 + $x10 = COPY %4 + PseudoRET +... + +--- +name: ld_volatile +body: | + bb.0.entry: + liveins: $x10, $x11 + ; NO-PREFER-W-INST-LABEL: name: ld_volatile + ; NO-PREFER-W-INST: liveins: $x10, $x11 + ; NO-PREFER-W-INST-NEXT: {{ $}} + ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; NO-PREFER-W-INST-NEXT: [[LD:%[0-9]+]]:gpr = LD [[COPY]], 0 :: (volatile load (s64)) + ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LD]], 1 + ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; NO-PREFER-W-INST-NEXT: PseudoRET + ; + ; PREFER-W-INST-LABEL: name: ld_volatile + ; PREFER-W-INST: liveins: $x10, $x11 + ; PREFER-W-INST-NEXT: {{ $}} + ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; PREFER-W-INST-NEXT: [[LD:%[0-9]+]]:gpr = LD [[COPY]], 0 :: (volatile load (s64)) + ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LD]], 1 + ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; PREFER-W-INST-NEXT: PseudoRET + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = LD %1, 0 :: (volatile load (s64)) + %4:gpr = ADDIW %3, 1 + $x10 = COPY %4 + PseudoRET +... + + +--- +name: lwu +body: | + bb.0.entry: + liveins: $x10, $x11 + ; NO-PREFER-W-INST-LABEL: name: lwu + ; NO-PREFER-W-INST: liveins: $x10, $x11 + ; NO-PREFER-W-INST-NEXT: {{ $}} + ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; NO-PREFER-W-INST-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LW]], 1 + ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; NO-PREFER-W-INST-NEXT: PseudoRET + ; + ; PREFER-W-INST-LABEL: name: lwu + ; PREFER-W-INST: liveins: $x10, $x11 + ; PREFER-W-INST-NEXT: {{ $}} + ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; PREFER-W-INST-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LW]], 1 + ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]] + ; PREFER-W-INST-NEXT: PseudoRET + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = LWU %1, 0 :: (load (s32)) + %4:gpr = ADDIW %3, 1 + $x10 = COPY %4 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rda-entry-bb-is-a-loop.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rda-entry-bb-is-a-loop.mir new file mode 100644 index 0000000..0f56e90 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rda-entry-bb-is-a-loop.mir @@ -0,0 +1,26 @@ +# RUN: llc %s -mtriple=riscv64 --passes='print' -o - 2>&1 | FileCheck %s +--- +name: entry_bb_is_a_loop +tracksRegLiveness: true +body: | + ; CHECK-LABEL: Reaching definitions for for machine function: entry_bb_is_a_loop + ; CHECK-NEXT: %bb.0: + ; CHECK-NEXT: $x10:{ 1 } + ; CHECK-NEXT: 0: $x10 = ADDI $x10, 1 + ; CHECK-EMPTY: + ; CHECK-NEXT: $x10:{ 0 } + ; CHECK-NEXT: 1: $x10 = ADDI $x10, 2 + ; CHECK-EMPTY: + ; CHECK-NEXT: $x10:{ 1 } + ; CHECK-NEXT: $x0:{ } + ; CHECK-NEXT: 2: BNE $x10, $x0, %bb.0 + bb.0.entry: + liveins: $x10 + $x10 = ADDI $x10, 1 + $x10 = ADDI $x10, 2 + BNE $x10, $x0, %bb.0 + + bb.1: + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rda-liveins.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rda-liveins.mir new file mode 100644 index 0000000..ff7c9ef --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rda-liveins.mir @@ -0,0 +1,117 @@ +# RUN: llc %s -mtriple=riscv64 --passes='print' -o - 2>&1 | FileCheck %s + +--- +name: test0 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: Reaching definitions for for machine function: test0 + ; CHECK-NEXT: %bb.0: + ; CHECK-NEXT: implicit $x10:{ } + ; CHECK-NEXT: 0: PseudoRET implicit $x10 + + bb.0.entry: + liveins: $x10 + PseudoRET implicit $x10 + +... + +--- +name: test1 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: Reaching definitions for for machine function: test1 + ; CHECK-NEXT: %bb.0: + ; CHECK-NEXT: $x10:{ } + ; CHECK-NEXT: 0: $x10 = ADDI $x10, 1 + ; CHECK-EMPTY: + ; CHECK-NEXT: implicit $x10:{ 0 } + ; CHECK-NEXT: 1: PseudoRET implicit $x10 + bb.0.entry: + liveins: $x10 + $x10 = ADDI $x10, 1 + PseudoRET implicit $x10 + +... + +--- +name: test2 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: Reaching definitions for for machine function: test2 + ; CHECK-NEXT: %bb.0: + ; CHECK-NEXT: $x10:{ } + ; CHECK-NEXT: $x0:{ } + ; CHECK-NEXT: 0: BEQ $x10, $x0, %bb.2 + ; CHECK-EMPTY: + ; CHECK-NEXT: %bb.1: + ; CHECK-NEXT: $x10:{ } + ; CHECK-NEXT: 1: $x10 = ADDI $x10, 1 + ; CHECK-EMPTY: + ; CHECK-NEXT: implicit $x10:{ 1 } + ; CHECK-NEXT: 2: PseudoRET implicit $x10 + ; CHECK-EMPTY: + ; CHECK-NEXT: %bb.2 + ; CHECK-NEXT: implicit $x10:{ } + ; CHECK-NEXT: 3: PseudoRET implicit $x10 + bb.0.entry: + liveins: $x10 + BEQ $x10, $x0, %bb.2 + + bb.1: + liveins: $x10 + $x10 = ADDI $x10, 1 + PseudoRET implicit $x10 + + bb.2: + liveins: $x10 + PseudoRET implicit $x10 +... + +--- +name: test3 +tracksRegLiveness: true +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + ; CHECK-LABEL: Reaching definitions for for machine function: test3 + ; CHECK-NEXT: %bb.0: + ; CHECK-NEXT: $x10:{ } + ; CHECK-NEXT: $x0:{ } + ; CHECK-NEXT: 0: BEQ $x10, $x0, %bb.2 + ; CHECK-EMPTY: + ; CHECK-NEXT: %bb.1: + ; CHECK-NEXT: $x10:{ } + ; CHECK-NEXT: 1: $x10 = ADDI $x10, 1 + ; CHECK-EMPTY: + ; CHECK-NEXT: 2: PseudoBR %bb.3 + ; CHECK-EMPTY: + ; CHECK-NEXT: %bb.2: + ; CHECK-NEXT: $x10:{ } + ; CHECK-NEXT: %stack.0:{ } + ; CHECK-NEXT: 3: SD $x10, %stack.0, 0 :: (store (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: 4: PseudoBR %bb.3 + ; CHECK-EMPTY: + ; CHECK-NEXT: %bb.3: + ; CHECK-NEXT: implicit $x10:{ 1 } + ; CHECK-NEXT: 5: PseudoRET implicit $x10 + bb.0.entry: + liveins: $x10 + BEQ $x10, $x0, %bb.2 + + bb.1: + liveins: $x10 + $x10 = ADDI $x10, 1 + PseudoBR %bb.3 + + bb.2: + liveins: $x10 + SD $x10, %stack.0, 0 :: (store (s64)) + PseudoBR %bb.3 + + bb.3: + liveins: $x10 + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rda-stack.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rda-stack.mir new file mode 100644 index 0000000..367c450 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rda-stack.mir @@ -0,0 +1,197 @@ +# RUN: llc %s -mtriple=riscv64 --passes='print' -o - 2>&1 | FileCheck %s + +--- +name: test0 +tracksRegLiveness: true +stack: + - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + ; CHECK-LABEL: Reaching definitions for for machine function: test0 + ; CHECK-NEXT: %bb.0: + ; CHECK-NEXT: %stack.0:{ } + ; CHECK-NEXT:0: $x10 = LD %stack.0, 0 :: (load (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: implicit $x10:{ 0 } + ; CHECK-NEXT:1: PseudoRET implicit $x10 + + bb.0.entry: + $x10 = LD %stack.0, 0 :: (load (s64)) + PseudoRET implicit $x10 + +... +--- +name: test1 +tracksRegLiveness: true +stack: + - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + ; CHECK-LABEL: Reaching definitions for for machine function: test1 + ; CHECK-NEXT: %bb.0: + ; CHECK-NEXT: %stack.0:{ } + ; CHECK-NEXT: 0: $x10 = LD %stack.0, 0 :: (load (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: %stack.1:{ } + ; CHECK-NEXT: 1: $x11 = LD %stack.1, 0 :: (load (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: $x10:{ 0 } + ; CHECK-NEXT: $x11:{ 1 } + ; CHECK-NEXT: 2: $x10 = ADD $x10, $x11 + ; CHECK-EMPTY: + ; CHECK-NEXT: implicit $x10:{ 2 } + ; CHECK-NEXT: 3: PseudoRET implicit $x10 + + bb.0.entry: + $x10 = LD %stack.0, 0 :: (load (s64)) + $x11 = LD %stack.1, 0 :: (load (s64)) + $x10 = ADD $x10, $x11 + PseudoRET implicit $x10 + +... +--- +name: test2 +tracksRegLiveness: true +stack: + - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + ; CHECK-LABEL: Reaching definitions for for machine function: test2 + ; CHECK-NEXT: %bb.0: + ; CHECK-NEXT: %stack.0:{ } + ; CHECK-NEXT: 0: $x10 = LD %stack.0, 0 :: (load (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: %stack.1:{ } + ; CHECK-NEXT: 1: $x11 = LD %stack.1, 0 :: (load (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: $x10:{ 0 } + ; CHECK-NEXT: $x11:{ 1 } + ; CHECK-NEXT: 2: $x10 = ADD $x10, $x11 + ; CHECK-EMPTY: + ; CHECK-NEXT: $x10:{ 2 } + ; CHECK-NEXT: %stack.0:{ } + ; CHECK-NEXT: 3: SD $x10, %stack.0, 0 :: (store (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: %stack.0:{ 3 } + ; CHECK-NEXT: 4: $x10 = LD %stack.0, 0 :: (load (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: implicit $x10:{ 4 } + ; CHECK-NEXT: 5: PseudoRET implicit $x10 + + bb.0.entry: + $x10 = LD %stack.0, 0 :: (load (s64)) + $x11 = LD %stack.1, 0 :: (load (s64)) + $x10 = ADD $x10, $x11 + SD $x10, %stack.0, 0 :: (store (s64)) + $x10 = LD %stack.0, 0 :: (load (s64)) + PseudoRET implicit $x10 + +... +--- +name: test3 +tracksRegLiveness: true +stack: + - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + ; CHECK-LABEL: Reaching definitions for for machine function: test3 + ; CHECK-NEXT: %bb.0: + ; CHECK-NEXT: $x10:{ } + ; CHECK-NEXT: $x0:{ } + ; CHECK-NEXT: 0: BEQ $x10, $x0, %bb.2 + ; CHECK-EMPTY: + ; CHECK-NEXT: %bb.1: + ; CHECK-NEXT: $x10:{ } + ; CHECK-NEXT: 1: $x10 = ADDI $x10, 1 + ; CHECK-EMPTY: + ; CHECK-NEXT: $x10:{ 1 } + ; CHECK-NEXT: %stack.0:{ } + ; CHECK-NEXT: 2: SD $x10, %stack.0, 0 :: (store (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: 3: PseudoBR %bb.3 + ; CHECK-EMPTY: + ; CHECK-NEXT: %bb.2: + ; CHECK-NEXT: $x10:{ } + ; CHECK-NEXT: 4: $x10 = ADDI $x10, 2 + ; CHECK-EMPTY: + ; CHECK-NEXT: $x10:{ 4 } + ; CHECK-NEXT: %stack.0:{ } + ; CHECK-NEXT: 5: SD $x10, %stack.0, 0 :: (store (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: %bb.3: + ; CHECK-NEXT: %stack.0:{ 2 5 } + ; CHECK-NEXT: 6: $x10 = LD %stack.0, 0 :: (load (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: implicit $x10:{ 6 } + ; CHECK-NEXT: 7: PseudoRET implicit $x10 + + bb.0.entry: + liveins: $x10 + BEQ $x10, $x0, %bb.2 + + bb.1: + liveins: $x10 + $x10 = ADDI $x10, 1 + SD $x10, %stack.0, 0 :: (store (s64)) + PseudoBR %bb.3 + + bb.2: + liveins: $x10 + $x10 = ADDI $x10, 2 + SD $x10, %stack.0, 0 :: (store (s64)) + + bb.3: + $x10 = LD %stack.0, 0 :: (load (s64)) + PseudoRET implicit $x10 +... +--- +name: test4 +tracksRegLiveness: true +fixedStack: + - { id: 0, type: default, offset: 0, size: 4, alignment: 16, + isImmutable: true, isAliased: false } +stack: + - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + ; CHECK-LABEL: Reaching definitions for for machine function: test4 + ; CHECK-NEXT: %bb.0: + ; CHECK-NEXT: $x10:{ } + ; CHECK-NEXT: %stack.0:{ } + ; CHECK-NEXT: 0: SD $x10, %stack.0, 0 :: (store (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: $x11:{ } + ; CHECK-NEXT: %stack.0:{ 0 } + ; CHECK-NEXT: 1: SD $x11, %stack.0, 0 :: (store (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: $x10:{ } + ; CHECK-NEXT: %stack.1:{ } + ; CHECK-NEXT: 2: SD $x10, %stack.1, 0 :: (store (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: $x11:{ } + ; CHECK-NEXT: %stack.1:{ 2 } + ; CHECK-NEXT: 3: SD $x11, %stack.1, 0 :: (store (s64)) + ; CHECK-EMPTY: + ; CHECK-NEXT: 4: PseudoRET + bb.0.entry: + liveins: $x10, $x11 + SD $x10, %stack.0, 0 :: (store (s64)) + SD $x11, %stack.0, 0 :: (store (s64)) + SD $x10, %stack.1, 0 :: (store (s64)) + SD $x11, %stack.1, 0 :: (store (s64)) + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/renamable-copy.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/renamable-copy.mir new file mode 100644 index 0000000..06f17f4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/renamable-copy.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -o - %s -mtriple=riscv32 -simplify-mir \ +# RUN: -run-pass=postrapseudos | FileCheck --check-prefix=RV32 %s +# RUN: llc -o - %s -mtriple=riscv64 -simplify-mir \ +# RUN: -run-pass=postrapseudos | FileCheck --check-prefix=RV64 %s + +--- | + define void @foo() { + entry: + ret void + } +... +--- +name: foo +body: | + bb.0.entry: + liveins: $x11 + ; RV32-LABEL: name: foo + ; RV32: liveins: $x11 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: $x10 = ADDI renamable $x11, 0 + ; RV32-NEXT: PseudoRET implicit $x10 + ; + ; RV64-LABEL: name: foo + ; RV64: liveins: $x11 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: $x10 = ADDI renamable $x11, 0 + ; RV64-NEXT: PseudoRET implicit $x10 + renamable $x10 = COPY renamable $x11 + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir new file mode 100644 index 0000000..5619099 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir @@ -0,0 +1,213 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=riscv32 -run-pass=prologepilog -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: main +alignment: 2 +tracksRegLiveness: true +frameInfo: + maxAlignment: 4 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 2276 +stack: + - { id: 0, name: '', type: default, offset: 0, size: 2304, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + local-offset: -2304, debug-info-variable: '', debug-info-expression: '', + debug-info-location: '' } + - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: spill-slot, offset: 0, size: 2204, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: spill-slot, offset: 0, size: 2204, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.0: + ; CHECK-LABEL: name: main + ; CHECK: liveins: $x1, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -2032 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-NEXT: frame-setup SW killed $x1, $x2, 2028 :: (store (s32) into %stack.4) + ; CHECK-NEXT: frame-setup SW killed $x8, $x2, 2024 :: (store (s32) into %stack.5) + ; CHECK-NEXT: frame-setup SW killed $x9, $x2, 2020 :: (store (s32) into %stack.6) + ; CHECK-NEXT: frame-setup SW killed $x18, $x2, 2016 :: (store (s32) into %stack.7) + ; CHECK-NEXT: frame-setup SW killed $x19, $x2, 2012 :: (store (s32) into %stack.8) + ; CHECK-NEXT: frame-setup SW killed $x20, $x2, 2008 :: (store (s32) into %stack.9) + ; CHECK-NEXT: frame-setup SW killed $x21, $x2, 2004 :: (store (s32) into %stack.10) + ; CHECK-NEXT: frame-setup SW killed $x22, $x2, 2000 :: (store (s32) into %stack.11) + ; CHECK-NEXT: frame-setup SW killed $x23, $x2, 1996 :: (store (s32) into %stack.12) + ; CHECK-NEXT: frame-setup SW killed $x24, $x2, 1992 :: (store (s32) into %stack.13) + ; CHECK-NEXT: frame-setup SW killed $x25, $x2, 1988 :: (store (s32) into %stack.14) + ; CHECK-NEXT: frame-setup SW killed $x26, $x2, 1984 :: (store (s32) into %stack.15) + ; CHECK-NEXT: frame-setup SW killed $x27, $x2, 1980 :: (store (s32) into %stack.16) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -28 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -36 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -40 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -44 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -48 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -52 + ; CHECK-NEXT: $x8 = frame-setup ADDI $x2, 2032 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0 + ; CHECK-NEXT: $x10 = frame-setup LUI 2 + ; CHECK-NEXT: $x10 = frame-setup ADDI killed $x10, -1168 + ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10 + ; CHECK-NEXT: renamable $x10 = ADDI $x8, -440 + ; CHECK-NEXT: $x11 = LUI 2 + ; CHECK-NEXT: $x11 = SUB $x8, killed $x11 + ; CHECK-NEXT: $x11 = LW killed $x11, 1420 + ; CHECK-NEXT: renamable $x12 = LW undef renamable $x10, 1 + ; CHECK-NEXT: renamable $x13 = LW undef renamable $x10, 9 + ; CHECK-NEXT: renamable $x14 = LW undef renamable $x10, 13 + ; CHECK-NEXT: renamable $x15 = LW undef renamable $x10, 17 + ; CHECK-NEXT: renamable $x16 = LW undef renamable $x10, 21 + ; CHECK-NEXT: renamable $x17 = LW undef renamable $x10, 25 + ; CHECK-NEXT: renamable $x5 = LW undef renamable $x10, 29 + ; CHECK-NEXT: renamable $x6 = LW undef renamable $x10, 33 + ; CHECK-NEXT: renamable $x7 = LW undef renamable $x10, 37 + ; CHECK-NEXT: renamable $x28 = LW undef renamable $x10, 41 + ; CHECK-NEXT: renamable $x29 = LW undef renamable $x10, 45 + ; CHECK-NEXT: renamable $x30 = LW undef renamable $x10, 49 + ; CHECK-NEXT: renamable $x31 = LW undef renamable $x10, 53 + ; CHECK-NEXT: renamable $x9 = LW undef renamable $x10, 61 + ; CHECK-NEXT: renamable $x18 = LW undef renamable $x10, 65 + ; CHECK-NEXT: renamable $x19 = LW undef renamable $x10, 69 + ; CHECK-NEXT: renamable $x20 = LW undef renamable $x10, 73 + ; CHECK-NEXT: renamable $x21 = LW undef renamable $x10, 77 + ; CHECK-NEXT: renamable $x22 = LW undef renamable $x10, 81 + ; CHECK-NEXT: renamable $x23 = LW undef renamable $x10, 85 + ; CHECK-NEXT: renamable $x24 = LW undef renamable $x10, 89 + ; CHECK-NEXT: renamable $x25 = LW undef renamable $x10, 93 + ; CHECK-NEXT: renamable $x26 = LW undef renamable $x10, 97 + ; CHECK-NEXT: renamable $x27 = LW undef renamable $x10, 101 + ; CHECK-NEXT: renamable $x1 = LW undef renamable $x10, 105 + ; CHECK-NEXT: SW killed $x11, $x8, -56 :: (store (s32) into %stack.17) + ; CHECK-NEXT: $x11 = LUI 1 + ; CHECK-NEXT: $x11 = SUB $x8, killed $x11 + ; CHECK-NEXT: SW $x10, killed $x11, -472 + ; CHECK-NEXT: $x11 = LW $x8, -56 :: (load (s32) from %stack.17) + ; CHECK-NEXT: SW killed renamable $x1, undef renamable $x11, 105 + ; CHECK-NEXT: SW killed renamable $x27, undef renamable $x11, 101 + ; CHECK-NEXT: SW killed renamable $x26, renamable $x11, 97 + ; CHECK-NEXT: SW killed renamable $x25, undef renamable $x11, 93 + ; CHECK-NEXT: SW killed renamable $x24, undef renamable $x11, 89 + ; CHECK-NEXT: SW killed renamable $x23, undef renamable $x11, 85 + ; CHECK-NEXT: SW killed renamable $x22, undef renamable $x11, 81 + ; CHECK-NEXT: SW killed renamable $x21, undef renamable $x11, 77 + ; CHECK-NEXT: SW killed renamable $x20, undef renamable $x11, 73 + ; CHECK-NEXT: SW killed renamable $x19, undef renamable $x11, 69 + ; CHECK-NEXT: SW killed renamable $x18, undef renamable $x11, 65 + ; CHECK-NEXT: SW killed renamable $x9, undef renamable $x11, 61 + ; CHECK-NEXT: SW killed renamable $x31, undef renamable $x11, 53 + ; CHECK-NEXT: SW killed renamable $x30, undef renamable $x11, 49 + ; CHECK-NEXT: SW killed renamable $x29, undef renamable $x11, 45 + ; CHECK-NEXT: SW killed renamable $x28, undef renamable $x11, 41 + ; CHECK-NEXT: SW killed renamable $x7, undef renamable $x11, 37 + ; CHECK-NEXT: SW killed renamable $x6, undef renamable $x11, 33 + ; CHECK-NEXT: SW killed renamable $x5, undef renamable $x11, 29 + ; CHECK-NEXT: SW killed renamable $x17, undef renamable $x11, 25 + ; CHECK-NEXT: SW killed renamable $x16, undef renamable $x11, 21 + ; CHECK-NEXT: SW killed renamable $x15, undef renamable $x11, 17 + ; CHECK-NEXT: SW killed renamable $x14, undef renamable $x11, 13 + ; CHECK-NEXT: SW killed renamable $x13, undef renamable $x11, 9 + ; CHECK-NEXT: SW killed renamable $x12, undef renamable $x11, 5 + ; CHECK-NEXT: $x10 = frame-destroy LUI 2 + ; CHECK-NEXT: $x10 = frame-destroy ADDI killed $x10, -1168 + ; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 2032 + ; CHECK-NEXT: $x1 = frame-destroy LW $x2, 2028 :: (load (s32) from %stack.4) + ; CHECK-NEXT: $x8 = frame-destroy LW $x2, 2024 :: (load (s32) from %stack.5) + ; CHECK-NEXT: $x9 = frame-destroy LW $x2, 2020 :: (load (s32) from %stack.6) + ; CHECK-NEXT: $x18 = frame-destroy LW $x2, 2016 :: (load (s32) from %stack.7) + ; CHECK-NEXT: $x19 = frame-destroy LW $x2, 2012 :: (load (s32) from %stack.8) + ; CHECK-NEXT: $x20 = frame-destroy LW $x2, 2008 :: (load (s32) from %stack.9) + ; CHECK-NEXT: $x21 = frame-destroy LW $x2, 2004 :: (load (s32) from %stack.10) + ; CHECK-NEXT: $x22 = frame-destroy LW $x2, 2000 :: (load (s32) from %stack.11) + ; CHECK-NEXT: $x23 = frame-destroy LW $x2, 1996 :: (load (s32) from %stack.12) + ; CHECK-NEXT: $x24 = frame-destroy LW $x2, 1992 :: (load (s32) from %stack.13) + ; CHECK-NEXT: $x25 = frame-destroy LW $x2, 1988 :: (load (s32) from %stack.14) + ; CHECK-NEXT: $x26 = frame-destroy LW $x2, 1984 :: (load (s32) from %stack.15) + ; CHECK-NEXT: $x27 = frame-destroy LW $x2, 1980 :: (load (s32) from %stack.16) + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x9 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x18 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x19 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x20 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x21 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x22 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x23 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x24 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x25 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x26 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x27 + ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NEXT: PseudoRET + renamable $x10 = ADDI %stack.0, 1920 + ADJCALLSTACKDOWN 2276, 0, implicit-def dead $x2, implicit $x2 + $x11 = LW %stack.3, 0 + ADJCALLSTACKUP 2276, 0, implicit-def dead $x2, implicit $x2 + renamable $x12 = LW undef renamable $x10, 1 + renamable $x13 = LW undef renamable $x10, 9 + renamable $x14 = LW undef renamable $x10, 13 + renamable $x15 = LW undef renamable $x10, 17 + renamable $x16 = LW undef renamable $x10, 21 + renamable $x17 = LW undef renamable $x10, 25 + renamable $x5 = LW undef renamable $x10, 29 + renamable $x6 = LW undef renamable $x10, 33 + renamable $x7 = LW undef renamable $x10, 37 + renamable $x28 = LW undef renamable $x10, 41 + renamable $x29 = LW undef renamable $x10, 45 + renamable $x30 = LW undef renamable $x10, 49 + renamable $x31 = LW undef renamable $x10, 53 + renamable $x9 = LW undef renamable $x10, 61 + renamable $x18 = LW undef renamable $x10, 65 + renamable $x19 = LW undef renamable $x10, 69 + renamable $x20 = LW undef renamable $x10, 73 + renamable $x21 = LW undef renamable $x10, 77 + renamable $x22 = LW undef renamable $x10, 81 + renamable $x23 = LW undef renamable $x10, 85 + renamable $x24 = LW undef renamable $x10, 89 + renamable $x25 = LW undef renamable $x10, 93 + renamable $x26 = LW undef renamable $x10, 97 + renamable $x27 = LW undef renamable $x10, 101 + renamable $x1 = LW undef renamable $x10, 105 + SW $x10, %stack.2, 0 + SW killed renamable $x1, undef renamable $x11, 105 + SW killed renamable $x27, undef renamable $x11, 101 + SW killed renamable $x26, renamable $x11, 97 + SW killed renamable $x25, undef renamable $x11, 93 + SW killed renamable $x24, undef renamable $x11, 89 + SW killed renamable $x23, undef renamable $x11, 85 + SW killed renamable $x22, undef renamable $x11, 81 + SW killed renamable $x21, undef renamable $x11, 77 + SW killed renamable $x20, undef renamable $x11, 73 + SW killed renamable $x19, undef renamable $x11, 69 + SW killed renamable $x18, undef renamable $x11, 65 + SW killed renamable $x9, undef renamable $x11, 61 + SW killed renamable $x31, undef renamable $x11, 53 + SW killed renamable $x30, undef renamable $x11, 49 + SW killed renamable $x29, undef renamable $x11, 45 + SW killed renamable $x28, undef renamable $x11, 41 + SW killed renamable $x7, undef renamable $x11, 37 + SW killed renamable $x6, undef renamable $x11, 33 + SW killed renamable $x5, undef renamable $x11, 29 + SW killed renamable $x17, undef renamable $x11, 25 + SW killed renamable $x16, undef renamable $x11, 21 + SW killed renamable $x15, undef renamable $x11, 17 + SW killed renamable $x14, undef renamable $x11, 13 + SW killed renamable $x13, undef renamable $x11, 9 + SW killed renamable $x12, undef renamable $x11, 5 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv64.mir new file mode 100644 index 0000000..7d8cf08 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv64.mir @@ -0,0 +1,109 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=riscv64 -run-pass=prologepilog -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: test +alignment: 4 +tracksRegLiveness: true +noPhis: true +isSSA: true +noVRegs: true +frameInfo: + maxAlignment: 8 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 4808 +stack: + - { id: 0, name: '', type: spill-slot, offset: 0, size: 104, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + ; CHECK-LABEL: name: test + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.5(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -2032 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-NEXT: frame-setup SD killed $x1, $x2, 2024 :: (store (s64) into %stack.1) + ; CHECK-NEXT: frame-setup SD killed $x8, $x2, 2016 :: (store (s64) into %stack.2) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-NEXT: $x8 = frame-setup ADDI $x2, 2032 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0 + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -2048 + ; CHECK-NEXT: $x2 = frame-setup ADDI killed $x2, -864 + ; CHECK-NEXT: BEQ undef renamable $x10, $x0, %bb.5 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: liveins: $x11, $x30 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000) + ; CHECK-NEXT: liveins: $x6, $x8, $x9, $x10, $x11, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x28, $x31, $x30 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SD undef renamable $x23, $x8, -128 + ; CHECK-NEXT: BEQ undef renamable $x30, $x0, %bb.3 + ; CHECK-NEXT: PseudoBR %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $x1, $x5, $x7, $x11, $x12, $x13, $x14, $x15, $x16, $x25, $x26, $x27, $x29, $x30 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-NEXT: $x2 = frame-destroy ADDI killed $x2, 880 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 2032 + ; CHECK-NEXT: $x1 = frame-destroy LD $x2, 2024 :: (load (s64) from %stack.1) + ; CHECK-NEXT: $x8 = frame-destroy LD $x2, 2016 :: (load (s64) from %stack.2) + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.1(0x40000000), %bb.5(0x40000000) + liveins: $x10, $x11, $x12 + + BEQ undef renamable $x10, $x0, %bb.5 + PseudoBR %bb.1 + + bb.1: + successors: %bb.2(0x80000000) + liveins: $x10, $x11, $x12 + + bb.2: + successors: %bb.3(0x80000000) + liveins: $x11, $x30 + + bb.3: + successors: %bb.4(0x04000000), %bb.3(0x7c000000) + liveins: $x6, $x8, $x9, $x10, $x11, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x28, $x31, $x30 + + SD undef renamable $x23, %stack.0, 0 + BEQ undef renamable $x30, $x0, %bb.3 + PseudoBR %bb.4 + + bb.4: + successors: %bb.2(0x80000000) + liveins: $x1, $x5, $x7, $x11, $x12, $x13, $x14, $x15, $x16, $x25, $x26, $x27, $x29, $x30 + + PseudoBR %bb.2 + + bb.5: + liveins: $x10 + + ADJCALLSTACKDOWN 4808, 0, implicit-def dead $x2, implicit $x2 + ADJCALLSTACKUP 4808, 0, implicit-def dead $x2, implicit $x2 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rv32-merge-non-arg-reg.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rv32-merge-non-arg-reg.mir new file mode 100644 index 0000000..ab3de8c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rv32-merge-non-arg-reg.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=riscv32 -mattr=+zdinx -run-pass=postrapseudos,riscv-move-merge %s -o - | FileCheck %s --check-prefix=ZDINX +# RUN: llc -mtriple=riscv32 -mattr=+experimental-p -run-pass=postrapseudos,riscv-move-merge %s -o - | FileCheck %s --check-prefix=P-EXT + +... +--- +name: merge_copy_non_arg_reg +tracksRegLiveness: true +body: | + bb.0: + liveins: $x28, $x29 + ; ZDINX-LABEL: name: merge_copy_non_arg_reg + ; ZDINX: liveins: $x28, $x29 + ; ZDINX-NEXT: {{ $}} + ; ZDINX-NEXT: $x6_x7 = FSGNJ_D_IN32X $x28_x29, $x28_x29 + ; ZDINX-NEXT: PseudoRET implicit $x6 + ; + ; P-EXT-LABEL: name: merge_copy_non_arg_reg + ; P-EXT: liveins: $x28, $x29 + ; P-EXT-NEXT: {{ $}} + ; P-EXT-NEXT: $x6_x7 = PADD_DW $x28_x29, $x0_pair + ; P-EXT-NEXT: PseudoRET implicit $x6 + $x6 = COPY $x28 + $x7 = COPY $x29 + PseudoRET implicit $x6 +... +--- +name: merge_copy_non_arg_reg_with_intervening_unrelated_copy +tracksRegLiveness: true +body: | + bb.0: + liveins: $x12, $x28, $x29 + ; ZDINX-LABEL: name: merge_copy_non_arg_reg_with_intervening_unrelated_copy + ; ZDINX: liveins: $x12, $x28, $x29 + ; ZDINX-NEXT: {{ $}} + ; ZDINX-NEXT: $x6_x7 = FSGNJ_D_IN32X $x28_x29, $x28_x29 + ; ZDINX-NEXT: $x18 = ADDI $x12, 0 + ; ZDINX-NEXT: PseudoRET implicit $x6 + ; + ; P-EXT-LABEL: name: merge_copy_non_arg_reg_with_intervening_unrelated_copy + ; P-EXT: liveins: $x12, $x28, $x29 + ; P-EXT-NEXT: {{ $}} + ; P-EXT-NEXT: $x6_x7 = PADD_DW $x28_x29, $x0_pair + ; P-EXT-NEXT: $x18 = ADDI $x12, 0 + ; P-EXT-NEXT: PseudoRET implicit $x6 + $x6 = COPY $x28 + $x18 = COPY $x12 + $x7 = COPY $x29 + PseudoRET implicit $x6 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir new file mode 100644 index 0000000..64430c9 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir @@ -0,0 +1,60 @@ +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass prologepilog %s -o - | FileCheck %s +--- | + declare void @extern(ptr) #0 + + define void @addi_rvv_stack_object() #0 { + %local0 = alloca , align 16 + call void @extern(ptr %local0) + ret void + } + + attributes #0 = { "target-features"="+v" } + +... +--- +name: addi_rvv_stack_object +alignment: 4 +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 16 + adjustsStack: true + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: [] + restorePoint: [] +fixedStack: [] +stack: + - { id: 0, name: local0, type: default, offset: 0, size: 16, alignment: 16, + stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +# CHECK: - { id: 2, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8, +# CHECK: stack-id: default, callee-saved-register: '', callee-saved-restored: true, +# CHECK: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0 (%ir-block.0): + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + $x10 = ADDI %stack.0.local0, 0 + PseudoCALL target-flags(riscv-call) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir new file mode 100644 index 0000000..c733ddf --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir @@ -0,0 +1,65 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s + +--- | + define void @add_scalable_offset( + ptr %pa, + i64 %vl) + { + ret void + } +... +--- +name: add_scalable_offset +tracksRegLiveness: true +frameInfo: + isFrameAddressTaken: true + stackSize: 2240 +stack: + - { id: 0, type: default, offset: 0, size: 1120, alignment: 4, + stack-id: default } + - { id: 1, type: default, offset: 1120, size: 1120, alignment: 4, + stack-id: default } + - { id: 2, offset: 0, size: 8, alignment: 8, stack-id: scalable-vector } +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: add_scalable_offset + ; CHECK: liveins: $x10, $x11, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -2032 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-NEXT: frame-setup SD killed $x1, $x2, 2024 :: (store (s64) into %stack.3) + ; CHECK-NEXT: frame-setup SD killed $x8, $x2, 2016 :: (store (s64) into %stack.4) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-NEXT: $x8 = frame-setup ADDI $x2, 2032 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0 + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -240 + ; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB + ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, killed renamable $x10, $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) + ; CHECK-NEXT: $x10 = PseudoReadVLENB + ; CHECK-NEXT: $x10 = SUB $x8, killed $x10 + ; CHECK-NEXT: $x10 = ADDI killed $x10, -2048 + ; CHECK-NEXT: $x10 = ADDI killed $x10, -224 + ; CHECK-NEXT: VS1R_V killed renamable $v8, killed renamable $x10 + ; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2032 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 2032 + ; CHECK-NEXT: $x1 = frame-destroy LD $x2, 2024 :: (load (s64) from %stack.3) + ; CHECK-NEXT: $x8 = frame-destroy LD $x2, 2016 :: (load (s64) from %stack.4) + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NEXT: PseudoRET + %1:gprnox0 = COPY $x11 + %0:gpr = COPY $x10 + %2:vr = PseudoVLE64_V_M1 undef $noreg, %0, %1, 6, 0 :: (load unknown-size from %ir.pa, align 8) + %3:gpr = ADDI %stack.2, 0 + VS1R_V killed %2:vr, %3:gpr + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/aliases.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/aliases.mir new file mode 100644 index 0000000..f39b0c7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/aliases.mir @@ -0,0 +1,61 @@ +# RUN: llc -mtriple riscv32 -mattr=+v -start-after riscv-expand-pseudo -o - %s | FileCheck %s +# RUN: llc -mtriple riscv64 -mattr=+v -start-after riscv-expand-pseudo -o - %s | FileCheck %s + +--- | + define void @vnot_mask_1() { + ret void + } + define void @vnot_mask_2() { + ret void + } + define void @vnot_no_mask_1() { + ret void + } + define void @vnot_no_mask_2() { + ret void + } +... +--- +name: vnot_mask_1 +body: | + bb.0: + liveins: $v0, $v25 + + ; CHECK-LABEL: vnot_mask_1: + ; CHECK: vnot.v v25, v25, v0.t + + $v25 = VXOR_VI killed $v25, -1, $v0, implicit $vtype, implicit $vl +... +--- +name: vnot_mask_2 +body: | + bb.0: + liveins: $v0, $v25 + + ; CHECK-LABEL: vnot_mask_2: + ; CHECK: vnot.v v1, v25, v0.t + + $v1 = VXOR_VI killed $v25, -1, $v0, implicit $vtype, implicit $vl +... +--- +name: vnot_no_mask_1 +body: | + bb.0: + liveins: $v25 + + ; CHECK-LABEL: vnot_no_mask_1: + ; CHECK: vnot.v v25, v25 + + $v25 = VXOR_VI killed $v25, -1, $noreg, implicit $vtype, implicit $vl +... +--- +name: vnot_no_mask_2 +body: | + bb.0: + liveins: $v25 + + ; CHECK-LABEL: vnot_no_mask_2: + ; CHECK: vnot.v v1, v25 + + $v1 = VXOR_VI killed $v25, -1, $noreg, implicit $vtype, implicit $vl +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.mir new file mode 100644 index 0000000..408d533 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.mir @@ -0,0 +1,16 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole -verify-machineinstrs | FileCheck %s + +# Take into account that the masked vcpop pseudo doesn't have a passthru +--- +name: vcpop.m +body: | + bb.0: + ; CHECK-LABEL: name: vcpop.m + ; CHECK: %allones:vr = PseudoVMSET_M_B64 $noreg /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY %allones + ; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 $noreg, 21 /* vl */, 0 /* e8 */ + %allones:vr = PseudoVMSET_M_B64 $noreg, 0 + $v0 = COPY %allones + %2:gpr = PseudoVCPOP_M_B64_MASK $noreg, $v0, 21, 0 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir new file mode 100644 index 0000000..0434fb9 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir @@ -0,0 +1,46 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=register-coalescer %s -o - 2>&1 | FileCheck %s + +# This test used to crash in the register coalescer when the target would +# return the out-of-bounds CommuteAnyOperandIndex for one of its commutable +# operand indices. + +--- | + target triple = "riscv64" + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" + + define void @commuted_op_indices() { + unreachable + } +... +--- +name: commuted_op_indices +tracksRegLiveness: true +registers: + - { id: 0, class: vr, preferred-register: '' } + - { id: 1, class: vrnov0, preferred-register: '' } + - { id: 2, class: vrnov0, preferred-register: '' } + - { id: 3, class: vr, preferred-register: '' } +body: | + bb.0: + liveins: $v0, $v1, $v2 + ; CHECK-LABEL: name: commuted_op_indices + ; CHECK: liveins: $v0, $v1, $v2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrnov0 = COPY $v1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrnov0 = COPY $v2 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = PseudoVNMSUB_VV_M1 [[COPY]], [[COPY1]], [[COPY2]], -1 /* vl=VLMAX */, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vr = COPY [[COPY]] + ; CHECK-NEXT: dead [[COPY3:%[0-9]+]]:vr = PseudoVSLL_VI_M1 undef [[COPY3]], [[COPY3]], 11, $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:vr = COPY $v0 + %1:vrnov0 = COPY $v1 + %2:vrnov0 = COPY $v2 + %0:vr = PseudoVNMSUB_VV_M1 %0, %1, killed %2, -1, 6, 1, implicit $vl, implicit $vtype + %3:vr = COPY %0 + %3:vr = PseudoVSLL_VI_M1 undef %3, %3, 11, $noreg, 6, 0, implicit $vl, implicit $vtype + $v0 = COPY %0 + PseudoRET implicit $v0 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/copyprop.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/copyprop.mir new file mode 100644 index 0000000..aba75ff --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/copyprop.mir @@ -0,0 +1,70 @@ +# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v,+xsfvcp -start-after=finalize-isel | FileCheck %s + +--- | + define void @foo() { + ; CHECK-LABEL: foo: + ; CHECK: # %bb.0: # %entry + ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma + ; CHECK-NEXT: sf.vc.v.x 3, 31, v9, a1 + ; CHECK-NEXT: bgeu a0, zero, .LBB0_3 + ; CHECK-NEXT: # %bb.1: # %entry + ; CHECK-NEXT: li a2, 128 + ; CHECK-NEXT: bltu a0, a2, .LBB0_4 + ; CHECK-NEXT: .LBB0_2: # %entry + ; CHECK-NEXT: vse64.v v9, (a1) + ; CHECK-NEXT: ret + ; CHECK-NEXT: .LBB0_3: + ; CHECK-NEXT: vmv.v.i v9, 0 + ; CHECK-NEXT: li a2, 128 + ; CHECK-NEXT: bgeu a0, a2, .LBB0_2 + ; CHECK-NEXT: .LBB0_4: # %entry + ; CHECK-NEXT: vmsne.vi v0, v8, 0 + ; CHECK-NEXT: vsll.vi v8, v8, 5 + ; CHECK-NEXT: vmerge.vim v9, v8, -1, v0 + ; CHECK-NEXT: vse64.v v9, (a1) + ; CHECK-NEXT: ret + entry: + ret void + } +... +--- +name: foo +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%1' } + - { reg: '$x11', virtual-reg: '%2' } + - { reg: '$v8', virtual-reg: '%2' } +body: | + bb.0.entry: + successors: %bb.1, %bb.2 + liveins: $x10, $x11, $x12, $v8 + + %2:gpr = COPY $x11 + %1:gpr = COPY $x10 + %3:vr = COPY $v8 + %17:vrnov0 = PseudoVSLL_VI_M1 undef $noreg, %3, 5, 1, 6 /* e64 */, 0 + %22:vr = PseudoVMSNE_VI_M1 %3, 0, 1, 6 /* e64 */ + %23:vmv0 = COPY %22 + %25:vrnov0 = PseudoVMERGE_VIM_M1 undef $noreg, %17, -1, %23, 1, 6 /* e64 */ + %29:vr = PseudoSF_VC_V_X_SE_M1 3, 31, %2, 1, 6 /* e64 */, implicit-def dead $sf_vcix_state, implicit $sf_vcix_state + %30:vr = PseudoVMV_V_I_M1 undef $noreg, 0, 1, 6 /* e64 */, 0 + BGEU %1, $x0, %bb.2 + + bb.1.entry: + + bb.2.entry: + successors: %bb.3, %bb.4 + + %31:vr = PHI %30, %bb.0, %29, %bb.1 + %32:gpr = ADDI $x0, 128 + BGEU %1, %32, %bb.4 + + bb.3.entry: + + bb.4.entry: + %33:vr = PHI %31, %bb.2, %25, %bb.3 + PseudoVSE64_V_M1 killed %33, %2, 1, 6 /* e64 */ + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir new file mode 100644 index 0000000..1e8aea9 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir @@ -0,0 +1,139 @@ +# RUN: llc -mtriple=riscv64 -mattr=+v -o %t0 -filetype=obj \ +# RUN: -start-before=prologepilog %s +# RUN: llc -mtriple=riscv64 -mattr=+v -o %t1 -filetype=obj \ +# RUN: -frame-pointer=all -start-before=prologepilog %s +# RUN: llvm-dwarfdump --name="value0" %t0 | FileCheck %s --check-prefix=CHECK0-PLUS +# RUN: llvm-dwarfdump --name="value1" %t0 | FileCheck %s --check-prefix=CHECK1-PLUS +# RUN: llvm-dwarfdump --name="value2" %t0 | FileCheck %s --check-prefix=CHECK2-PLUS +# RUN: llvm-dwarfdump --name="value3" %t0 | FileCheck %s --check-prefix=CHECK3-PLUS +# RUN: llvm-dwarfdump --name="value4" %t0 | FileCheck %s --check-prefix=CHECK4-PLUS +# RUN: llvm-dwarfdump --name="value5" %t0 | FileCheck %s --check-prefix=CHECK5-PLUS +# RUN: llvm-dwarfdump --name="value0" %t1 | FileCheck %s --check-prefix=CHECK0-MINUS +# RUN: llvm-dwarfdump --name="value1" %t1 | FileCheck %s --check-prefix=CHECK1-MINUS +# RUN: llvm-dwarfdump --name="value2" %t1 | FileCheck %s --check-prefix=CHECK2-MINUS +# RUN: llvm-dwarfdump --name="value3" %t1 | FileCheck %s --check-prefix=CHECK3-MINUS +# RUN: llvm-dwarfdump --name="value4" %t1 | FileCheck %s --check-prefix=CHECK4-MINUS +# RUN: llvm-dwarfdump --name="value5" %t1 | FileCheck %s --check-prefix=CHECK5-MINUS + +# CHECK0-PLUS: : DW_OP_breg2 X2+24) +# CHECK0-PLUS: DW_AT_type {{.*}}int32_t +# +# CHECK1-PLUS: : DW_OP_breg2 X2+16) +# CHECK1-PLUS: DW_AT_type {{.*}}int32_t +# +# CHECK2-PLUS: : DW_OP_breg2 X2+32, DW_OP_lit3, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_plus) +# CHECK2-PLUS: DW_AT_type {{.*}}vint32m1_t +# +# CHECK3-PLUS: : DW_OP_breg2 X2+32, DW_OP_lit2, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_plus) +# CHECK3-PLUS: DW_AT_type {{.*}}vint32m1_t +# +# CHECK4-PLUS: : DW_OP_breg2 X2+32, DW_OP_lit1, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_plus) +# CHECK4-PLUS: DW_AT_type {{.*}}vbool1_t +# +# CHECK5-PLUS: : DW_OP_breg2 X2+32) +# CHECK5-PLUS: DW_AT_type {{.*}}vbool1_t + +# CHECK0-MINUS: : DW_OP_breg8 X8-40) +# CHECK0-MINUS: DW_AT_type {{.*}}int32_t +# +# CHECK1-MINUS: : DW_OP_breg8 X8-48) +# CHECK1-MINUS: DW_AT_type {{.*}}int32_t +# +# CHECK2-MINUS: : DW_OP_breg8 X8-48, DW_OP_lit1, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_minus) +# CHECK2-MINUS: DW_AT_type {{.*}}vint32m1_t +# +# CHECK3-MINUS: : DW_OP_breg8 X8-48, DW_OP_lit2, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_minus) +# CHECK3-MINUS: DW_AT_type {{.*}}vint32m1_t +# +# CHECK4-MINUS: : DW_OP_breg8 X8-48, DW_OP_lit3, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_minus) +# CHECK4-MINUS: DW_AT_type {{.*}}vbool1_t +# +# CHECK5-MINUS: : DW_OP_breg8 X8-48, DW_OP_lit4, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_minus) +# CHECK5-MINUS: DW_AT_type {{.*}}vbool1_t + +--- | + define void @foo() !dbg !5 { + entry: + unreachable, !dbg !8 + } + + !llvm.dbg.cu = !{!0} + !llvm.debugify = !{!3, !3} + !llvm.module.flags = !{!4} + + !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) + !1 = !DIFile(filename: "debug-info-rvv-dbg-value.mir", directory: "/") + !2 = !{} + !3 = !{i32 1} + !4 = !{i32 2, !"Debug Info Version", i32 3} + !5 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !9) + !6 = !DISubroutineType(types: !2) + !7 = !DIBasicType(name: "int32_t", size: 32, encoding: DW_ATE_signed) + !8 = !DILocation(line: 1, column: 1, scope: !5) + !9 = !{!10, !11, !12, !13, !14, !15} + !10 = !DILocalVariable(name: "value0", scope: !5, file: !1, line: 1, type: !7) + !11 = !DILocalVariable(name: "value1", scope: !5, file: !1, line: 1, type: !7) + !12 = !DILocalVariable(name: "value2", scope: !5, file: !1, line: 1, type: !16) + !13 = !DILocalVariable(name: "value3", scope: !5, file: !1, line: 1, type: !16) + !14 = !DILocalVariable(name: "value4", scope: !5, file: !1, line: 1, type: !21) + !15 = !DILocalVariable(name: "value5", scope: !5, file: !1, line: 1, type: !21) + !16 = !DIDerivedType(tag: DW_TAG_typedef, name: "vint32m1_t", file: !1, line: 1, baseType: !17) + !17 = !DIDerivedType(tag: DW_TAG_typedef, name: "__rvv_int32m1_t", file: !1, baseType: !18) + !18 = !DICompositeType(tag: DW_TAG_array_type, baseType: !7, flags: DIFlagVector, elements: !19) + !19 = !{!20} + !20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_constu, 4, DW_OP_div, DW_OP_constu, 1, DW_OP_mul)) + !21 = !DIDerivedType(tag: DW_TAG_typedef, name: "vbool1_t", file: !1, line: 90, baseType: !22) + !22 = !DIDerivedType(tag: DW_TAG_typedef, name: "__rvv_bool1_t", file: !1, baseType: !23) + !23 = !DICompositeType(tag: DW_TAG_array_type, baseType: !24, flags: DIFlagVector, elements: !25) + !24 = !DIBasicType(name: "_Bool", size: 8, encoding: DW_ATE_boolean) + !25 = !{!26} + !26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_constu, 1, DW_OP_div, DW_OP_constu, 1, DW_OP_mul)) + +... +--- +name: foo +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x12' } + - { reg: '$x13' } + - { reg: '$v8' } + - { reg: '$v9' } + - { reg: '$v0' } + - { reg: '$v1' } +frameInfo: + maxAlignment: 16 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 0 + localFrameSize: 4 +stack: + - { id: 0, size: 8, alignment: 8 } + - { id: 1, size: 8, alignment: 8 } + - { id: 2, size: 8, alignment: 4, stack-id: scalable-vector } + - { id: 3, size: 8, alignment: 4, stack-id: scalable-vector } + - { id: 4, size: 8, alignment: 1, stack-id: scalable-vector } + - { id: 5, size: 8, alignment: 1, stack-id: scalable-vector } +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x12, $x13, $v8, $v9, $v0, $v1 + + SD killed renamable $x12, %stack.0, 0, debug-location !8 + DBG_VALUE %stack.0, $noreg, !10, !DIExpression(DW_OP_deref), debug-location !8 + SD killed renamable $x13, %stack.1, 0, debug-location !8 + DBG_VALUE %stack.1, $noreg, !11, !DIExpression(DW_OP_deref), debug-location !8 + + PseudoVSE32_V_M1 killed renamable $v8, %stack.2, 8, 5, debug-location !DILocation(line: 5, column: 1, scope: !5) + DBG_VALUE %stack.2, $noreg, !12, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 5, column: 1, scope: !5) + PseudoVSE32_V_M1 killed renamable $v9, %stack.3, 8, 5, debug-location !DILocation(line: 6, column: 1, scope: !5) + DBG_VALUE %stack.3, $noreg, !13, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 6, column: 1, scope: !5) + + PseudoVSM_V_B64 killed renamable $v0, %stack.4, 8, 0, debug-location !DILocation(line: 2, column: 1, scope: !5) + DBG_VALUE %stack.4, $noreg, !14, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 2, column: 1, scope: !5) + PseudoVSM_V_B64 killed renamable $v1, %stack.5, 8, 0, debug-location !DILocation(line: 3, column: 1, scope: !5) + DBG_VALUE %stack.5, $noreg, !15, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 3, column: 1, scope: !5) + + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir new file mode 100644 index 0000000..d8cc861 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir @@ -0,0 +1,233 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple riscv64 -mattr=+m,+v -run-pass=prologepilog -o - \ +# RUN: -verify-machineinstrs %s | FileCheck %s +--- | + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" + target triple = "riscv64" + + define void @spillslot() { + ret void + } + +... +--- +name: spillslot +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x12', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 128 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: [] + restorePoint: [] +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 2048, alignment: 128, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8, + stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: spill-slot, offset: 0, size: 400, alignment: 8, + stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + ; CHECK-LABEL: name: spillslot + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x12, $x1, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -2032 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-NEXT: frame-setup SD killed $x1, $x2, 2024 :: (store (s64) into %stack.3) + ; CHECK-NEXT: frame-setup SD killed $x8, $x2, 2016 :: (store (s64) into %stack.4) + ; CHECK-NEXT: frame-setup SD killed $x18, $x2, 2008 :: (store (s64) into %stack.5) + ; CHECK-NEXT: frame-setup SD killed $x19, $x2, 2000 :: (store (s64) into %stack.6) + ; CHECK-NEXT: frame-setup SD killed $x20, $x2, 1992 :: (store (s64) into %stack.7) + ; CHECK-NEXT: frame-setup SD killed $x21, $x2, 1984 :: (store (s64) into %stack.8) + ; CHECK-NEXT: frame-setup SD killed $x22, $x2, 1976 :: (store (s64) into %stack.9) + ; CHECK-NEXT: frame-setup SD killed $x23, $x2, 1968 :: (store (s64) into %stack.10) + ; CHECK-NEXT: frame-setup SD killed $x24, $x2, 1960 :: (store (s64) into %stack.11) + ; CHECK-NEXT: frame-setup SD killed $x25, $x2, 1952 :: (store (s64) into %stack.12) + ; CHECK-NEXT: frame-setup SD killed $x26, $x2, 1944 :: (store (s64) into %stack.13) + ; CHECK-NEXT: frame-setup SD killed $x27, $x2, 1936 :: (store (s64) into %stack.14) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -40 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -48 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -56 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -64 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -72 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -80 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -88 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -96 + ; CHECK-NEXT: $x8 = frame-setup ADDI $x2, 2032 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0 + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -272 + ; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB + ; CHECK-NEXT: $x11 = frame-setup ADDI $x0, 51 + ; CHECK-NEXT: $x10 = frame-setup MUL killed $x10, killed $x11 + ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10 + ; CHECK-NEXT: $x2 = frame-setup ANDI $x2, -128 + ; CHECK-NEXT: dead renamable $x15 = PseudoVSETIVLI 1, 72 /* e16, m1, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v25 = PseudoVMV_V_X_M1 undef $v25, killed renamable $x12, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $x10 = PseudoReadVLENB + ; CHECK-NEXT: $x11 = ADDI $x0, 50 + ; CHECK-NEXT: $x10 = MUL killed $x10, killed $x11 + ; CHECK-NEXT: $x10 = ADD $x2, killed $x10 + ; CHECK-NEXT: $x10 = ADDI killed $x10, 2047 + ; CHECK-NEXT: $x10 = ADDI killed $x10, 161 + ; CHECK-NEXT: VS1R_V killed renamable $v25, killed $x10 :: (store unknown-size into %stack.1, align 8) + ; CHECK-NEXT: renamable $x1 = ADDI $x0, 255 + ; CHECK-NEXT: renamable $x5 = nuw ADDI $x2, 384 + ; CHECK-NEXT: renamable $x6 = ADDI $x2, 512 + ; CHECK-NEXT: renamable $x7 = nuw ADDI $x2, 640 + ; CHECK-NEXT: renamable $x10 = ADDI $x0, 128 + ; CHECK-NEXT: renamable $x12 = nuw ADDI $x2, 256 + ; CHECK-NEXT: renamable $x14 = COPY $x0 + ; CHECK-NEXT: renamable $x17 = nuw ADDI $x2, 256 + ; CHECK-NEXT: renamable $x18 = ADDI $x2, 1280 + ; CHECK-NEXT: renamable $x19 = ADDI $x2, 1408 + ; CHECK-NEXT: renamable $x20 = ADDI $x2, 1536 + ; CHECK-NEXT: renamable $x21 = ADDI $x2, 1664 + ; CHECK-NEXT: renamable $x22 = ADDI $x2, 1792 + ; CHECK-NEXT: renamable $x23 = ADDI $x2, 1920 + ; CHECK-NEXT: $x24 = ADDI $x2, 2047 + ; CHECK-NEXT: $x24 = ADDI killed $x24, 1 + ; CHECK-NEXT: renamable $x25 = ADDI $x2, 128 + ; CHECK-NEXT: renamable $x26 = ADDI $x2, 128 + ; CHECK-NEXT: renamable $x27 = ADDI $x0, 2 + ; CHECK-NEXT: renamable $x28 = ADDI $x2, 768 + ; CHECK-NEXT: renamable $x29 = ADDI $x2, 896 + ; CHECK-NEXT: renamable $x30 = ADDI $x2, 1024 + ; CHECK-NEXT: renamable $x31 = nuw ADDI $x2, 1152 + ; CHECK-NEXT: renamable $x15 = ADDIW renamable $x14, 0 + ; CHECK-NEXT: renamable $x11 = ANDI renamable $x15, 255 + ; CHECK-NEXT: renamable $x13 = SLLI renamable $x11, 3 + ; CHECK-NEXT: renamable $x13 = ADD renamable $x26, killed renamable $x13 + ; CHECK-NEXT: renamable $x13 = LD killed renamable $x13, 0 :: (load (s64)) + ; CHECK-NEXT: renamable $x16 = SUB killed renamable $x13, renamable $x13 + ; CHECK-NEXT: dead renamable $x13 = PseudoVSETIVLI 1, 64 /* e8, m1, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $x13 = nsw ADDI renamable $x16, -2 + ; CHECK-NEXT: SD killed $x10, $x2, 8 :: (store (s64) into %stack.15) + ; CHECK-NEXT: $x10 = PseudoReadVLENB + ; CHECK-NEXT: SD killed $x12, $x2, 0 :: (store (s64) into %stack.16) + ; CHECK-NEXT: $x12 = ADDI $x0, 50 + ; CHECK-NEXT: $x10 = MUL killed $x10, killed $x12 + ; CHECK-NEXT: $x12 = LD $x2, 0 :: (load (s64) from %stack.16) + ; CHECK-NEXT: $x10 = ADD $x2, killed $x10 + ; CHECK-NEXT: $x10 = ADDI killed $x10, 2047 + ; CHECK-NEXT: $x10 = ADDI killed $x10, 161 + ; CHECK-NEXT: renamable $v0 = VL1RE8_V killed $x10 :: (load unknown-size from %stack.1, align 8) + ; CHECK-NEXT: $x10 = LD $x2, 8 :: (load (s64) from %stack.15) + ; CHECK-NEXT: renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg /* vl */, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $x13 = PseudoVMV_X_S killed renamable $v0, 3 /* e8 */, implicit $vtype + ; CHECK-NEXT: BLT killed renamable $x16, renamable $x27, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $x1, $x5, $x6, $x7, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x10 = COPY killed renamable $x13 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2032 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 2032 + ; CHECK-NEXT: $x1 = frame-destroy LD $x2, 2024 :: (load (s64) from %stack.3) + ; CHECK-NEXT: $x8 = frame-destroy LD $x2, 2016 :: (load (s64) from %stack.4) + ; CHECK-NEXT: $x18 = frame-destroy LD $x2, 2008 :: (load (s64) from %stack.5) + ; CHECK-NEXT: $x19 = frame-destroy LD $x2, 2000 :: (load (s64) from %stack.6) + ; CHECK-NEXT: $x20 = frame-destroy LD $x2, 1992 :: (load (s64) from %stack.7) + ; CHECK-NEXT: $x21 = frame-destroy LD $x2, 1984 :: (load (s64) from %stack.8) + ; CHECK-NEXT: $x22 = frame-destroy LD $x2, 1976 :: (load (s64) from %stack.9) + ; CHECK-NEXT: $x23 = frame-destroy LD $x2, 1968 :: (load (s64) from %stack.10) + ; CHECK-NEXT: $x24 = frame-destroy LD $x2, 1960 :: (load (s64) from %stack.11) + ; CHECK-NEXT: $x25 = frame-destroy LD $x2, 1952 :: (load (s64) from %stack.12) + ; CHECK-NEXT: $x26 = frame-destroy LD $x2, 1944 :: (load (s64) from %stack.13) + ; CHECK-NEXT: $x27 = frame-destroy LD $x2, 1936 :: (load (s64) from %stack.14) + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x18 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x19 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x20 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x21 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x22 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x23 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x24 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x25 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x26 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x27 + ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.1, %bb.2 + liveins: $x12 + + dead renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype + renamable $v25 = PseudoVMV_V_X_M1 undef $v25, killed renamable $x12, $noreg, 4, 0, implicit $vl, implicit $vtype + VS1R_V killed renamable $v25, %stack.1 :: (store unknown-size into %stack.1, align 8) + renamable $x1 = ADDI $x0, 255 + renamable $x5 = nuw ADDI %stack.0, 256 + renamable $x6 = ADDI %stack.0, 384 + renamable $x7 = nuw ADDI %stack.0, 512 + renamable $x10 = ADDI $x0, 128 + renamable $x12 = nuw ADDI %stack.0, 128 + renamable $x14 = COPY $x0 + renamable $x17 = nuw ADDI %stack.0, 128 + renamable $x18 = ADDI %stack.0, 1152 + renamable $x19 = ADDI %stack.0, 1280 + renamable $x20 = ADDI %stack.0, 1408 + renamable $x21 = ADDI %stack.0, 1536 + renamable $x22 = ADDI %stack.0, 1664 + renamable $x23 = ADDI %stack.0, 1792 + renamable $x24 = ADDI %stack.0, 1920 + renamable $x25 = ADDI %stack.0, 0 + renamable $x26 = ADDI %stack.0, 0 + renamable $x27 = ADDI $x0, 2 + renamable $x28 = ADDI %stack.0, 640 + renamable $x29 = ADDI %stack.0, 768 + renamable $x30 = ADDI %stack.0, 896 + renamable $x31 = nuw ADDI %stack.0, 1024 + renamable $x15 = ADDIW renamable $x14, 0 + renamable $x11 = ANDI renamable $x15, 255 + renamable $x13 = SLLI renamable $x11, 3 + renamable $x13 = ADD renamable $x26, killed renamable $x13 + renamable $x13 = LD killed renamable $x13, 0 :: (load (s64)) + renamable $x16 = SUB killed renamable $x13, renamable $x13 + dead renamable $x13 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype + renamable $x13 = nsw ADDI renamable $x16, -2 + renamable $v0 = VL1RE8_V %stack.1 :: (load unknown-size from %stack.1, align 8) + renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 3, 1, implicit $vl, implicit $vtype + renamable $x13 = PseudoVMV_X_S killed renamable $v0, 3, implicit $vtype + BLT killed renamable $x16, renamable $x27, %bb.2 + + bb.1: + successors: %bb.2 + liveins: $x1, $x5, $x6, $x7, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31 + + renamable $x10 = COPY killed renamable $x13 + PseudoBR %bb.2 + + bb.2: + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir new file mode 100644 index 0000000..071e3a8 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir @@ -0,0 +1,59 @@ +# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +# RUN: llc -mtriple riscv64 -mattr=+v -target-abi=lp64 -start-before=prologepilog -o - \ +# RUN: -verify-machineinstrs %s | FileCheck %s +--- | + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" + target triple = "riscv64" + + define weak_odr dso_local void @fixedlen_vector_spillslot(ptr %ay) nounwind { + ; CHECK-LABEL: fixedlen_vector_spillslot: + ; CHECK: # %bb.0: # %entry + ; CHECK-NEXT: addi sp, sp, -48 + ; CHECK-NEXT: sd ra, 40(sp) # 8-byte Folded Spill + ; CHECK-NEXT: sd a0, 32(sp) + ; CHECK-NEXT: sd a0, 16(sp) + ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu + ; CHECK-NEXT: sd a1, 0(sp) # 8-byte Folded Spill + ; CHECK-NEXT: addi a1, sp, 24 + ; CHECK-NEXT: vs1r.v v25, (a1) # vscale x 8-byte Folded Spill + ; CHECK-NEXT: ld a1, 0(sp) # 8-byte Folded Reload + ; CHECK-NEXT: call fixedlen_vector_spillslot + ; CHECK-NEXT: ld ra, 40(sp) # 8-byte Folded Reload + ; CHECK-NEXT: addi sp, sp, 48 + ; CHECK-NEXT: ret + entry: + ret void + } + +... +--- +name: fixedlen_vector_spillslot +alignment: 2 +tracksRegLiveness: false +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: spill-slot, offset: 0, size: 2, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.0.entry: + liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x31, $v25 + + SD $x10, %stack.0, 0 + SD $x10, %stack.2, 0 + dead $x0 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype + VS1R_V killed renamable $v25, %stack.1 :: (store () into %stack.1, align 8) + ; This is here just to make all the eligible registers live at this point. + ; This way when we replace the frame index %stack.1 with its actual address + ; we have to allocate a virtual register to compute it. + ; A later run of the the register scavenger won't find an available register + ; either so it will have to spill one to the emergency spill slot. + PseudoCALL target-flags(riscv-call) @fixedlen_vector_spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir new file mode 100644 index 0000000..1d9b8b2 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir @@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v -o - %s \ +# RUN: -stop-after=prologepilog | FileCheck %s + +--- | + define void @foo() !dbg !0 { + entry: + %va = alloca , align 4, !dbg !1 + br label %end + end: + ret void, !dbg !2 + } + + !0 = distinct !DISubprogram(name: "foo", line: 3, scopeLine: 3, type: !4) + !1 = !DILocation(line: 4, column: 14, scope: !0) + !2 = !DILocation(line: 5, column: 3, scope: !0) + !3 = !{null} + !4 = !DISubroutineType(types: !3) + +... +--- +name: foo +tracksRegLiveness: true +stack: + - { id: 0, stack-id: scalable-vector, offset: 0, size: 8, alignment: 8 } +body: | + ; CHECK-LABEL: name: foo + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB + ; CHECK-NEXT: $x10 = frame-setup SLLI killed $x10, 1 + ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0a, 0x72, 0x00, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB + ; CHECK-NEXT: $x10 = frame-destroy SLLI killed $x10, 1 + ; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 0 + ; CHECK-NEXT: PseudoRET + bb.0: + bb.1: + PseudoRET diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir new file mode 100644 index 0000000..cb39f24 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir @@ -0,0 +1,23 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -run-pass=init-undef -o - %s | FileCheck %s --check-prefix=MIR + +# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -passes=init-undef -o - %s | FileCheck %s --check-prefix=MIR +... +--- +name: vrgather_all_undef +tracksRegLiveness: true +body: | + bb.0.entry: + ; MIR-LABEL: name: vrgather_all_undef + ; MIR: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; MIR-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF + ; MIR-NEXT: [[INIT_UNDEF:%[0-9]+]]:vr = INIT_UNDEF + ; MIR-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 [[DEF1]], killed [[INIT_UNDEF]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; MIR-NEXT: $v8 = COPY %1 + ; MIR-NEXT: PseudoRET implicit $v8 + %2:vr = IMPLICIT_DEF + early-clobber %1:vr = PseudoVRGATHER_VI_M1 $noreg, killed undef %2, 0, 0, 5 /* e32 */, 0 /* tu, mu */ + $v8 = COPY %1 + PseudoRET implicit $v8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir new file mode 100644 index 0000000..9d02dc7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir @@ -0,0 +1,94 @@ +# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +# RUN: llc -mtriple riscv64 -mattr=+m,+v -target-abi=lp64 -start-before=prologepilog -o - \ +# RUN: -verify-machineinstrs %s | FileCheck %s +--- | + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" + target triple = "riscv64" + + define void @spillslot() { + ; CHECK-LABEL: spillslot: + ; CHECK: # %bb.0: + ; CHECK-NEXT: addi sp, sp, -2032 + ; CHECK-NEXT: .cfi_def_cfa_offset 2032 + ; CHECK-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill + ; CHECK-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill + ; CHECK-NEXT: .cfi_offset ra, -8 + ; CHECK-NEXT: .cfi_offset s0, -16 + ; CHECK-NEXT: addi s0, sp, 2032 + ; CHECK-NEXT: .cfi_def_cfa s0, 0 + ; CHECK-NEXT: addi sp, sp, -272 + ; CHECK-NEXT: sd a0, 8(sp) # 8-byte Folded Spill + ; CHECK-NEXT: csrr a0, vlenb + ; CHECK-NEXT: sd a1, 0(sp) # 8-byte Folded Spill + ; CHECK-NEXT: li a1, 3 + ; CHECK-NEXT: slli a1, a1, 10 + ; CHECK-NEXT: mul a0, a0, a1 + ; CHECK-NEXT: ld a1, 0(sp) # 8-byte Folded Reload + ; CHECK-NEXT: sub sp, sp, a0 + ; CHECK-NEXT: ld a0, 8(sp) # 8-byte Folded Reload + ; CHECK-NEXT: andi sp, sp, -128 + ; CHECK-NEXT: sd a0, 8(sp) # 8-byte Folded Spill + ; CHECK-NEXT: addi a0, sp, 2047 + ; CHECK-NEXT: addi a0, a0, 241 + ; CHECK-NEXT: vs1r.v v25, (a0) # vscale x 8-byte Folded Spill + ; CHECK-NEXT: ld a0, 8(sp) # 8-byte Folded Reload + ; CHECK-NEXT: call spillslot + ; CHECK-NEXT: addi sp, s0, -2032 + ; CHECK-NEXT: .cfi_def_cfa sp, 2032 + ; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload + ; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload + ; CHECK-NEXT: .cfi_restore ra + ; CHECK-NEXT: .cfi_restore s0 + ; CHECK-NEXT: addi sp, sp, 2032 + ; CHECK-NEXT: .cfi_def_cfa_offset 0 + ; CHECK-NEXT: ret + ret void + } + +... +--- +name: spillslot +alignment: 4 +tracksRegLiveness: false +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 128 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: [] + restorePoint: [] +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 2048, alignment: 128, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: spill-slot, offset: 0, size: 24576, alignment: 8, + stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.0: + liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x31, $v25 + + VS1R_V killed renamable $v25, %stack.1 :: (store () into %stack.1, align 8) + ; This is here just to make all the eligible registers live at this point. + ; This way when we replace the frame index %stack.1 with its actual address + ; we have to allocate two virtual registers to compute it. + ; A later run of the the register scavenger won't find available registers + ; either so it will have to spill two to the emergency spill slots + ; required for this RVV computation. + PseudoCALL target-flags(riscv-call) @spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/machine-combiner-subreg-verifier-error.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/machine-combiner-subreg-verifier-error.mir new file mode 100644 index 0000000..507d0e3 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/machine-combiner-subreg-verifier-error.mir @@ -0,0 +1,39 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -run-pass=machine-combiner -o - %s | FileCheck %s + +# Make sure the verifier doesn't fail due to dropping subregister +# uses. + +--- +name: machine_combiner_subreg_verifier_error +tracksRegLiveness: true +isSSA: true +body: | + bb.0: + liveins: $v8m4, $v12m4 + + ; CHECK-LABEL: name: machine_combiner_subreg_verifier_error + ; CHECK: liveins: $v8m4, $v12m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:gprnox0 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVSLIDEDOWN_VI_M8_:%[0-9]+]]:vrm8 = PseudoVSLIDEDOWN_VI_M8 $noreg, [[DEF2]], 26, 2 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 $noreg, [[DEF2]].sub_vrm1_0, killed [[DEF3]], 2 /* vl */, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVADD_VV_MF2_1:%[0-9]+]]:vr = PseudoVADD_VV_MF2 $noreg, [[PseudoVSLIDEDOWN_VI_M8_]].sub_vrm1_0, killed [[PseudoVADD_VV_MF2_]], 2 /* vl */, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:vrm4 = IMPLICIT_DEF + %1:gprnox0 = IMPLICIT_DEF + %2:vrm8 = IMPLICIT_DEF + %3:vr = IMPLICIT_DEF + %4:vrm2 = IMPLICIT_DEF + %5:vr = IMPLICIT_DEF + %6:vrm8 = PseudoVSLIDEDOWN_VI_M8 $noreg, %2, 26, 2, 5 /* e32 */, 3 /* ta, ma */ + %7:vr = PseudoVADD_VV_MF2 $noreg, %6.sub_vrm1_0, %2.sub_vrm1_0, 2, 5 /* e32 */, 1 /* ta, mu */ + %8:vr = PseudoVADD_VV_MF2 $noreg, killed %7, killed %3, 2, 5 /* e32 */, 1 /* ta, mu */ + PseudoRET implicit $v8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir new file mode 100644 index 0000000..6d59554 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir @@ -0,0 +1,36 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \ +# RUN: -start-after finalize-isel -stop-after prologepilog -o - %s | FileCheck %s + +--- | + define void @mask_reg_alloc() { + ret void + } +... +--- +name: mask_reg_alloc +tracksRegLiveness: true +body: | + bb.0 (%ir-block.0): + liveins: $v0, $v1, $v2, $v3 + ; CHECK-LABEL: name: mask_reg_alloc + ; CHECK: liveins: $v0, $v1, $v2, $v3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v8 = PseudoVMERGE_VIM_M1 undef renamable $v8, killed renamable $v2, 1, $v0, 1 /* vl */, 3 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v0 = COPY $v1, implicit $vtype + ; CHECK-NEXT: renamable $v9 = PseudoVMERGE_VIM_M1 undef renamable $v9, killed renamable $v3, 1, $v0, 1 /* vl */, 3 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v0 = PseudoVADD_VV_M1 undef renamable $v0, killed renamable $v8, killed renamable $v9, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:vr = COPY $v0 + %1:vr = COPY $v1 + %2:vrnov0 = COPY $v2 + %3:vrnov0 = COPY $v3 + %4:vmv0 = COPY %0 + %5:vrnov0 = PseudoVMERGE_VIM_M1 undef $noreg, killed %2, 1, %4, 1, 3 + %6:vmv0 = COPY %1 + %7:vrnov0 = PseudoVMERGE_VIM_M1 undef $noreg, killed %3, 1, %6, 1, 3 + %8:vr = PseudoVADD_VV_M1 undef $noreg, killed %5, killed %7, 1, 3, 0 + $v0 = COPY %8 + PseudoRET implicit $v0 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir new file mode 100644 index 0000000..f100897 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc %s -mtriple=riscv64 -mattr=+v -run-pass=register-coalescer -o - | FileCheck %s +--- +# Make sure that SrcReg & DstReg of PseudoVRGATHER are not coalesced +name: test_earlyclobber +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: test_earlyclobber + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[PseudoVLE32_V_M2_:%[0-9]+]].sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 %pt, $x10, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %pt2:vrm2 = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]].sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 %pt2, $x10, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %pt3:vrm2 = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M2_1:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt3, $x10, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: undef early-clobber %5.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 undef %5.sub_vrm2_0, [[PseudoVLE32_V_M2_]].sub_vrm2_0, 0, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]].sub_vrm2_1:vrn2m2 = COPY [[PseudoVLE32_V_M2_]].sub_vrm2_1 + ; CHECK-NEXT: PseudoVSUXSEG2EI32_V_M2_M2 [[COPY]], $x10, [[PseudoVLE32_V_M2_1]], 1 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + %pt:vrm2 = IMPLICIT_DEF + undef %0.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 %pt, $x10, 1, 5, 0 + %pt2:vrm2 = IMPLICIT_DEF + %0.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 %pt2, $x10, 1, 5, 0 + %pt3:vrm2 = IMPLICIT_DEF + %1:vrm2 = PseudoVLE32_V_M2 %pt3, $x10, 1, 5, 0 + undef early-clobber %2.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 undef %2.sub_vrm2_0, %0.sub_vrm2_0:vrn2m2, 0, 1, 5, 0, implicit $vl, implicit $vtype + %2.sub_vrm2_1:vrn2m2 = COPY %0.sub_vrm2_1:vrn2m2 + PseudoVSUXSEG2EI32_V_M2_M2 %2:vrn2m2, $x10, %1:vrm2, 1, 5, implicit $vl, implicit $vtype +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.mir new file mode 100644 index 0000000..3be74a7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.mir @@ -0,0 +1,57 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=register-coalescer -o - %s | FileCheck %s + +--- +name: pr71023 +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: pr71023 + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $v8, $v10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF + ; CHECK-NEXT: undef [[PseudoVMV_V_I_M1_:%[0-9]+]].sub_vrm1_2:vrn8m1 = PseudoVMV_V_I_M1 undef [[PseudoVMV_V_I_M1_]].sub_vrm1_2, 0, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]].sub_vrm1_6:vrn8m1 = COPY undef [[PseudoVMV_V_I_M1_]].sub_vrm1_2 + ; CHECK-NEXT: BNE undef [[DEF]], $x0, %bb.3 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BNE undef [[DEF]], $x0, %bb.3 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: dead [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF + ; CHECK-NEXT: early-clobber [[PseudoVMV_V_I_M1_]].sub_vrm1_0:vrn8m1 = PseudoVRGATHER_VI_M1 undef [[PseudoVMV_V_I_M1_]].sub_vrm1_0, [[PseudoVMV_V_I_M1_]].sub_vrm1_2, 0, 0 /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSSEG6E8_V_M1_MASK [[PseudoVMV_V_I_M1_]].sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, undef [[DEF]], killed undef $v0, 0 /* vl */, 3 /* e8 */, implicit $vl, implicit $vtype :: (store unknown-size, align 1) + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.3(0x40000000), %bb.1(0x40000000) + liveins: $x10, $v8, $v10 + %0:gpr = IMPLICIT_DEF + %1:vrnov0 = PseudoVMV_V_I_M1 undef %1, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + %2:vrnov0 = IMPLICIT_DEF + undef %3.sub_vrm1_0:vrn6m1nov0 = COPY undef %1 + %3.sub_vrm1_3:vrn6m1nov0 = COPY %2 + %3.sub_vrm1_4:vrn6m1nov0 = COPY undef %1 + BNE undef %0, $x0, %bb.3 + PseudoBR %bb.1 + bb.1: + successors: %bb.3(0x40000000), %bb.2(0x40000000) + BNE killed undef %0, $x0, %bb.3 + PseudoBR %bb.2 + bb.2: + successors: %bb.3(0x80000000) + bb.3: + %4:vr = IMPLICIT_DEF + early-clobber %4:vr = PseudoVRGATHER_VI_M1 undef %4, killed %1, 0, 0, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + undef %5.sub_vrm1_0:vrn6m1 = COPY killed %4 + %5.sub_vrm1_5:vrn6m1 = COPY killed %2 + PseudoVSSEG6E8_V_M1_MASK killed %5, undef %0, killed undef $v0, 0, 3 /* e8 */, implicit $vl, implicit $vtype :: (store unknown-size, align 1) + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir new file mode 100644 index 0000000..b74aad5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir @@ -0,0 +1,281 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \ +# RUN: -verify-machineinstrs | FileCheck %s + +--- +name: undef_passthru +body: | + bb.0: + liveins: $x1, $v8, $v9 + ; CHECK-LABEL: name: undef_passthru + ; CHECK: liveins: $x1, $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %false:vrnov0 = COPY $v8 + ; CHECK-NEXT: %true:vrnov0 = COPY $v9 + ; CHECK-NEXT: %avl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY %mask + %false:vrnov0 = COPY $v8 + %true:vrnov0 = COPY $v9 + %avl:gprnox0 = COPY $x1 + %mask:vmv0 = PseudoVMSET_M_B8 %avl, 0 + $v0 = COPY %mask + %x:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %false, %true, $v0, %avl, 5 +... +--- +name: undef_false +body: | + bb.0: + liveins: $x1, $v8, $v9 + ; CHECK-LABEL: name: undef_false + ; CHECK: liveins: $x1, $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %pt:vr = COPY $v8 + ; CHECK-NEXT: %false:vrnov0 = COPY $noreg + ; CHECK-NEXT: %true:vrnov0 = COPY $v9 + ; CHECK-NEXT: %avl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v0 = COPY %mask + ; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + %pt:vrnov0 = COPY $v8 + %false:vrnov0 = COPY $noreg + %true:vrnov0 = COPY $v9 + %avl:gprnox0 = COPY $x1 + %mask:vmv0 = PseudoVMSET_M_B8 %avl, 0 + $v0 = COPY %mask + %x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, $v0, %avl, 5 +... +--- +name: equal_passthru_false +body: | + bb.0: + liveins: $x1, $v8, $v9 + ; CHECK-LABEL: name: equal_passthru_false + ; CHECK: liveins: $x1, $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %false:vrnov0 = COPY $v8 + ; CHECK-NEXT: %pt:vr = COPY $v8 + ; CHECK-NEXT: %true:vrnov0 = COPY $v9 + ; CHECK-NEXT: %avl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + %false:vrnov0 = COPY $v8 + %pt:vrnov0 = COPY $v8 + %true:vrnov0 = COPY $v9 + %avl:gprnox0 = COPY $x1 + %mask:vmv0 = PseudoVMSET_M_B8 %avl, 0 + %x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, %avl, 5 +... +--- +name: same_mask +body: | + bb.0: + liveins: $v8, $v9, $v0 + ; CHECK-LABEL: name: same_mask + ; CHECK: liveins: $v8, $v9, $v0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %pt:vr = COPY $v8 + ; CHECK-NEXT: %false:vrnov0 = COPY $v9 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 8 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + %pt:vrnov0 = COPY $v8 + %false:vrnov0 = COPY $v9 + %mask:vmv0 = COPY $v0 + %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 8, 5 /* e32 */, 0 /* tu, mu */ + %x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, 4, 5 /* e32 */ +... +--- +# Shouldn't be converted because false operands are different +name: same_mask_different_false +body: | + bb.0: + liveins: $v8, $v9, $v0 + ; CHECK-LABEL: name: same_mask_different_false + ; CHECK: liveins: $v8, $v9, $v0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %pt:vrnov0 = COPY $v8 + ; CHECK-NEXT: %false:vrnov0 = COPY $v9 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %pt, $noreg, $noreg, %mask, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, 8 /* vl */, 5 /* e32 */ + %pt:vrnov0 = COPY $v8 + %false:vrnov0 = COPY $v9 + %mask:vmv0 = COPY $v0 + %true:vrnov0 = PseudoVADD_VV_M1_MASK %pt, $noreg, $noreg, %mask, 4, 5 /* e32 */, 0 /* tu, mu */ + %x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, 8, 5 /* e32 */ +... +--- +# Shouldn't be converted because EEWs are different +name: same_mask_different_eew +body: | + bb.0: + liveins: $v8, $v9, $v0 + ; CHECK-LABEL: name: same_mask_different_eew + ; CHECK: liveins: $v8, $v9, $v0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %pt:vrnov0 = COPY $v8 + ; CHECK-NEXT: %false:vrnov0 = COPY $v9 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 4 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, 8 /* vl */, 5 /* e32 */ + %pt:vrnov0 = COPY $v8 + %false:vrnov0 = COPY $v9 + %mask:vmv0 = COPY $v0 + %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 4, 4 /* e16 */, 0 /* tu, mu */ + %x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, 8, 5 /* e32 */ +... +--- +name: same_mask_undef_truepassthru +body: | + bb.0: + liveins: $v8, $v0 + ; CHECK-LABEL: name: same_mask_undef_truepassthru + ; CHECK: liveins: $v8, $v0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %false:vrnov0 = COPY $v8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 4 /* vl */, 5 /* e32 */, 1 /* ta, mu */ + %false:vrnov0 = COPY $v8 + %mask:vmv0 = COPY $v0 + %true:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %mask, 4, 5 /* e32 */, 0 /* tu, mu */ + %x:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %false, %true, %mask, 4, 5 /* e32 */ +... +--- +# Shouldn't be converted because true is in a different block +name: same_mask_diff_blocks +body: | + ; CHECK-LABEL: name: same_mask_diff_blocks + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $v8, $v0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %false:vrnov0 = COPY $v8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %mask, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %false, %true, %mask, 4 /* vl */, 5 /* e32 */ + bb.0: + liveins: $v8, $v0 + %false:vrnov0 = COPY $v8 + %mask:vmv0 = COPY $v0 + %true:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %mask, 4, 5 /* e32 */, 0 /* tu, mu */ + bb.1: + %5:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %false, %true, %mask, 4, 5 /* e32 */ +... +--- +# Shouldn't be converted because vmerge adds back in elements from false past avl that would be lost if we converted to vmv.v.v +name: preserve_false +body: | + bb.0: + liveins: $v8, $v9, $v0, $x8, $x9 + ; CHECK-LABEL: name: preserve_false + ; CHECK: liveins: $v8, $v9, $v0, $x8, $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %pt:vrnov0 = COPY $v8 + ; CHECK-NEXT: %false:vrnov0 = COPY $v9 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %avl1:gprnox0 = COPY $x8 + ; CHECK-NEXT: %avl2:gprnox0 = COPY $x9 + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %mask, %avl1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, %avl2 /* vl */, 5 /* e32 */ + %pt:vrnov0 = COPY $v8 + %false:vrnov0 = COPY $v9 + %mask:vmv0 = COPY $v0 + %avl1:gprnox0 = COPY $x8 + %avl2:gprnox0 = COPY $x9 + %true:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %mask, %avl1, 5 /* e32 */, 3 /* ta, ma */ + %5:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, %avl2, 5 /* e32 */ +... +--- +# But we can convert this one because vmerge's avl being <= true's means we don't lose any false elements past avl. +name: preserve_false_avl_known_le +body: | + bb.0: + liveins: $v8, $v9, $v0 + ; CHECK-LABEL: name: preserve_false_avl_known_le + ; CHECK: liveins: $v8, $v9, $v0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %pt:vr = COPY $v8 + ; CHECK-NEXT: %false:vrnov0 = COPY $v9 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 2 /* vl */, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVMV_V_V_M1_:%[0-9]+]]:vr = PseudoVMV_V_V_M1 %pt, %true, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + %pt:vrnov0 = COPY $v8 + %false:vrnov0 = COPY $v9 + %mask:vmv0 = COPY $v0 + %true:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %mask, 2, 5 /* e32 */, 3 /* ta, ma */ + %5:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, 1, 5 /* e32 */ +... +--- +# Can convert because False == Passthru and True's tail policy is TU, +# so True's tail lanes preserve passthru (= False = Passthru). +name: same_mask_false_eq_passthru_true_tu +body: | + bb.0: + liveins: $v8, $v0, $x8, $x9 + ; CHECK-LABEL: name: same_mask_false_eq_passthru_true_tu + ; CHECK: liveins: $v8, $v0, $x8, $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %false:vrnov0 = COPY $v8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %avl1:gprnox0 = COPY $x8 + ; CHECK-NEXT: %avl2:gprnox0 = COPY $x9 + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, %avl1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVMV_V_V_M1_:%[0-9]+]]:vr = PseudoVMV_V_V_M1 %false, %true, %avl2 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + %false:vrnov0 = COPY $v8 + %mask:vmv0 = COPY $v0 + %avl1:gprnox0 = COPY $x8 + %avl2:gprnox0 = COPY $x9 + %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, %avl1, 5 /* e32 */, 0 /* tu, mu */ + %5:vrnov0 = PseudoVMERGE_VVM_M1 %false, %false, %true, %mask, %avl2, 5 /* e32 */ +... +--- +# Shouldn't be converted because True's tail policy is TA, so tail lanes +# past TrueVL could be agnostic, even though False == Passthru. +name: same_mask_false_eq_passthru_true_ta +body: | + bb.0: + liveins: $v8, $v0, $x8, $x9 + ; CHECK-LABEL: name: same_mask_false_eq_passthru_true_ta + ; CHECK: liveins: $v8, $v0, $x8, $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %false:vrnov0 = COPY $v8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %avl1:gprnox0 = COPY $x8 + ; CHECK-NEXT: %avl2:gprnox0 = COPY $x9 + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, %avl1 /* vl */, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 %false, %false, %true, %mask, %avl2 /* vl */, 5 /* e32 */ + %false:vrnov0 = COPY $v8 + %mask:vmv0 = COPY $v0 + %avl1:gprnox0 = COPY $x8 + %avl2:gprnox0 = COPY $x9 + %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, %avl1, 5 /* e32 */, 1 /* ta, mu */ + %5:vrnov0 = PseudoVMERGE_VVM_M1 %false, %false, %true, %mask, %avl2, 5 /* e32 */ +... +--- +# Shouldn't be converted because False != Passthru, even though True's +# tail policy is TU and MIVL could be > TrueVL. +name: same_mask_false_ne_passthru_true_tu +body: | + bb.0: + liveins: $v8, $v9, $v0, $x8, $x9 + ; CHECK-LABEL: name: same_mask_false_ne_passthru_true_tu + ; CHECK: liveins: $v8, $v9, $v0, $x8, $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %pt:vrnov0 = COPY $v8 + ; CHECK-NEXT: %false:vrnov0 = COPY $v9 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %avl1:gprnox0 = COPY $x8 + ; CHECK-NEXT: %avl2:gprnox0 = COPY $x9 + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, %avl1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, %avl2 /* vl */, 5 /* e32 */ + %pt:vrnov0 = COPY $v8 + %false:vrnov0 = COPY $v9 + %mask:vmv0 = COPY $v0 + %avl1:gprnox0 = COPY $x8 + %avl2:gprnox0 = COPY $x9 + %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, %avl1, 5 /* e32 */, 0 /* tu, mu */ + %5:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, %avl2, 5 /* e32 */ +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir new file mode 100644 index 0000000..c0170e7 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir @@ -0,0 +1,285 @@ +# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +# RUN: llc -mtriple riscv32 -mattr=+zve64x -start-before=prologepilog -o - \ +# RUN: -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32 +# RUN: llc -mtriple riscv32 -mattr=+v -start-before=prologepilog -o - \ +# RUN: -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32 +# RUN: llc -mtriple riscv64 -mattr=+zve64x -start-before=prologepilog -o - \ +# RUN: -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64 +# RUN: llc -mtriple riscv64 -mattr=+v -start-before=prologepilog -o - \ +# RUN: -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64 +--- | + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" + target triple = "riscv64" + + declare void @extern(ptr) + + define void @rvv_stack_align8() #0 { + ; RV32-LABEL: rvv_stack_align8: + ; RV32: # %bb.0: + ; RV32-NEXT: addi sp, sp, -48 + ; RV32-NEXT: sw ra, 44(sp) # 4-byte Folded Spill + ; RV32-NEXT: csrr a0, vlenb + ; RV32-NEXT: slli a0, a0, 1 + ; RV32-NEXT: sub sp, sp, a0 + ; RV32-NEXT: addi a0, sp, 32 + ; RV32-NEXT: addi a1, sp, 16 + ; RV32-NEXT: addi a2, sp, 8 + ; RV32-NEXT: call extern + ; RV32-NEXT: csrr a0, vlenb + ; RV32-NEXT: slli a0, a0, 1 + ; RV32-NEXT: add sp, sp, a0 + ; RV32-NEXT: lw ra, 44(sp) # 4-byte Folded Reload + ; RV32-NEXT: addi sp, sp, 48 + ; RV32-NEXT: ret + ; + ; RV64-LABEL: rvv_stack_align8: + ; RV64: # %bb.0: + ; RV64-NEXT: addi sp, sp, -48 + ; RV64-NEXT: sd ra, 40(sp) # 8-byte Folded Spill + ; RV64-NEXT: csrr a0, vlenb + ; RV64-NEXT: slli a0, a0, 1 + ; RV64-NEXT: sub sp, sp, a0 + ; RV64-NEXT: addi a0, sp, 32 + ; RV64-NEXT: addi a1, sp, 16 + ; RV64-NEXT: addi a2, sp, 8 + ; RV64-NEXT: call extern + ; RV64-NEXT: csrr a0, vlenb + ; RV64-NEXT: slli a0, a0, 1 + ; RV64-NEXT: add sp, sp, a0 + ; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload + ; RV64-NEXT: addi sp, sp, 48 + ; RV64-NEXT: ret + %a = alloca , align 8 + %b = alloca i64 + %c = alloca i64 + call void @extern(ptr %a) + ret void + } + + define void @rvv_stack_align16() #0 { + ; RV32-LABEL: rvv_stack_align16: + ; RV32: # %bb.0: + ; RV32-NEXT: addi sp, sp, -48 + ; RV32-NEXT: sw ra, 44(sp) # 4-byte Folded Spill + ; RV32-NEXT: csrr a0, vlenb + ; RV32-NEXT: slli a0, a0, 1 + ; RV32-NEXT: sub sp, sp, a0 + ; RV32-NEXT: addi a0, sp, 32 + ; RV32-NEXT: addi a1, sp, 16 + ; RV32-NEXT: addi a2, sp, 8 + ; RV32-NEXT: call extern + ; RV32-NEXT: csrr a0, vlenb + ; RV32-NEXT: slli a0, a0, 1 + ; RV32-NEXT: add sp, sp, a0 + ; RV32-NEXT: lw ra, 44(sp) # 4-byte Folded Reload + ; RV32-NEXT: addi sp, sp, 48 + ; RV32-NEXT: ret + ; + ; RV64-LABEL: rvv_stack_align16: + ; RV64: # %bb.0: + ; RV64-NEXT: addi sp, sp, -48 + ; RV64-NEXT: sd ra, 40(sp) # 8-byte Folded Spill + ; RV64-NEXT: csrr a0, vlenb + ; RV64-NEXT: slli a0, a0, 1 + ; RV64-NEXT: sub sp, sp, a0 + ; RV64-NEXT: addi a0, sp, 32 + ; RV64-NEXT: addi a1, sp, 16 + ; RV64-NEXT: addi a2, sp, 8 + ; RV64-NEXT: call extern + ; RV64-NEXT: csrr a0, vlenb + ; RV64-NEXT: slli a0, a0, 1 + ; RV64-NEXT: add sp, sp, a0 + ; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload + ; RV64-NEXT: addi sp, sp, 48 + ; RV64-NEXT: ret + %a = alloca , align 16 + %b = alloca i64 + %c = alloca i64 + call void @extern(ptr %a) + ret void + } + + define void @rvv_stack_align32() #0 { + ; RV32-LABEL: rvv_stack_align32: + ; RV32: # %bb.0: + ; RV32-NEXT: addi sp, sp, -48 + ; RV32-NEXT: sw ra, 44(sp) # 4-byte Folded Spill + ; RV32-NEXT: sw s0, 40(sp) # 4-byte Folded Spill + ; RV32-NEXT: addi s0, sp, 48 + ; RV32-NEXT: csrr a0, vlenb + ; RV32-NEXT: slli a0, a0, 2 + ; RV32-NEXT: sub sp, sp, a0 + ; RV32-NEXT: andi sp, sp, -32 + ; RV32-NEXT: addi a0, sp, 32 + ; RV32-NEXT: addi a1, sp, 16 + ; RV32-NEXT: addi a2, sp, 8 + ; RV32-NEXT: call extern + ; RV32-NEXT: addi sp, s0, -48 + ; RV32-NEXT: lw ra, 44(sp) # 4-byte Folded Reload + ; RV32-NEXT: lw s0, 40(sp) # 4-byte Folded Reload + ; RV32-NEXT: addi sp, sp, 48 + ; RV32-NEXT: ret + ; + ; RV64-LABEL: rvv_stack_align32: + ; RV64: # %bb.0: + ; RV64-NEXT: addi sp, sp, -80 + ; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill + ; RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill + ; RV64-NEXT: addi s0, sp, 80 + ; RV64-NEXT: csrr a0, vlenb + ; RV64-NEXT: slli a0, a0, 2 + ; RV64-NEXT: sub sp, sp, a0 + ; RV64-NEXT: andi sp, sp, -32 + ; RV64-NEXT: addi a0, sp, 64 + ; RV64-NEXT: addi a1, sp, 40 + ; RV64-NEXT: addi a2, sp, 32 + ; RV64-NEXT: call extern + ; RV64-NEXT: addi sp, s0, -80 + ; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload + ; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload + ; RV64-NEXT: addi sp, sp, 80 + ; RV64-NEXT: ret + %a = alloca , align 32 + %b = alloca i64 + %c = alloca i64 + call void @extern(ptr %a) + ret void + } + + attributes #0 = { nounwind nofree nosync } +... +--- +name: rvv_stack_align8 +alignment: 4 +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: true + hasCalls: true + stackProtector: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: [] + restorePoint: [] +fixedStack: [] +stack: + - { id: 0, name: a, type: default, offset: 0, size: 16, alignment: 8, + stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: b, type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: c, type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.0 (%ir-block.0): + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + $x10 = ADDI %stack.0.a, 0 + $x11 = ADDI %stack.1.b, 0 + $x12 = ADDI %stack.2.c, 0 + PseudoCALL target-flags(riscv-call) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + PseudoRET + +... +--- +name: rvv_stack_align16 +alignment: 4 +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 16 + adjustsStack: true + hasCalls: true + stackProtector: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: [] + restorePoint: [] +fixedStack: [] +stack: + - { id: 0, name: a, type: default, offset: 0, size: 16, alignment: 16, + stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: b, type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: c, type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.0 (%ir-block.0): + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + $x10 = ADDI %stack.0.a, 0 + $x11 = ADDI %stack.1.b, 0 + $x12 = ADDI %stack.2.c, 0 + PseudoCALL target-flags(riscv-call) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + PseudoRET + +... +--- +name: rvv_stack_align32 +alignment: 4 +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 32 + adjustsStack: true + hasCalls: true + stackProtector: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: [] + restorePoint: [] +fixedStack: [] +stack: + - { id: 0, name: a, type: default, offset: 0, size: 16, alignment: 32, + stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: b, type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: c, type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.0 (%ir-block.0): + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + $x10 = ADDI %stack.0.a, 0 + $x11 = ADDI %stack.1.b, 0 + $x12 = ADDI %stack.2.c, 0 + PseudoCALL target-flags(riscv-call) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir new file mode 100644 index 0000000..3faf5f5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir @@ -0,0 +1,523 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v \ +# RUN: -run-pass=phi-node-elimination,register-coalescer,riscv-insert-vsetvli | FileCheck %s + +--- | + define void @xsfmm_same_state( %tile1, %tile2, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) { + entry: + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, %tile1, %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2) + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, %tile1, %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2) + ret void + } + + define void @xsfmm_different_state( %tile1, %tile2, i64 %tm, i64 %tn, i64 %tk) { + entry: + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, %tile1, %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2) + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, %tile1, %tile2, i64 %tm, i64 %tn, i64 %tk, i64 4) + ret void + } + + define void @xsfmm_different_state_bf( %tile1, %tile2, i64 %tm, i64 %tn, i64 %tk) { + entry: + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, %tile1, %tile1, i64 %tm, i64 %tn, i64 %tk, i64 2) + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32bf16(i64 2, %tile2, %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2) + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, %tile1, %tile1, i64 %tm, i64 %tn, i64 %tk, i64 2) + ret void + } + + define @interleave_rvv_and_xsfmm( %tile, i64 %vl, ptr %base) { + entry: + %0 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 1, i64 %vl) + %1 = call @llvm.riscv.vadd.nxv64i8.nxv64i8.i64( poison, %tile, %0, i64 %vl) + call void @llvm.riscv.sf.vste16.i64(i64 1, ptr %base, i64 %vl) + ret %1 + } + + define @interleave_rvv_and_xsfmm2( %tile, i64 %vl, ptr %base) { + entry: + %0 = call @llvm.riscv.vadd.nxv64i8.nxv64i8.i64( poison, %tile, %tile, i64 %vl) + %1 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 1, i64 %vl) + %2 = call @llvm.riscv.vadd.nxv64i8.nxv64i8.i64( poison, %tile, %0, i64 %vl) + call void @llvm.riscv.sf.vste16.i64(i64 1, ptr %base, i64 %vl) + ret %2 + } + + define void @consecutive_xsfmm( %tile, i64 %tm, i64 %tn, i64 %tk, ptr %base) { + entry: + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, %tile, %tile, i64 %tm, i64 %tn, i64 %tk, i64 2) + call void @llvm.riscv.sf.vste16.i64(i64 0, ptr %base, i64 %tn) + ret void + } + + define i64 @vsettnt_max(i64 %vl) { + entry: + %0 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %vl, i64 1, i64 2) + %1 = call i64 @llvm.riscv.sf.vsettnt_max.i64(i64 1, i64 2) + ret i64 %0 + } + + define i64 @single_vsettm(i64 %vl) { + entry: + %0 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %vl, i64 1, i64 2) + ret i64 %0 + } + + define i64 @single_vsettn(i64 %vl) { + entry: + %0 = call i64 @llvm.riscv.sf.vsettn.i64(i64 %vl, i64 1, i64 2) + ret i64 %0 + } + + define i64 @single_vsettk(i64 %vl) { + entry: + %0 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %vl, i64 1, i64 2) + ret i64 %0 + } + + define void @sf_vtzero(i64 %tm, i64 %tn) { + entry: + call void @llvm.riscv.sf.vtzero.i64(i64 1, i64 %tm, i64 %tn, i64 3, i64 4) + ret void + } + + declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64, , , i64, i64, i64, i64) + declare void @llvm.riscv.sf.mm.f.f.i64.nxv32bf16(i64, , , i64, i64, i64, i64) + declare @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64) + declare @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(, , , i64) + declare void @llvm.riscv.sf.vste16.i64(i64, ptr, i64) + declare i64 @llvm.riscv.sf.vsettnt_max.i64(i64, i64) + declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64, i64) + declare i64 @llvm.riscv.sf.vsettn.i64(i64, i64, i64) + declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64, i64) + declare void @llvm.riscv.sf.vtzero.i64(i64, i64, i64, i64, i64) +... +--- +name: xsfmm_same_state +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vrm8 } + - { id: 1, class: vrm8 } + - { id: 2, class: gprnox0 } + - { id: 3, class: gprnox0 } + - { id: 4, class: gprnox0 } +liveins: + - { reg: '$v8m8', virtual-reg: '%0' } + - { reg: '$v8m8', virtual-reg: '%1' } + - { reg: '$x10', virtual-reg: '%2' } + - { reg: '$x11', virtual-reg: '%3' } + - { reg: '$x12', virtual-reg: '%4' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8m8, $v16m8, $x10, $x11, $x12 + ; CHECK-LABEL: name: xsfmm_same_state + ; CHECK: liveins: $v8m8, $v16m8, $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %4:gprnox0 = COPY $x12 + %3:gprnox0 = COPY $x11 + %2:gprnox0 = COPY $x10 + %1:vrm8 = COPY $v16m8 + %0:vrm8 = COPY $v8m8 + PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm + PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm + PseudoRET +... +--- +name: xsfmm_different_state +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vrm8 } + - { id: 1, class: vrm8 } + - { id: 2, class: gprnox0 } + - { id: 3, class: gprnox0 } + - { id: 4, class: gprnox0 } +liveins: + - { reg: '$v8m8', virtual-reg: '%0' } + - { reg: '$v8m8', virtual-reg: '%1' } + - { reg: '$x10', virtual-reg: '%2' } + - { reg: '$x11', virtual-reg: '%3' } + - { reg: '$x12', virtual-reg: '%4' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8m8, $v16m8, $x10, $x11, $x12 + ; CHECK-LABEL: name: xsfmm_different_state + ; CHECK: liveins: $v8m8, $v16m8, $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1544 /* e16, w4 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 4 /* w4 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 4 /* w4 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 4 /* w4 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %4:gprnox0 = COPY $x12 + %3:gprnox0 = COPY $x11 + %2:gprnox0 = COPY $x10 + %1:vrm8 = COPY $v16m8 + %0:vrm8 = COPY $v8m8 + PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm + PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 4, implicit $frm + PseudoRET +... +--- +name: xsfmm_different_state_bf +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vrm8 } + - { id: 1, class: vrm8 } + - { id: 2, class: gprnox0 } + - { id: 3, class: gprnox0 } + - { id: 4, class: gprnox0 } +liveins: + - { reg: '$v8m8', virtual-reg: '%0' } + - { reg: '$v8m8', virtual-reg: '%1' } + - { reg: '$x10', virtual-reg: '%2' } + - { reg: '$x11', virtual-reg: '%3' } + - { reg: '$x12', virtual-reg: '%4' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8m8, $v16m8, $x10, $x11, $x12 + ; CHECK-LABEL: name: xsfmm_different_state_bf + ; CHECK: liveins: $v8m8, $v16m8, $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNTX0X0 killed $x0, 1288 /* e16, w2 */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F_ALT $t2, [[COPY3]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNTX0X0 killed $x0, 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %4:gprnox0 = COPY $x12 + %3:gprnox0 = COPY $x11 + %2:gprnox0 = COPY $x10 + %1:vrm8 = COPY $v16m8 + %0:vrm8 = COPY $v8m8 + PseudoSF_MM_F_F $t2, %0:vrm8, %0:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm + PseudoSF_MM_F_F_ALT $t2, %1:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm + PseudoSF_MM_F_F $t2, %0:vrm8, %0:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm + PseudoRET +... +--- +name: interleave_rvv_and_xsfmm +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vrm8 } + - { id: 1, class: gprnox0 } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: vrm8 } + - { id: 5, class: vrm8 } +liveins: + - { reg: '$v8m8', virtual-reg: '%0' } + - { reg: '$x10', virtual-reg: '%1' } + - { reg: '$x11', virtual-reg: '%2' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8m8, $x10, $x11 + ; CHECK-LABEL: name: interleave_rvv_and_xsfmm + ; CHECK: liveins: $v8m8, $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY $v8m8 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 512 /* e8, w1 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3 /* e8 */, 1 /* w1 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[PseudoSF_VTMV_V_T]], $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4 /* e16 */, 1 /* w1 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]], implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %2:gpr = COPY $x11 + %1:gprnox0 = COPY $x10 + %0:vrm8 = COPY $v8m8 + %3:gpr = ADDI $x0, 1 + %4:vrm8 = PseudoSF_VTMV_V_T %3:gpr, %1:gprnox0, 3, 1 + %5:vrm8 = PseudoVADD_VV_M8 $noreg, %0:vrm8, killed %4:vrm8, %1:gprnox0, 3, 0 + PseudoSF_VSTE16 %3:gpr, %2:gpr, %1:gprnox0, 4, 1 + $v8m8 = COPY %5:vrm8 + PseudoRET implicit $v8m8 +... +--- +name: interleave_rvv_and_xsfmm2 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vrm8 } + - { id: 1, class: gprnox0 } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: vrm8 } + - { id: 5, class: vrm8 } +liveins: + - { reg: '$v8m8', virtual-reg: '%0' } + - { reg: '$x10', virtual-reg: '%1' } + - { reg: '$x11', virtual-reg: '%2' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8m8, $x10, $x11 + ; CHECK-LABEL: name: interleave_rvv_and_xsfmm2 + ; CHECK: liveins: $v8m8, $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY $v8m8 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[COPY2]], $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 512 /* e8, w1 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3 /* e8 */, 1 /* w1 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M8_1:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[PseudoVADD_VV_M8_]], [[PseudoVADD_VV_M8_]], $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4 /* e16 */, 1 /* w1 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_1]], implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %2:gpr = COPY $x11 + %1:gprnox0 = COPY $x10 + %0:vrm8 = COPY $v8m8 + %3:gpr = ADDI $x0, 1 + %4:vrm8 = PseudoVADD_VV_M8 $noreg, %0:vrm8, killed %0:vrm8, %1:gprnox0, 3, 0 + %5:vrm8 = PseudoSF_VTMV_V_T %3:gpr, %1:gprnox0, 3, 1 + %6:vrm8 = PseudoVADD_VV_M8 $noreg, %4:vrm8, killed %4:vrm8, %1:gprnox0, 3, 0 + PseudoSF_VSTE16 %3:gpr, %2:gpr, %1:gprnox0, 4, 1 + $v8m8 = COPY %6:vrm8 + PseudoRET implicit $v8m8 +... +--- +name: consecutive_xsfmm +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vrm8 } + - { id: 1, class: gprnox0 } + - { id: 2, class: gprnox0 } + - { id: 3, class: gprnox0 } + - { id: 4, class: gprnox0 } +liveins: + - { reg: '$v8m8', virtual-reg: '%0' } + - { reg: '$x10', virtual-reg: '%1' } + - { reg: '$x11', virtual-reg: '%2' } + - { reg: '$x12', virtual-reg: '%3' } + - { reg: '$x13', virtual-reg: '%4' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8m8, $x10, $x11, $x12, $x13 + ; CHECK-LABEL: name: consecutive_xsfmm + ; CHECK: liveins: $v8m8, $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprnox0 = COPY $x12 + ; CHECK-NEXT: dead [[COPY4:%[0-9]+]]:gprnox0 = COPY $x13 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY2]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY3]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY]], [[COPY]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY3]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: PseudoSF_VSTE16 [[COPY1]], [[COPY2]], $noreg, 4 /* e16 */, 1 /* w1 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %0:vrm8 = COPY $v8m8 + %1:gprnox0 = COPY $x10 + %2:gprnox0 = COPY $x11 + %3:gprnox0 = COPY $x12 + %4:gprnox0 = COPY $x13 + PseudoSF_MM_F_F $t2, %0:vrm8, %0:vrm8, 7, %1:gprnox0, %2:gprnox0, %3:gprnox0, 4, 2, implicit $frm + PseudoSF_VSTE16 %1:gprnox0, %2:gprnox0, %3:gprnox0, 4, 1 + PseudoRET +... +--- +name: vsettnt_max +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gprnox0 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: vsettnt_max + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 1 /* w1 */, implicit-def $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_1:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4 /* e16 */, 1 /* w1 */, implicit-def $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTM]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprnox0 = COPY $x10 + %1:gprnox0 = PseudoSF_VSETTK %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype + %2:gprnox0 = PseudoSF_VSETTNTX0 $x0, 520, implicit-def $vl, implicit-def $vtype, implicit $vtype + %3:gprnox0 = PseudoSF_VSETTM %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype + $x10 = COPY %3:gprnox0 + PseudoRET implicit $x10 +... +--- +name: single_vsettm +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gprnox0 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: single_vsettm + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4 /* e16 */, 1 /* w1 */, implicit-def $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTM]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprnox0 = COPY $x10 + %1:gprnox0 = PseudoSF_VSETTM %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype + $x10 = COPY %1:gprnox0 + PseudoRET implicit $x10 +... +--- +name: single_vsettn +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gprnox0 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: single_vsettn + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[PseudoSF_VSETTNT:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNT [[COPY]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTNT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprnox0 = COPY $x10 + %1:gprnox0 = PseudoSF_VSETTNT %0:gprnox0, 520, implicit-def $vl, implicit-def $vtype, implicit $vtype + $x10 = COPY %1:gprnox0 + PseudoRET implicit $x10 +... +--- +name: single_vsettk +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gprnox0 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: single_vsettk + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 1 /* w1 */, implicit-def $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTK]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprnox0 = COPY $x10 + %1:gprnox0 = PseudoSF_VSETTK %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype + $x10 = COPY %1:gprnox0 + PseudoRET implicit $x10 +... +--- +name: sf_vtzero +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gprnox0 } + - { id: 1, class: gprnox0 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10, $x11 + ; CHECK-LABEL: name: sf_vtzero + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1536 /* e8, w4 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY]], 3 /* e8 */, 4 /* w4 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_VTZERO_T $t1, $noreg, $noreg, 3 /* e8 */, 4 /* w4 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %0:gprnox0 = COPY $x10 + %1:gprnox0 = COPY $x11 + PseudoSF_VTZERO_T $t1, %0:gprnox0, %1:gprnox0, 3, 4 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/stack-coloring-scalablevec.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/stack-coloring-scalablevec.mir new file mode 100644 index 0000000..03b36b2 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/stack-coloring-scalablevec.mir @@ -0,0 +1,39 @@ +# RUN: llc -mtriple riscv64 -mattr=+m,+v -run-pass=stack-coloring \ +# RUN: -riscv-v-vector-bits-min=512 -o - %s | FileCheck %s + +# Test that a scalable slot (%stack.1) is not merged into a non-scalable one +# (%stack.0) + +# CHECK: {{^}}stack: +# CHECK-NEXT: - { id: 0, +# CHECK: - { id: 1, + +--- | + define dso_local void @dont_merge() { + entry: + %buf1 = alloca <4 x i32> + %buf2 = alloca + ret void + } + +... +--- +name: dont_merge +tracksRegLiveness: true +stack: + - { id: 0, name: buf1, size: 16, alignment: 16 } + - { id: 1, name: buf2, size: 16, alignment: 16, stack-id: scalable-vector } +body: | + bb.0.entry: + liveins: $v8, $v10, $x10, $x11 + + LIFETIME_START %stack.0 + VS1R_V killed renamable $v8, %stack.0 :: (store 16 into %stack.0, align 16) + renamable $v8 = VL1RE8_V killed $x10 :: (load 16 from %stack.0, align 16) + LIFETIME_END %stack.0 + LIFETIME_START %stack.1 + VS2R_V killed renamable $v10m2, %stack.1 :: (store unknown-size into %stack.1, align 16) + renamable $v10m2 = VL2RE8_V killed $x11 :: (load unknown-size from %stack.1, align 16) + LIFETIME_END %stack.1 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.mir new file mode 100644 index 0000000..58a01df --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.mir @@ -0,0 +1,324 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc %s -mtriple=riscv64 -mattr=+v -run-pass=greedy,virtregrewriter,stack-slot-coloring -o - | FileCheck %s + +--- +name: nop_copy_elim_m1 +alignment: 4 +tracksRegLiveness: true +frameInfo: + maxAlignment: 4 + localFrameSize: 4 +stack: + - { id: 0, size: 1, alignment: 4, local-offset: -4 } +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + ; CHECK-LABEL: name: nop_copy_elim_m1 + ; CHECK: $v0 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v1 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v2 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v3 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v4 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v5 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v6 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v7 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v8 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v9 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v10 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v11 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v12 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v13 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v14 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v15 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v16 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v17 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v18 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v19 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v20 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v21 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v22 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v23 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v24 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v25 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v26 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v27 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v28 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v29 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v30 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: renamable $v31 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: VS1R_V killed renamable $v31, %stack.1 :: (store () into %stack.1) + ; CHECK-NEXT: renamable $v31 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: VS1R_V killed renamable $v31, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: renamable $v31 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: VS1R_V killed renamable $v31, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: renamable $v31 = VL1RE8_V %stack.1 :: (load () from %stack.1) + ; CHECK-NEXT: VS1R_V killed renamable $v31, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v0, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v1, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v2, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v3, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v4, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v5, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v6, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v7, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v8, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v9, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v10, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v11, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v12, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v13, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v14, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v15, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v16, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v17, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v18, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v19, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v20, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v21, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v22, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v23, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v24, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v25, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v26, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v27, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v28, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v29, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v30, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: PseudoRET + $v0 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v1 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v2 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v3 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v4 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v5 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v6 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v7 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v8 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v9 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v10 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v11 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v12 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v13 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v14 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v15 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v16 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v17 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v18 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v19 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v20 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v21 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v22 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v23 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v24 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v25 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v26 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v27 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v28 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v29 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v30 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + + %0:vr = VL1RE8_V %stack.0 :: (volatile load unknown-size) + %1:vr = VL1RE8_V %stack.0 :: (volatile load unknown-size) + VS1R_V %1:vr, %stack.0 :: (volatile store unknown-size) + + %2:vr = COPY %0:vr + + %3:vr = VL1RE8_V %stack.0 :: (volatile load unknown-size) + VS1R_V %3:vr, %stack.0 :: (volatile store unknown-size) + VS1R_V %2:vr, %stack.0 :: (volatile store unknown-size) + + VS1R_V $v0, %stack.0 :: (volatile store unknown-size) + VS1R_V $v1, %stack.0 :: (volatile store unknown-size) + VS1R_V $v2, %stack.0 :: (volatile store unknown-size) + VS1R_V $v3, %stack.0 :: (volatile store unknown-size) + VS1R_V $v4, %stack.0 :: (volatile store unknown-size) + VS1R_V $v5, %stack.0 :: (volatile store unknown-size) + VS1R_V $v6, %stack.0 :: (volatile store unknown-size) + VS1R_V $v7, %stack.0 :: (volatile store unknown-size) + VS1R_V $v8, %stack.0 :: (volatile store unknown-size) + VS1R_V $v9, %stack.0 :: (volatile store unknown-size) + VS1R_V $v10, %stack.0 :: (volatile store unknown-size) + VS1R_V $v11, %stack.0 :: (volatile store unknown-size) + VS1R_V $v12, %stack.0 :: (volatile store unknown-size) + VS1R_V $v13, %stack.0 :: (volatile store unknown-size) + VS1R_V $v14, %stack.0 :: (volatile store unknown-size) + VS1R_V $v15, %stack.0 :: (volatile store unknown-size) + VS1R_V $v16, %stack.0 :: (volatile store unknown-size) + VS1R_V $v17, %stack.0 :: (volatile store unknown-size) + VS1R_V $v18, %stack.0 :: (volatile store unknown-size) + VS1R_V $v19, %stack.0 :: (volatile store unknown-size) + VS1R_V $v20, %stack.0 :: (volatile store unknown-size) + VS1R_V $v21, %stack.0 :: (volatile store unknown-size) + VS1R_V $v22, %stack.0 :: (volatile store unknown-size) + VS1R_V $v23, %stack.0 :: (volatile store unknown-size) + VS1R_V $v24, %stack.0 :: (volatile store unknown-size) + VS1R_V $v25, %stack.0 :: (volatile store unknown-size) + VS1R_V $v26, %stack.0 :: (volatile store unknown-size) + VS1R_V $v27, %stack.0 :: (volatile store unknown-size) + VS1R_V $v28, %stack.0 :: (volatile store unknown-size) + VS1R_V $v29, %stack.0 :: (volatile store unknown-size) + VS1R_V $v30, %stack.0 :: (volatile store unknown-size) + PseudoRET + +... +--- +name: nop_copy_elim_m2 +alignment: 4 +tracksRegLiveness: true +frameInfo: + maxAlignment: 4 + localFrameSize: 4 +stack: + - { id: 0, size: 1, alignment: 4, local-offset: -4 } +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + ; CHECK-LABEL: name: nop_copy_elim_m2 + ; CHECK: $v0 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v1 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v2 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v3 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v4 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v5 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v6 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v7 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v8 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v9 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v10 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v11 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v12 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v13 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v14 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v15 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v16 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v17 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v18 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v19 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v20 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v21 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v22 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v23 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v24 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v25 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v26 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v27 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v28 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: $v29 = VL1RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: renamable $v30m2 = VL2RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: VS2R_V killed renamable $v30m2, %stack.1 :: (store () into %stack.1, align 8) + ; CHECK-NEXT: renamable $v30m2 = VL2RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: VS2R_V killed renamable $v30m2, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: renamable $v30m2 = VL2RE8_V %stack.0 :: (volatile load unknown-size, align 1) + ; CHECK-NEXT: VS2R_V killed renamable $v30m2, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: renamable $v30m2 = VL2RE8_V %stack.1 :: (load () from %stack.1, align 8) + ; CHECK-NEXT: VS2R_V killed renamable $v30m2, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v0, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v1, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v2, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v3, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v4, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v5, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v6, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v7, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v8, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v9, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v10, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v11, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v12, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v13, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v14, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v15, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v16, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v17, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v18, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v19, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v20, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v21, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v22, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v23, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v24, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v25, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v26, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v27, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v28, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: VS1R_V $v29, %stack.0 :: (volatile store unknown-size, align 1) + ; CHECK-NEXT: PseudoRET + $v0 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v1 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v2 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v3 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v4 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v5 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v6 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v7 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v8 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v9 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v10 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v11 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v12 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v13 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v14 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v15 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v16 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v17 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v18 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v19 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v20 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v21 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v22 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v23 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v24 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v25 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v26 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v27 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v28 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + $v29 = VL1RE8_V %stack.0 :: (volatile load unknown-size) + + %0:vrm2 = VL2RE8_V %stack.0 :: (volatile load unknown-size) + %1:vrm2 = VL2RE8_V %stack.0 :: (volatile load unknown-size) + VS2R_V %1:vrm2, %stack.0 :: (volatile store unknown-size) + + %2:vrm2 = COPY %0:vrm2 + + %3:vrm2 = VL2RE8_V %stack.0 :: (volatile load unknown-size) + VS2R_V %3:vrm2, %stack.0 :: (volatile store unknown-size) + VS2R_V %2:vrm2, %stack.0 :: (volatile store unknown-size) + + VS1R_V $v0, %stack.0 :: (volatile store unknown-size) + VS1R_V $v1, %stack.0 :: (volatile store unknown-size) + VS1R_V $v2, %stack.0 :: (volatile store unknown-size) + VS1R_V $v3, %stack.0 :: (volatile store unknown-size) + VS1R_V $v4, %stack.0 :: (volatile store unknown-size) + VS1R_V $v5, %stack.0 :: (volatile store unknown-size) + VS1R_V $v6, %stack.0 :: (volatile store unknown-size) + VS1R_V $v7, %stack.0 :: (volatile store unknown-size) + VS1R_V $v8, %stack.0 :: (volatile store unknown-size) + VS1R_V $v9, %stack.0 :: (volatile store unknown-size) + VS1R_V $v10, %stack.0 :: (volatile store unknown-size) + VS1R_V $v11, %stack.0 :: (volatile store unknown-size) + VS1R_V $v12, %stack.0 :: (volatile store unknown-size) + VS1R_V $v13, %stack.0 :: (volatile store unknown-size) + VS1R_V $v14, %stack.0 :: (volatile store unknown-size) + VS1R_V $v15, %stack.0 :: (volatile store unknown-size) + VS1R_V $v16, %stack.0 :: (volatile store unknown-size) + VS1R_V $v17, %stack.0 :: (volatile store unknown-size) + VS1R_V $v18, %stack.0 :: (volatile store unknown-size) + VS1R_V $v19, %stack.0 :: (volatile store unknown-size) + VS1R_V $v20, %stack.0 :: (volatile store unknown-size) + VS1R_V $v21, %stack.0 :: (volatile store unknown-size) + VS1R_V $v22, %stack.0 :: (volatile store unknown-size) + VS1R_V $v23, %stack.0 :: (volatile store unknown-size) + VS1R_V $v24, %stack.0 :: (volatile store unknown-size) + VS1R_V $v25, %stack.0 :: (volatile store unknown-size) + VS1R_V $v26, %stack.0 :: (volatile store unknown-size) + VS1R_V $v27, %stack.0 :: (volatile store unknown-size) + VS1R_V $v28, %stack.0 :: (volatile store unknown-size) + VS1R_V $v29, %stack.0 :: (volatile store unknown-size) + PseudoRET + +... + diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir new file mode 100644 index 0000000..559dc12 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir @@ -0,0 +1,773 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc %s -mtriple=riscv64 -mattr=+v -enable-subreg-liveness -run-pass=init-undef -o - | FileCheck %s +# RUN: llc %s -mtriple=riscv64 -mattr=+v -enable-subreg-liveness -passes=init-undef -o - | FileCheck %s + +... +--- +name: test_M4_sub_vrm1_0 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M4_sub_vrm1_0 + ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_0 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_1 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_1 + ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm4 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vr = IMPLICIT_DEF + %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_0 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm4 = IMPLICIT_DEF + early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5/* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M4_sub_vrm1_1 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M4_sub_vrm1_1 + ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_1 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_1 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:zzz_vrmf8 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_0 + ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm4 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vr = IMPLICIT_DEF + %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_1 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm4 = IMPLICIT_DEF + early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M4_sub_vrm1_2 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M4_sub_vrm1_2 + ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_2 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_0 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_3 + ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm4 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vr = IMPLICIT_DEF + %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_2 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm4 = IMPLICIT_DEF + early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M4_sub_vrm1_3 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M4_sub_vrm1_3 + ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_3 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_0 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_2 + ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm4 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vr = IMPLICIT_DEF + %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_3 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm4 = IMPLICIT_DEF + early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M4_sub_vrm2_0 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M4_sub_vrm2_0 + ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_0 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_1 + ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG1]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm4 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vrm2 = IMPLICIT_DEF + %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm2_0 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm4 = IMPLICIT_DEF + early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M4_sub_vrm2_1 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M4_sub_vrm2_1 + ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_1 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_0 + ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG1]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm4 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vrm2 = IMPLICIT_DEF + %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm2_1 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm4 = IMPLICIT_DEF + early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + + +--- +name: test_M8_sub_vrm1_0 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm1_0 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_0 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_1 + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_1 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vr = IMPLICIT_DEF + %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_0 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm1_1 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm1_1 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_1 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_1 + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_0 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vr = IMPLICIT_DEF + %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_1 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm1_2 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm1_2 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_2 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_0 + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_3 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vr = IMPLICIT_DEF + %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_2 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm1_3 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm1_3 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_3 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_0 + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_2 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vr = IMPLICIT_DEF + %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_3 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm1_4 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm1_4 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_4 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_3 + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_5 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vr = IMPLICIT_DEF + %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_4 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm1_5 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm1_5 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_5 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_3 + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_4 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vr = IMPLICIT_DEF + %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_5 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm1_6 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm1_6 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_6 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_2 + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_7 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vr = IMPLICIT_DEF + %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_6 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm1_7 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm1_7 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_7 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_2 + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_6 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vr = IMPLICIT_DEF + %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_7 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm2_0 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm2_0 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_0 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_1 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vrm2 = IMPLICIT_DEF + %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_0 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm2_1 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm2_1 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_1 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_0 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vrm2 = IMPLICIT_DEF + %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_1 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm2_2 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm2_2 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_2 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_3 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vrm2 = IMPLICIT_DEF + %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_2 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm2_3 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm2_3 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_3 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_2 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vrm2 = IMPLICIT_DEF + %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_3 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm4_0 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm4_0 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M4_]], %subreg.sub_vrm4_0 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG1]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vrm4 = IMPLICIT_DEF + %5:vrm4 = PseudoVLE32_V_M4 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm4_0 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... + +--- +name: test_M8_sub_vrm4_1 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_M8_sub_vrm4_1 + ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %pt:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M4_]], %subreg.sub_vrm4_1 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4 = INIT_UNDEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG1]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %pt:vrm4 = IMPLICIT_DEF + %5:vrm4 = PseudoVLE32_V_M4 %pt, killed %7:gpr, 0, 5, 0 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm4_1 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + %pt2:vrm8 = IMPLICIT_DEF + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype + %2:gpr = ADDI $x0, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir new file mode 100644 index 0000000..299d6dd --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir @@ -0,0 +1,65 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc %s -mtriple=riscv64 -mattr=v -riscv-v-vector-bits-min=128 -run-pass=finalize-isel -o - | FileCheck %s +# RUN: llc %s -mtriple=riscv64 -mattr=v -riscv-v-vector-bits-min=128 -passes=finalize-isel -o - | FileCheck %s + +# This test makes sure we peak through the COPY instruction between the +# IMPLICIT_DEF and PseudoVLE64_V_M8_MASK in order to select the tail agnostic +# policy. The test is working if the second argument to PseudoVSETVLI has bit 6 +# set. + +--- | + ; ModuleID = 'test.ll' + source_filename = "test.ll" + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" + target triple = "riscv64" + + ; Function Attrs: nounwind + define @masked_load_nxv8i64(ptr %a, %mask) #0 { + %load = call @llvm.masked.load.nxv8i64.p0(ptr %a, i32 8, %mask, undef) + ret %load + } + + attributes #0 = { nounwind "target-features"="+v" } + +... +--- +name: masked_load_nxv8i64 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: vr } + - { id: 2, class: vrm8nov0 } + - { id: 3, class: vrm8 } + - { id: 4, class: vrm8nov0 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$v0', virtual-reg: '%1' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0 (%ir-block.0): + liveins: $x10, $v0 + + ; CHECK-LABEL: name: masked_load_nxv8i64 + ; CHECK: liveins: $x10, $v0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: $v0 = COPY [[COPY]] + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8nov0 = COPY [[DEF]] + ; CHECK-NEXT: [[PseudoVLE64_V_M8_MASK:%[0-9]+]]:vrm8nov0 = PseudoVLE64_V_M8_MASK [[COPY2]], [[COPY1]], $v0, -1 /* vl=VLMAX */, 6 /* e64 */, 1 /* ta, mu */ :: (load (s512) from %ir.a, align 8) + ; CHECK-NEXT: $v8m8 = COPY [[PseudoVLE64_V_M8_MASK]] + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:vr = COPY $v0 + %0:gpr = COPY $x10 + $v0 = COPY %1 + %3:vrm8 = IMPLICIT_DEF + %4:vrm8nov0 = COPY %3 + %2:vrm8nov0 = PseudoVLE64_V_M8_MASK %4, %0, $v0, -1, 6, 1 :: (load (s512) from %ir.a, align 8) + $v8m8 = COPY %2 + PseudoRET implicit $v8m8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir new file mode 100644 index 0000000..3e7f596 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir @@ -0,0 +1,89 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -enable-subreg-liveness -run-pass init-undef -run-pass machineverifier %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv32 -mattr=+v -enable-subreg-liveness -passes=init-undef,verify %s -o - | FileCheck %s + +--- | + source_filename = "" + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" + target triple = "riscv64" + + define @undef_early_clobber_chain(ptr %p) #0 { + entry: + %0 = tail call @llvm.riscv.vrgather.vx.nxv2f32.i64( undef, undef, i64 0, i64 0) + ret %0 + } + + attributes #0 = { "target-features"="+v" } + +... +--- +name: undef_early_clobber_chain +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHContTarget: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gpr, preferred-register: '' } + - { id: 1, class: vr, preferred-register: '' } + - { id: 2, class: vr, preferred-register: '' } + - { id: 3, class: vr, preferred-register: '' } +liveins: [] +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: [] + restorePoint: [] +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + ; CHECK-LABEL: name: undef_early_clobber_chain + ; CHECK: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vr = INIT_UNDEF + ; CHECK-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef [[DEF]], [[INIT_UNDEF]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8 = COPY %1 + ; CHECK-NEXT: PseudoRET implicit $v8 + %2:vr = IMPLICIT_DEF + dead $x0 = PseudoVSETIVLI 0, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef %2, undef %2, 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + $v8 = COPY %1 + PseudoRET implicit $v8 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir new file mode 100644 index 0000000..8fcf816 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir @@ -0,0 +1,2425 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s + +--- +name: vop_vi +body: | + bb.0: + ; CHECK-LABEL: name: vop_vi + ; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vop_vi_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vop_vi_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vop_vi_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vop_vi_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vop_vv +body: | + bb.0: + ; CHECK-LABEL: name: vop_vv + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vop_vv_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vop_vv_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vop_vv_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vop_vv_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vwop_vv_vd +body: | + bb.0: + ; CHECK-LABEL: name: vwop_vv_vd + ; CHECK: early-clobber %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vwop_vv_vd_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vwop_vv_vd_incompatible_eew + ; CHECK: early-clobber %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vwop_vv_vd_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vwop_vv_vd_incompatible_emul + ; CHECK: early-clobber %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 4 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vwop_vv_vd_passthru_use +body: | + bb.0: + ; CHECK-LABEL: name: vwop_vv_vd_passthru_use + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVWADD_VV_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %z +... +--- +name: vwop_vv_vd_passthru_use_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vwop_vv_vd_passthru_use_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 %x, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVWADD_VV_MF2 %x, $noreg, $noreg, 1, 4 /* e16 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %z +... +--- +name: vwop_vv_vd_passthru_use_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vwop_vv_vd_passthru_use_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF4 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVWADD_VV_MF4 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %z +... +--- +name: vwop_vv_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vwop_vv_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8m2 = COPY %y +... +--- +name: vwop_vv_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vwop_vv_vs2_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8m2 = COPY %y +... +--- +name: vwop_vv_vs2_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vwop_vv_vs2_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVWADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vwop_vv_vs1 +body: | + bb.0: + ; CHECK-LABEL: name: vwop_vv_vs1 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8m2 = COPY %y +... +--- +name: vwop_vv_vs1_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vwop_vv_vs1_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_VV_M1 $noreg, $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrm2 = PseudoVWADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 + $v8m2 = COPY %y +... +--- +name: vwop_vv_vs1_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vwop_vv_vs1_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vwop_wv_vd +body: | + bb.0: + ; CHECK-LABEL: name: vwop_wv_vd + ; CHECK: early-clobber %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vwop_wv_vd_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vwop_wv_vd_incompatible_eew + ; CHECK: early-clobber %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vwop_wv_vd_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vwop_wv_vd_incompatible_emul + ; CHECK: early-clobber %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 4 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vwop_wv_vd_passthru_use +body: | + bb.0: + ; CHECK-LABEL: name: vwop_wv_vd_passthru_use + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF2 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVWADD_WV_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %z +... +--- +name: vwop_wv_vd_passthru_use_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vwop_wv_vd_passthru_use_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF2 %x, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVWADD_WV_MF2 %x, $noreg, $noreg, 1, 4 /* e16 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %z +... +--- +name: vwop_wv_vd_passthru_use_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vwop_wv_vd_passthru_use_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF4 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVWADD_WV_MF4 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %z +... +--- +name: vwop_wv_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vwop_wv_vs2 + ; CHECK: %x:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vrm2 = PseudoVWADD_WV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8m2 = COPY %y +... +--- +name: vwop_wv_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vwop_wv_vs2_incompatible_eew + ; CHECK: %x:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrm2 = PseudoVWADD_WV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8m2 = COPY %y +... +--- +name: vwop_wv_vs2_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vwop_wv_vs2_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVWADD_WV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vwop_wv_vs1 +body: | + bb.0: + ; CHECK-LABEL: name: vwop_wv_vs1 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8m2 = COPY %y +... +--- +name: vwop_wv_vs1_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vwop_wv_vs1_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8m2 = COPY %y +... +--- +name: vwop_wv_vs1_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vwop_wv_vs1_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8m2 = COPY %y +... +--- +name: tied_vwop_wv_vs1 +body: | + bb.0: + ; CHECK-LABEL: name: tied_vwop_wv_vs1 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 + $v8m2 = COPY %y +... +--- +name: tied_vwop_wv_vs1_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: tied_vwop_wv_vs1_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 + $v8m2 = COPY %y +... +--- +name: tied_vwop_wv_vs1_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: tied_vwop_wv_vs1_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 + $v8m2 = COPY %y +... +--- +name: vop_vf2_vd +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf2_vd + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF2_M1 $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVZEXT_VF2_M1 $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf2_vd_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf2_vd_incompatible_eew + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF2_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVZEXT_VF2_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf2_vd_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf2_vd_incompatible_emul + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF2_MF2 $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVZEXT_VF2_MF2 $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf2_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf2_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf2_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf2_vs2_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf2_vs2_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf2_vs2_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf4_vd +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf4_vd + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF4_M1 $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVZEXT_VF4_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf4_vd_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf4_vd_incompatible_eew + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF4_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVZEXT_VF4_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf4_vd_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf4_vd_incompatible_emul + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF4_MF2 $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVZEXT_VF4_MF2 $noreg, $noreg, -1, 5 /* e32 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf4_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf4_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf4_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf4_vs2_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf4_vs2_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf4_vs2_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf8_vd +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf8_vd + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, -1, 6 /* e64 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 6 /* e64 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf8_vd_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf8_vd_incompatible_eew + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, -1, 6 /* e64 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf8_vd_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf8_vd_incompatible_emul + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, -1, 6 /* e64 */, 0 + %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 6 /* e64 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf8_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf8_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_MF8 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF8 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1, 6 /* e64 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf8_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf8_vs2_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_MF8 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF8 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1, 6 /* e64 */, 0 + $v8 = COPY %y +... +--- +name: vop_vf8_vs2_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vop_vf8_vs2_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1, 6 /* e64 */, 0 + $v8 = COPY %y +... +--- +name: vnop_wv_vd +body: | + bb.0: + ; CHECK-LABEL: name: vnop_wv_vd + ; CHECK: early-clobber %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vnop_wv_vd_unsupported_eew +body: | + bb.0: + ; CHECK-LABEL: name: vnop_wv_vd_unsupported_eew + ; CHECK: early-clobber %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vnop_wv_vd_unsupported_emul +body: | + bb.0: + ; CHECK-LABEL: name: vnop_wv_vd_unsupported_emul + ; CHECK: %x:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vnop_wv_vd_passthru_use +body: | + bb.0: + ; CHECK-LABEL: name: vnop_wv_vd_passthru_use + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVNSRL_WV_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVNSRL_WV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %z +... +--- +name: vnop_wv_vd_passthru_use_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vnop_wv_vd_passthru_use_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVNSRL_WV_M1 %x, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVNSRL_WV_M1 %x, $noreg, $noreg, 1, 4 /* e16 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %z +... +--- +name: vnop_wv_vd_passthru_use_unsupported_emul +body: | + bb.0: + ; CHECK-LABEL: name: vnop_wv_vd_passthru_use_unsupported_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVNSRL_WV_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %z +... +--- +name: vnop_wv_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vnop_wv_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vnop_wv_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vnop_wv_vs2_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vnop_wv_vs2_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vnop_wv_vs2_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vnop_wv_vs1 +body: | + bb.0: + ; CHECK-LABEL: name: vnop_wv_vs1 + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vnop_wv_vs1_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vnop_wv_vs1_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vnop_wv_vs1_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vnop_wv_vs1_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vfnop_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vfnop_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0 /* frm=rne */, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vfnop_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vfnop_vs2_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0 /* frm=rne */, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vfnop_vs2_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vfnop_vs2_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0 /* frm=rne */, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vseN_v +body: | + bb.0: + ; CHECK-LABEL: name: vseN_v + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, 1 /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + PseudoVSE8_V_M1 %x, $noreg, 1, 3 /* e8 */ +... +--- +name: vseN_v_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vseN_v_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, 1 /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + PseudoVSE8_V_M1 %x, $noreg, 1, 3 /* e8 */ +... +--- +name: vseN_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vseN_v_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSE8_V_MF2 %x, $noreg, 1 /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + PseudoVSE8_V_MF2 %x, $noreg, 1, 3 /* e8 */ +... +--- +name: vsm_v +body: | + bb.0: + ; CHECK-LABEL: name: vsm_v + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: PseudoVSM_V_B8 %x, $noreg, 1 /* vl */, 0 /* e8 */ + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + PseudoVSM_V_B8 %x, $noreg, 1, 0 +... +--- +name: vsm_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vsm_v_incompatible_emul + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: PseudoVSM_V_B16 %x, $noreg, 1 /* vl */, 0 /* e8 */ + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + PseudoVSM_V_B16 %x, $noreg, 1, 0 +... +--- +name: vleN_v +body: | + bb.0: + ; CHECK-LABEL: name: vleN_v + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vleN_v_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vleN_v_incompatible_eew + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vleN_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vleN_v_incompatible_emul + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vlm_v +body: | + bb.0: + ; CHECK-LABEL: name: vlm_v + ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0 + %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 + $v8 = COPY %y +... +--- +name: vlm_v_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vlm_v_incompatible_eew + ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vlm_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vlm_v_incompatible_emul + ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0 + %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 + $v8 = COPY %y +... +--- +name: vsseN_v +body: | + bb.0: + ; CHECK-LABEL: name: vsseN_v + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSSE8_V_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + PseudoVSSE8_V_M1 %x, $noreg, $noreg, 1, 3 /* e8 */ +... +--- +name: vsseN_v_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vsseN_v_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSSE8_V_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + PseudoVSSE8_V_M1 %x, $noreg, $noreg, 1, 3 /* e8 */ +... +--- +name: vsseN_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vsseN_v_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSSE8_V_MF2 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + PseudoVSSE8_V_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */ +... +--- +name: vsuxeiN_v_data +body: | + bb.0: + ; CHECK-LABEL: name: vsuxeiN_v_data + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */ +... +--- +name: vsuxeiN_v_data_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vsuxeiN_v_data_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */ +... +--- +name: vsuxeiN_v_data_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vsuxeiN_v_data_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSUXEI8_V_MF2_MF2 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + PseudoVSUXEI8_V_MF2_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */ +... +--- +name: vsuxeiN_v_idx +body: | + bb.0: + ; CHECK-LABEL: name: vsuxeiN_v_idx + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */ +... +--- +name: vsuxeiN_v_idx_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vsuxeiN_v_idx_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */ +... +--- +name: vsuxeiN_v_idx_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vsuxeiN_v_idx_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + PseudoVSUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */ +... +--- +name: vluxeiN_v_data +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_data + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vluxeiN_v_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vluxeiN_v_data_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_data_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vluxeiN_v_idx +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_idx + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVLUXEI8_V_MF2_M1 $noreg, $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVLUXEI8_V_MF2_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vluxeiN_v_idx_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_idx_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vluxeiN_v_idx_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_idx_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vluxeiN_v_vd +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_vd + ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vluxeiN_v_vd_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_vd_incompatible_eew + ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vluxeiN_vd_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_vd_incompatible_emul + ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmop_mm +body: | + bb.0: + ; CHECK-LABEL: name: vmop_mm + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 + $v8 = COPY %y +... +--- +name: vmop_mm_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vmop_mm_incompatible_eew + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmop_mm_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmop_mm_incompatible_emul + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 + $v8 = COPY %y +... +--- +name: vmop_mm_mask +body: | + bb.0: + ; CHECK-LABEL: name: vmop_mm_mask + ; CHECK: %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmop_mm_mask_larger_emul_user +body: | + bb.0: + ; CHECK-LABEL: name: vmop_mm_mask_larger_emul_user + ; CHECK: %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0 + $v8m2 = COPY %y +... +--- +name: vmop_mm_mask_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmop_mm_mask_incompatible_emul + ; CHECK: %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmop_vv +body: | + bb.0: + ; CHECK-LABEL: name: vmop_vv + ; CHECK: %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ + %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 + $v8 = COPY %y +... +--- +name: vmop_vv_maskuser +body: | + bb.0: + ; CHECK-LABEL: name: vmop_vv_maskuser + ; CHECK: %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ + %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmop_vv_maskuser_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vmop_vv_maskuser_incompatible_eew + ; CHECK: %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ + %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vmop_vv_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmop_vv_incompatible_emul + ; CHECK: %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ + %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 + $v8 = COPY %y +... +--- +name: vmop_vv_maskuser_incompaible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmop_vv_maskuser_incompaible_emul + ; CHECK: %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ + %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmop_vv_maskuser_larger_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmop_vv_maskuser_larger_emul + ; CHECK: %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ + %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0 + $v8m2 = COPY %y +... +--- +name: vmop_vv_consumer_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vmop_vv_consumer_incompatible_eew + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMSEQ_VV_M1 $noreg, %x, 1 /* vl */, 4 /* e16 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVMSEQ_VV_M1 $noreg, %x, 1, 4 /* e16 */ + $v8 = COPY %y +... +--- +name: vmop_vv_consumer_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmop_vv_consumer_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMSEQ_VV_MF2 $noreg, %x, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVMSEQ_VV_MF2 $noreg, %x, 1, 3 /* e8 */ + $v8 = COPY %y +... +--- +name: vmop_vv_passthru_use +body: | + bb.0: + ; CHECK-LABEL: name: vmop_vv_passthru_use + ; CHECK: %x:vrnov0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 1 /* ta, mu */ + ; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vrnov0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e1 */ + %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1 + %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e1 */ + $v8 = COPY %z +... +--- +name: vmop_vv_passthru_use_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vmop_vv_passthru_use_incompatible_eew + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 1 /* ta, mu */ + ; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1 + %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e1 */ + $v8 = COPY %z +... +--- +name: vmop_vv_passthru_use_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmop_vv_passthru_use_incompatible_emul + ; CHECK: %x:vrnov0 = PseudoVMAND_MM_B16 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 1 /* ta, mu */ + ; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vrnov0 = PseudoVMAND_MM_B16 $noreg, $noreg, -1, 0 /* e1 */ + %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1 + %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e1 */ + $v8 = COPY %z +... +--- +name: vmerge_vim +body: | + bb.0: + ; CHECK-LABEL: name: vmerge_vim + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */ + $v8 = COPY %y +... +--- +name: vmerge_vim_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vmerge_vim_incompatible_eew + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */ + $v8 = COPY %y +... +--- +name: vmerge_vim_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmerge_vim_incompatible_emul + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_MF2 $noreg, %x, 9, $v0, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrnov0 = PseudoVMERGE_VIM_MF2 $noreg, %x, 9, $v0, 1, 3 /* e8 */ + $v8 = COPY %y +... +--- +name: vmerge_vxm +body: | + bb.0: + ; CHECK-LABEL: name: vmerge_vxm + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */ + $v8 = COPY %y +... +--- +name: vmerge_vxm_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vmerge_vxm_incompatible_eew + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */ + $v8 = COPY %y +... +--- +name: vmerge_vxm_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmerge_vxm_incompatible_emul + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VXM_MF2 $noreg, %x, $noreg, $v0, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrnov0 = PseudoVMERGE_VXM_MF2 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */ + $v8 = COPY %y +... +--- +name: vmerge_vvm +body: | + bb.0: + ; CHECK-LABEL: name: vmerge_vvm + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */ + $v8 = COPY %y +... +--- +name: vmerge_vvm_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vmerge_vvm_incompatible_eew + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */ + $v8 = COPY %y +... +--- +name: vmerge_vvm_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmerge_vvm_incompatible_emul + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_MF2 $noreg, $noreg, %x, $v0, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vrnov0 = PseudoVMERGE_VVM_MF2 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */ + $v8 = COPY %y +... +--- +name: vmv_v_i +body: | + bb.0: + ; CHECK-LABEL: name: vmv_v_i + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_M1 %x, 9, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmv_v_i_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vmv_v_i_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_M1 %x, 9, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmv_v_i_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmv_v_i_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_MF2 %x, 9, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVMV_V_I_MF2 %x, 9, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmv_v_x +body: | + bb.0: + ; CHECK-LABEL: name: vmv_v_x + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmv_v_x_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vmv_v_x_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmv_v_x_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmv_v_x_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_X_MF2 %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVMV_V_X_MF2 %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmv_v_v +body: | + bb.0: + ; CHECK-LABEL: name: vmv_v_v + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmv_v_v_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vmv_v_v_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmv_v_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmv_v_v_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_MF2 $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVMV_V_V_MF2 $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: viota_m_dest +body: | + bb.0: + ; CHECK-LABEL: name: viota_m_dest + ; CHECK: early-clobber %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: viota_m_dest_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: viota_m_dest_incompatible_eew + ; CHECK: early-clobber %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: viota_m_dest_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: viota_m_dest_incompatible_emul + ; CHECK: early-clobber %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: viota_m_dest_passthru_use +body: | + bb.0: + ; CHECK-LABEL: name: viota_m_dest_passthru_use + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVIOTA_M_M1 %x, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %z +... +--- +name: viota_m_dest_passthru_use_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: viota_m_dest_passthru_use_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVIOTA_M_M1 %x, $noreg, 1, 4 /* e16 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %z +... +--- +name: viota_m_dest_passthru_use_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: viota_m_dest_passthru_use_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_MF2 %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVIOTA_M_MF2 %x, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %z +... +--- +name: viota_m_mask +body: | + bb.0: + ; CHECK-LABEL: name: viota_m_mask + ; CHECK: %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ + %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: viota_m_mask_scale_mask +body: | + bb.0: + ; CHECK-LABEL: name: viota_m_mask_scale_mask + ; CHECK: early-clobber %x:vr = PseudoVMSEQ_VV_M2 $noreg, $noreg, 1 /* vl */, 4 /* e16 */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMSEQ_VV_M2 $noreg, $noreg, -1, 4 /* e16 */ + %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: viota_m_mask_incompatible_emul_from_sew +body: | + bb.0: + ; CHECK-LABEL: name: viota_m_mask_incompatible_emul_from_sew + ; CHECK: %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0 + %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: viota_m_mask_incompatible_emul_from_lmul +body: | + bb.0: + ; CHECK-LABEL: name: viota_m_mask_incompatible_emul_from_lmul + ; CHECK: %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_MF2 $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0 + %y:vr = PseudoVIOTA_M_MF2 $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vred_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vred_vs1 +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs1 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vred_vs1_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs1_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vred_vs1_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs1_vs2_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vred_vs1_vs2_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs1_vs2_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_MF2_E8 $noreg, %x, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_MF2_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vred_other_user_is_vl0 +body: | + bb.0: + ; CHECK-LABEL: name: vred_other_user_is_vl0 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: $v9 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 + $v8 = COPY %y + $v9 = COPY %z +... +--- +name: vred_both_vl0 +body: | + bb.0: + ; CHECK-LABEL: name: vred_both_vl0 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: $v9 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 + $v8 = COPY %y + $v9 = COPY %z +... +--- +name: vred_vl0_and_vlreg +body: | + bb.0: + ; CHECK-LABEL: name: vred_vl0_and_vlreg + ; CHECK: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, %vl /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: $v9 = COPY %z + %vl:gprnox0 = COPY $x1 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, %vl, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 + $v8 = COPY %y + $v9 = COPY %z +... +--- +name: vred_vlreg_and_vl0 +body: | + bb.0: + ; CHECK-LABEL: name: vred_vlreg_and_vl0 + ; CHECK: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: $v9 = COPY %z + %vl:gprnox0 = COPY $x1 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 3 /* e8 */, 0 + $v8 = COPY %y + $v9 = COPY %z +... +--- +name: vred_other_user_is_vl2 +body: | + bb.0: + ; CHECK-LABEL: name: vred_other_user_is_vl2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: $v9 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2, 3 /* e8 */, 0 + $v8 = COPY %y + $v9 = COPY %z +... +--- +name: vwred_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vwred_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vwred_vs1 +body: | + bb.0: + ; CHECK-LABEL: name: vwred_vs1 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vwred_vs1_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vwred_vs1_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vwred_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vwred_vs2_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vwred_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vwred_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF2_E8 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVWREDSUM_VS_MF2_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vfred_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vfred_vs2 + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 5 /* e32 */, 0 + %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vfred_vs1 +body: | + bb.0: + ; CHECK-LABEL: name: vfred_vs1 + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, $noreg, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 5 /* e32 */, 0 + %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vfred_vs1_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vfred_vs1_vs2 + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 5 /* e32 */, 0 + %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, %x, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vfred_vs1_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vfred_vs1_vs2_incompatible_eew + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 6 /* e64 */, 0 + %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, %x, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vfred_vs1_vs2_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vfred_vs1_vs2_incompatible_emul + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_MF2_E32 $noreg, %x, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 5 /* e32 */, 0 + %y:vr = PseudoVFREDMAX_VS_MF2_E32 $noreg, %x, %x, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vwred_passthru_use +body: | + bb.0: + ; CHECK-LABEL: name: vwred_passthru_use + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF2_E8 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVWREDSUM_VS_MF2_E8 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %z +... +--- +name: vwred_passthru_use_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vwred_passthru_use_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF2_E8 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVWREDSUM_VS_MF2_E8 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %z +... +--- +name: vwred_passthru_use_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vwred_passthru_use_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF4_E8 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVWREDSUM_VS_MF4_E8 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %z +... +--- +name: vfirst_v +body: | + bb.0: + ; CHECK-LABEL: name: vfirst_v + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:gpr = PseudoVFIRST_M_B8 %x, 1 /* vl */, 0 /* e8 */ + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + %y:gpr = PseudoVFIRST_M_B8 %x, 1, 0 +... +--- +name: vfirst_v_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vfirst_v_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:gpr = PseudoVFIRST_M_B8 %x, 1 /* vl */, 0 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:gpr = PseudoVFIRST_M_B8 %x, 1, 0 +... +--- +name: vfirst_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vfirst_v_incompatible_emul + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:gpr = PseudoVFIRST_M_B16 %x, 1 /* vl */, 0 /* e8 */ + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + %y:gpr = PseudoVFIRST_M_B16 %x, 1, 0 +... +--- +name: vcpop_v +body: | + bb.0: + ; CHECK-LABEL: name: vcpop_v + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:gpr = PseudoVCPOP_M_B8 %x, 1 /* vl */, 0 /* e8 */ + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + %y:gpr = PseudoVCPOP_M_B8 %x, 1, 0 +... +--- +name: vcopop_v_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vcopop_v_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:gpr = PseudoVCPOP_M_B8 %x, 1 /* vl */, 0 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:gpr = PseudoVCPOP_M_B8 %x, 1, 0 +... +--- +name: vcpop_v_incompaitble_emul +body: | + bb.0: + ; CHECK-LABEL: name: vcpop_v_incompaitble_emul + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:gpr = PseudoVCPOP_M_B16 %x, 1 /* vl */, 0 /* e8 */ + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + %y:gpr = PseudoVCPOP_M_B16 %x, 1, 0 +... +--- +name: vmclr_m +body: | + bb.0: + ; CHECK-LABEL: name: vmclr_m + ; CHECK: %x:vr = PseudoVMCLR_M_B8 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMCLR_M_B8 -1, 0 + %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 + $v8 = COPY %y +... +--- +name: vmclr_m_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vmclr_m_incompatible_eew + ; CHECK: %x:vr = PseudoVMCLR_M_B8 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMCLR_M_B8 -1, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmclr_m_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmclr_m_incompatible_emul + ; CHECK: %x:vr = PseudoVMCLR_M_B8 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMCLR_M_B8 -1, 0 + %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 + $v8 = COPY %y +... +--- +name: vmset_m +body: | + bb.0: + ; CHECK-LABEL: name: vmset_m + ; CHECK: %x:vr = PseudoVMSET_M_B8 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMSET_M_B8 -1, 0 + %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 + $v8 = COPY %y +... +--- +name: vmset_m_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vmset_m_incompatible_eew + ; CHECK: %x:vr = PseudoVMSET_M_B8 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMSET_M_B8 -1, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vmset_m_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vmset_m_incompatible_emul + ; CHECK: %x:vr = PseudoVMSET_M_B8 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVMSET_M_B8 -1, 0 + %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 + $v8 = COPY %y +... +--- +name: vrgatherei16_vv +body: | + bb.0: + ; CHECK-LABEL: name: vrgatherei16_vv + ; CHECK: early-clobber %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vrgatherei16_vv_incompatible_data_eew +body: | + bb.0: + ; CHECK-LABEL: name: vrgatherei16_vv_incompatible_data_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vrgatherei16_vv_incompatible_index_eew +body: | + bb.0: + ; CHECK-LABEL: name: vrgatherei16_vv_incompatible_index_eew + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vrgatherei16_vv_incompatible_dest_emul +body: | + bb.0: + ; CHECK-LABEL: name: vrgatherei16_vv_incompatible_dest_emul + ; CHECK: early-clobber %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 + %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vrgatherei16_vv_incompatible_source_emul +body: | + bb.0: + ; CHECK-LABEL: name: vrgatherei16_vv_incompatible_source_emul + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 + %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vrgatherei16_vv_incompatible_index_emul +body: | + bb.0: + ; CHECK-LABEL: name: vrgatherei16_vv_incompatible_index_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vsseg3e32_v +body: | + bb.0: + liveins: $v8 + + ; CHECK-LABEL: name: vsseg3e32_v + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 + ; CHECK-NEXT: PseudoVSSEG3E32_V_M1 killed [[INSERT_SUBREG2]], $noreg, 1 /* vl */, 5 /* e32 */ + %0:vr = COPY $v8 + %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ + %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + %6:vrn3m1 = IMPLICIT_DEF + %5:vrn3m1 = INSERT_SUBREG %6, %0, %subreg.sub_vrm1_0 + %7:vrn3m1 = INSERT_SUBREG %5, %1, %subreg.sub_vrm1_1 + %8:vrn3m1 = INSERT_SUBREG %7, %2, %subreg.sub_vrm1_2 + PseudoVSSEG3E32_V_M1 killed %8, $noreg, 1, 5 /* e32 */ +... +--- +name: vsseg3e64_v_incompatible_eew +body: | + bb.0: + liveins: $v8 + + ; CHECK-LABEL: name: vsseg3e64_v_incompatible_eew + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 + ; CHECK-NEXT: PseudoVSSEG3E64_V_M1 killed [[INSERT_SUBREG2]], $noreg, 1 /* vl */, 6 /* e64 */ + %0:vr = COPY $v8 + %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ + %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + %6:vrn3m1 = IMPLICIT_DEF + %5:vrn3m1 = INSERT_SUBREG %6, %0, %subreg.sub_vrm1_0 + %7:vrn3m1 = INSERT_SUBREG %5, %1, %subreg.sub_vrm1_1 + %8:vrn3m1 = INSERT_SUBREG %7, %2, %subreg.sub_vrm1_2 + PseudoVSSEG3E64_V_M1 killed %8, $noreg, 1, 6 /* e64 */ +... +--- +name: vsseg3e32_v_incompatible_emul +body: | + bb.0: + liveins: $v8 + + ; CHECK-LABEL: name: vsseg3e32_v_incompatible_emul + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 + ; CHECK-NEXT: PseudoVSSEG3E32_V_M1 killed [[INSERT_SUBREG2]], $noreg, 1 /* vl */, 6 /* e64 */ + %0:vr = COPY $v8 + %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ + %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + %6:vrn3m1 = IMPLICIT_DEF + %5:vrn3m1 = INSERT_SUBREG %6, %0, %subreg.sub_vrm1_0 + %7:vrn3m1 = INSERT_SUBREG %5, %1, %subreg.sub_vrm1_1 + %8:vrn3m1 = INSERT_SUBREG %7, %2, %subreg.sub_vrm1_2 + PseudoVSSEG3E32_V_M1 killed %8, $noreg, 1, 6 /* e64 */ +... +--- +name: vsseg3e32_v_incompatible_insert_subreg +body: | + bb.0: + + ; CHECK-LABEL: name: vsseg3e32_v_incompatible_insert_subreg + ; CHECK: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[PseudoVADD_VV_M2_]], %subreg.sub_vrm2_0 + ; CHECK-NEXT: PseudoVSSEG3E32_V_M1 killed [[INSERT_SUBREG]], $noreg, 1 /* vl */, 5 /* e32 */ + %2:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + %6:vrn3m1 = IMPLICIT_DEF + %5:vrn3m1 = INSERT_SUBREG %6, %2, %subreg.sub_vrm2_0 + PseudoVSSEG3E32_V_M1 killed %5, $noreg, 1, 5 /* e32 */ +... +--- +name: vssseg3e32_v +body: | + bb.0: + liveins: $v8 + + ; CHECK-LABEL: name: vssseg3e32_v + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 + ; CHECK-NEXT: PseudoVSSSEG3E32_V_M1 killed [[INSERT_SUBREG2]], $noreg, $noreg, 1 /* vl */, 5 /* e32 */ + %0:vr = COPY $v8 + %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ + %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + %6:vrn3m1 = IMPLICIT_DEF + %5:vrn3m1 = INSERT_SUBREG %6, %0, %subreg.sub_vrm1_0 + %7:vrn3m1 = INSERT_SUBREG %5, %1, %subreg.sub_vrm1_1 + %8:vrn3m1 = INSERT_SUBREG %7, %2, %subreg.sub_vrm1_2 + PseudoVSSSEG3E32_V_M1 killed %8, $noreg, $noreg, 1, 5 /* e32 */ +... +--- +name: vsuxseg3ei64_v +body: | + bb.0: + liveins: $v8 + + ; CHECK-LABEL: name: vsuxseg3ei64_v + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 + ; CHECK-NEXT: PseudoVSUXSEG3EI64_V_M2_M1 killed [[INSERT_SUBREG2]], $noreg, $noreg, 1 /* vl */, 5 /* e32 */ + %0:vr = COPY $v8 + %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ + %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + %6:vrn3m1 = IMPLICIT_DEF + %5:vrn3m1 = INSERT_SUBREG %6, %0, %subreg.sub_vrm1_0 + %7:vrn3m1 = INSERT_SUBREG %5, %1, %subreg.sub_vrm1_1 + %8:vrn3m1 = INSERT_SUBREG %7, %2, %subreg.sub_vrm1_2 + PseudoVSUXSEG3EI64_V_M2_M1 killed %8, $noreg, $noreg, 1, 5 /* e32 */ +... +--- +name: vsuxseg3ei64_v_incompatible_data_eew +body: | + bb.0: + liveins: $v8 + + ; CHECK-LABEL: name: vsuxseg3ei64_v_incompatible_data_eew + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10 /* vl */, 6 /* e64 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 + ; CHECK-NEXT: PseudoVSUXSEG3EI64_V_M2_M1 killed [[INSERT_SUBREG2]], $noreg, $noreg, 1 /* vl */, 5 /* e32 */ + %0:vr = COPY $v8 + %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 6 /* e64 */, 3 /* ta, ma */ + %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 6 /* e64 */, 3 /* ta, ma */ + %6:vrn3m1 = IMPLICIT_DEF + %5:vrn3m1 = INSERT_SUBREG %6, %0, %subreg.sub_vrm1_0 + %7:vrn3m1 = INSERT_SUBREG %5, %1, %subreg.sub_vrm1_1 + %8:vrn3m1 = INSERT_SUBREG %7, %2, %subreg.sub_vrm1_2 + PseudoVSUXSEG3EI64_V_M2_M1 killed %8, $noreg, $noreg, 1, 5 /* e32 */ +... +--- +name: vsuxseg3ei32_v_index +body: | + bb.0: + + ; CHECK-LABEL: name: vsuxseg3ei32_v_index + ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSUXSEG3EI32_V_M1_M2 $noreg, $noreg, [[PseudoVADD_VV_M1_]], 1 /* vl */, 6 /* e64 */ + %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + PseudoVSUXSEG3EI32_V_M1_M2 $noreg, $noreg, %2, 1, 6 /* e64 */ +... +--- +name: vsuxseg3ei32_v_incompatible_index_eew +body: | + bb.0: + + ; CHECK-LABEL: name: vsuxseg3ei32_v_incompatible_index_eew + ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSUXSEG3EI32_V_M1_M2 $noreg, $noreg, [[PseudoVADD_VV_M1_]], 1 /* vl */, 6 /* e64 */ + %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 6 /* e64 */, 3 /* ta, ma */ + PseudoVSUXSEG3EI32_V_M1_M2 $noreg, $noreg, %2, 1, 6 /* e64 */ +... +--- +name: vsoxseg3ei64_v +body: | + bb.0: + liveins: $v8 + + ; CHECK-LABEL: name: vsoxseg3ei64_v + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 + ; CHECK-NEXT: PseudoVSOXSEG3EI64_V_M2_M1 killed [[INSERT_SUBREG2]], $noreg, $noreg, 1 /* vl */, 5 /* e32 */ + %0:vr = COPY $v8 + %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ + %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + %6:vrn3m1 = IMPLICIT_DEF + %5:vrn3m1 = INSERT_SUBREG %6, %0, %subreg.sub_vrm1_0 + %7:vrn3m1 = INSERT_SUBREG %5, %1, %subreg.sub_vrm1_1 + %8:vrn3m1 = INSERT_SUBREG %7, %2, %subreg.sub_vrm1_2 + PseudoVSOXSEG3EI64_V_M2_M1 killed %8, $noreg, $noreg, 1, 5 /* e32 */ +... +--- +name: vsoxseg3ei32_v_index +body: | + bb.0: + + ; CHECK-LABEL: name: vsoxseg3ei32_v_index + ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSOXSEG3EI32_V_M1_M2 $noreg, $noreg, [[PseudoVADD_VV_M1_]], 1 /* vl */, 6 /* e64 */ + %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + PseudoVSOXSEG3EI32_V_M1_M2 $noreg, $noreg, %2, 1, 6 /* e64 */ +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir new file mode 100644 index 0000000..9600339 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir @@ -0,0 +1,15 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -o - -mtriple=riscv32 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s + +--- +name: vec_instr_with_scalar_def +tracksRegLiveness: true +isSSA: true +body: | + bb.0: + ; CHECK-LABEL: name: vec_instr_with_scalar_def + ; CHECK: [[PseudoVMNAND_MM_B8_:%[0-9]+]]:vr = PseudoVMNAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 killed [[PseudoVMNAND_MM_B8_]], -1 /* vl=VLMAX */, 0 /* e8 */ + %1:vr = PseudoVMNAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */ + %2:gpr = PseudoVCPOP_M_B1 killed %1, -1, 0 /* e8 */ +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir new file mode 100644 index 0000000..d2b6ba3 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir @@ -0,0 +1,1110 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v,+zvfbfmin -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s + +--- +name: vnsrl_wv_user +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: vnsrl_wv_user + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %vl:gprnox0 = COPY $x1 + %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ + %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */ + $v8 = COPY %y +... +--- +name: vredsum_vv_user +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: vredsum_vv_user + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E64 $noreg, %x, $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: $v9 = COPY %z + %vl:gprnox0 = COPY $x1 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ + %y:vr = PseudoVREDSUM_VS_M1_E64 $noreg, %x, $noreg, -1, 6 /* e64 */, 0 /* tu, mu */ + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 5 /* e32 */, 0 /* tu, mu */ + $v8 = COPY %y + $v9 = COPY %z +... +--- +name: use_largest_common_vl_imm_imm +body: | + bb.0: + ; CHECK-LABEL: name: use_largest_common_vl_imm_imm + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: $v9 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2, 3 /* e8 */, 0 + $v8 = COPY %y + $v9 = COPY %z +... +--- +name: use_largest_common_vl_same_reg +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: use_largest_common_vl_same_reg + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %vl /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: $v9 = COPY %z + %vl:gprnox0 = COPY $x1 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 3 /* e8 */, 0 + $v8 = COPY %y + $v9 = COPY %z +... +--- +name: use_largest_common_vl_diff_regs +body: | + bb.0: + liveins: $x1, $x2 + ; CHECK-LABEL: name: use_largest_common_vl_diff_regs + ; CHECK: liveins: $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %vl0:gprnox0 = COPY $x1 + ; CHECK-NEXT: %vl1:gprnox0 = COPY $x2 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl0 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: $v9 = COPY %z + %vl0:gprnox0 = COPY $x1 + %vl1:gprnox0 = COPY $x2 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl0, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl1, 3 /* e8 */, 0 + $v8 = COPY %y + $v9 = COPY %z +... +--- +name: use_largest_common_vl_imm_reg +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: use_largest_common_vl_imm_reg + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: $v9 = COPY %z + %vl:gprnox0 = COPY $x1 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y + $v9 = COPY %z +... +--- +name: use_largest_common_vl_imm_vlmax +body: | + bb.0: + ; CHECK-LABEL: name: use_largest_common_vl_imm_vlmax + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: $v9 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, -1, 3 /* e8 */, 0 + $v8 = COPY %y + $v9 = COPY %z +... +--- +name: vfcvt_x_f_v_nofpexcept +body: | + bb.0: + ; CHECK-LABEL: name: vfcvt_x_f_v_nofpexcept + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e32 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vfcvt_x_f_v_fpexcept +body: | + bb.0: + ; CHECK-LABEL: name: vfcvt_x_f_v_fpexcept + ; CHECK: %x:vr = PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e32 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 + $v8 = COPY %y +... +--- +name: vfncvtbf16_f_f_w_nofpexcept +body: | + bb.0: + ; CHECK-LABEL: name: vfncvtbf16_f_f_w_nofpexcept + ; CHECK: early-clobber %x:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, $noreg, 7 /* frm=dyn */, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $frm + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, $noreg, 7, -1, 4 /* e16 */, 0 /* tu, mu */, implicit $frm + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 + $v8 = COPY %y +... +--- +name: vfsqrt_nofpexcept +body: | + bb.0: + ; CHECK-LABEL: name: vfsqrt_nofpexcept + ; CHECK: %x:vrm2 = nofpexcept PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7 /* frm=dyn */, 6 /* vl */, 5 /* e32 */, 3 /* ta, ma */, implicit $frm + ; CHECK-NEXT: early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7 /* frm=dyn */, 6 /* vl */, 4 /* e16 */, 3 /* ta, ma */, implicit $frm + ; CHECK-NEXT: $v8 = COPY %y + %x:vrm2 = nofpexcept PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7, 8, 5, 3, implicit $frm + early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7, 6, 4, 3, implicit $frm + $v8 = COPY %y +... +--- +name: vfsqrt_fpexcept +body: | + bb.0: + ; CHECK-LABEL: name: vfsqrt_fpexcept + ; CHECK: %x:vrm2 = PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7 /* frm=dyn */, 8 /* vl */, 5 /* e32 */, 3 /* ta, ma */, implicit $frm + ; CHECK-NEXT: early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7 /* frm=dyn */, 6 /* vl */, 4 /* e16 */, 3 /* ta, ma */, implicit $frm + ; CHECK-NEXT: $v8 = COPY %y + %x:vrm2 = PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7, 8, 5, 3, implicit $frm + early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7, 6, 4, 3, implicit $frm + $v8 = COPY %y +... +--- +name: vfrsqrt7_nofpexcept +body: | + bb.0: + ; CHECK-LABEL: name: vfrsqrt7_nofpexcept + ; CHECK: %x:vrm2 = nofpexcept PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vrm2 = nofpexcept PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 7, 5, 0 + %y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 + $v8m2 = COPY %y +... +--- +name: vfrsqrt7_fpexcept +body: | + bb.0: + ; CHECK-LABEL: name: vfrsqrt7_fpexcept + ; CHECK: %x:vrm2 = PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 7 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vrm2 = PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 7, 5, 0 + %y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 + $v8m2 = COPY %y +... +--- +name: vwadd_tied_vs1 +body: | + bb.0: + ; CHECK-LABEL: name: vwadd_tied_vs1 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8m2 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8m2 = COPY %y +... +--- +name: crossbb +body: | + ; CHECK-LABEL: name: crossbb + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: %a1:vr = PseudoVADD_VV_M1 $noreg, %c, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %a2:vr = PseudoVADD_VV_M1 $noreg, %a1, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %a2 + ; CHECK-NEXT: PseudoRET + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: %b1:vr = PseudoVADD_VV_M1 $noreg, %c, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %b2:vr = PseudoVADD_VV_M1 $noreg, %b1, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %b2 + ; CHECK-NEXT: PseudoRET + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %c:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: BEQ $x1, $x0, %bb.1 + ; CHECK-NEXT: PseudoBR %bb.2 + bb.0: + PseudoBR %bb.3 + bb.1: + %a1:vr = PseudoVADD_VV_M1 $noreg, %c, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + %a2:vr = PseudoVADD_VV_M1 $noreg, %a1, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %a2 + PseudoRET + bb.2: + %b1:vr = PseudoVADD_VV_M1 $noreg, %c, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + %b2:vr = PseudoVADD_VV_M1 $noreg, %b1, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %b2 + PseudoRET + bb.3: + liveins: $x1 + %c:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + BEQ $x1, $x0, %bb.1 + PseudoBR %bb.2 +... +--- +name: unreachable +body: | + ; CHECK-LABEL: name: unreachable + ; CHECK: bb.0: + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %x + ; CHECK-NEXT: PseudoRET + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: PseudoRET + bb.0: + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %x + PseudoRET + bb.1: + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %y + PseudoRET +... +--- +# Can reduce %x even though %y uses it as a passthru, because %y's inactive elements aren't demanded +name: passthru_not_demanded +body: | + bb.0: + ; CHECK-LABEL: name: passthru_not_demanded + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %z +... +--- +# Can't reduce %x because %y uses it as a passthru, and %y's inactive elements are demanded by %z +name: passthru_demanded +body: | + bb.0: + ; CHECK-LABEL: name: passthru_demanded + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 2, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %z +... +--- +# Can reduce %x even though %y uses it as a passthru, because %y's inactive elements aren't demanded +name: passthru_not_demanded_passthru_chain +body: | + bb.0: + ; CHECK-LABEL: name: passthru_not_demanded_passthru_chain + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 %y, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %a:vr = PseudoVADD_VV_M1 %z, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %b:vr = PseudoVADD_VV_M1 $noreg, %a, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %b + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %z:vr = PseudoVADD_VV_M1 %y, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %a:vr = PseudoVADD_VV_M1 %z, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %b:vr = PseudoVADD_VV_M1 $noreg, %a, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %b +... +--- +# Can't reduce %x because %y uses it as a passthru, and %y's inactive elements are ultimately demanded in %b +name: passthru_demanded_passthru_chain +body: | + bb.0: + ; CHECK-LABEL: name: passthru_demanded_passthru_chain + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 %y, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %a:vr = PseudoVADD_VV_M1 %z, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %b:vr = PseudoVADD_VV_M1 $noreg, %a, $noreg, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %b + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %z:vr = PseudoVADD_VV_M1 %y, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %a:vr = PseudoVADD_VV_M1 %z, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %b:vr = PseudoVADD_VV_M1 $noreg, %a, $noreg, 2, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %b +... +--- +name: vxsat_dead +body: | + bb.0: + ; CHECK-LABEL: name: vxsat_dead + ; CHECK: %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vxsat + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vxsat + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %y +... +--- +name: vxsat_not_dead +body: | + bb.0: + ; CHECK-LABEL: name: vxsat_not_dead + ; CHECK: %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit-def $vxsat + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */, implicit-def $vxsat + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %y +... +--- +name: vxsat_instr_dead +body: | + bb.0: + ; CHECK-LABEL: name: vxsat_instr_dead + ; CHECK: %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vxsat + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vxsat + %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %y +... +--- +name: copy +body: | + bb.0: + ; CHECK-LABEL: name: copy + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = COPY %x + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + %y:vr = COPY %x + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %z +... +--- +name: copy_multiple_users +body: | + bb.0: + ; CHECK-LABEL: name: copy_multiple_users + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = COPY %x + ; CHECK-NEXT: %z0:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z1:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 3 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z0 + ; CHECK-NEXT: $v9 = COPY %z1 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + %y:vr = COPY %x + %z0:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %z1:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 3, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %z0 + $v9 = COPY %z1 +... +--- +name: copy_user_invalid_sew +body: | + bb.0: + ; CHECK-LABEL: name: copy_user_invalid_sew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = COPY %x + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + %y:vr = COPY %x + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + $v8 = COPY %z +... +--- +name: phi +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: phi + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: BNE $noreg, $noreg, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: %y:vr = PHI %w, %bb.0, %x, %bb.1 + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + bb.0: + %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + BNE $noreg, $noreg, %bb.2 + bb.1: + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + bb.2: + %y:vr = PHI %w, %bb.0, %x, %bb.1 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %z +... +--- +name: phi_user_invalid_sew +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: phi_user_invalid_sew + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: BNE $noreg, $noreg, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: %y:vr = PHI %w, %bb.0, %x, %bb.1 + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + bb.0: + %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + BNE $noreg, $noreg, %bb.2 + bb.1: + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + bb.2: + %y:vr = PHI %w, %bb.0, %x, %bb.1 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + $v8 = COPY %z +... +--- +name: phi_different_incoming_sew +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: phi_different_incoming_sew + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: BNE $noreg, $noreg, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: %y:vr = PHI %w, %bb.0, %x, %bb.1 + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + bb.0: + %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + BNE $noreg, $noreg, %bb.2 + bb.1: + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ + bb.2: + %y:vr = PHI %w, %bb.0, %x, %bb.1 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %z +... +--- +name: phi_cycle_direct +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: phi_cycle_direct + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %y:vr = PHI %x, %bb.0, %y, %bb.1 + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + ; CHECK-NEXT: PseudoBR %bb.1 + bb.0: + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + bb.1: + %y:vr = PHI %x, %bb.0, %y, %bb.1 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %z + PseudoBR %bb.1 +... +--- +name: phi_cycle_indirect +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: phi_cycle_indirect + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %y:vr = PHI %x, %bb.0, %z, %bb.1 + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + ; CHECK-NEXT: PseudoBR %bb.1 + bb.0: + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + bb.1: + %y:vr = PHI %x, %bb.0, %z, %bb.1 + %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + $v8 = COPY %z + PseudoBR %bb.1 +... +--- +name: EMUL_is_unknown +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: EMUL_is_unknown + ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: [[PseudoVMOR_MM_B4_:%[0-9]+]]:vmv0 = PseudoVMOR_MM_B4 [[PseudoVMCLR_M_B4_]], [[PseudoVMCLR_M_B4_]], 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: [[PseudoVMV_S_X:%[0-9]+]]:vr = PseudoVMV_S_X $noreg, [[COPY]], 1 /* vl */, 5 /* e32 */ + ; CHECK-NEXT: [[PseudoVMV_V_I_M8_:%[0-9]+]]:vrm8 = PseudoVMV_V_I_M8 $noreg, 0, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVREDMAX_VS_M8_E32_MASK:%[0-9]+]]:vrnov0 = PseudoVREDMAX_VS_M8_E32_MASK $noreg, killed [[PseudoVMV_V_I_M8_]], killed [[PseudoVMV_S_X]], [[PseudoVMOR_MM_B4_]], 1 /* vl */, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S killed [[PseudoVREDMAX_VS_M8_E32_MASK]], 5 /* e32 */ + ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %2:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */ + %3:vmv0 = PseudoVMOR_MM_B4 %2, %2, 1, 0 /* e8 */ + %4:gpr = COPY $x0 + %5:vr = PseudoVMV_S_X $noreg, %4, 1, 5 /* e32 */ + %6:vrm8 = PseudoVMV_V_I_M8 $noreg, 0, 1, 5 /* e32 */, 0 /* tu, mu */ + %7:vrnov0 = PseudoVREDMAX_VS_M8_E32_MASK $noreg, killed %6, killed %5, %3, 1, 5 /* e32 */, 1 /* ta, mu */ + %9:gpr = PseudoVMV_X_S killed %7, 5 /* e32 */ + $x10 = COPY %9 + PseudoRET implicit $x10 +... +--- +name: vleff_imm +body: | + bb.0: + ; CHECK-LABEL: name: vleff_imm + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */ + %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */ + PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */ +... +--- +name: vleff_reg_dominates +body: | + bb.0: + liveins: $x8 + ; CHECK-LABEL: name: vleff_reg_dominates + ; CHECK: liveins: $x8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %avl /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl /* vl */, 3 /* e8 */ + %avl:gprnox0 = COPY $x8 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */ + %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */ + PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */ +... +--- +name: vleff_reg_doesnt_dominate +body: | + bb.0: + liveins: $x8 + ; CHECK-LABEL: name: vleff_reg_doesnt_dominate + ; CHECK: liveins: $x8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %avl /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */ + %avl:gprnox0 = COPY $x8 + %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */ + PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */ +... +--- +name: vleff_mask_imm +body: | + bb.0: + ; CHECK-LABEL: name: vleff_mask_imm + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: %y:vrnov0, %vl:gprnox0 = PseudoVLE8FF_V_M1_MASK $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl /* vl */, 3 /* e8 */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */ + %y:vrnov0, %vl:gprnox0 = PseudoVLE8FF_V_M1_MASK $noreg, $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */ + PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */ +... +--- +name: insert_subreg_bitcast_no_peekthru +body: | + bb.0: + liveins: $v8, $v9, $v10 + + ; We should not peekthrough an INSERT_SUBREG if any of its users is not a segmented store or another INSERT_SUBREG. + ; CHECK-LABEL: name: insert_subreg_bitcast_no_peekthru + ; CHECK: liveins: $v8, $v9, $v10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v10 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn4m1 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn4m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn4m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[COPY1]], %subreg.sub_vrm1_1 + ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn4m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_2 + ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrn4m1 = INSERT_SUBREG [[INSERT_SUBREG2]], [[COPY2]], %subreg.sub_vrm1_3 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm4 = COPY [[INSERT_SUBREG3]] + ; CHECK-NEXT: PseudoVSE32_V_M4 [[COPY3]], $noreg, 1 /* vl */, 5 /* e32 */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, [[PseudoVADD_VV_M1_]], $noreg, 10 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: $v10 = COPY [[PseudoVADD_VV_M1_1]] + ; CHECK-NEXT: PseudoRET implicit $v10 + %0:vr = COPY $v8 + %1:vr = COPY $v9 + %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + %3:vr = COPY $v10 + %6:vrn4m1 = IMPLICIT_DEF + %5:vrn4m1 = INSERT_SUBREG %6, %0, %subreg.sub_vrm1_0 + %7:vrn4m1 = INSERT_SUBREG %5, %1, %subreg.sub_vrm1_1 + %8:vrn4m1 = INSERT_SUBREG %7, %2, %subreg.sub_vrm1_2 + %9:vrn4m1 = INSERT_SUBREG %8, %3, %subreg.sub_vrm1_3 + %10:vrm4 = COPY %9 + PseudoVSE32_V_M4 %10:vrm4, $noreg, 1, 5 /* e32 */ + %11:vr = PseudoVADD_VV_M1 $noreg, %2, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ + $v10 = COPY %11 + PseudoRET implicit $v10 +... +--- +name: recurrence +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: recurrence + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %start:vr = PseudoVMV_V_I_M1 $noreg, 0, %avl /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %phi:vr = PHI %start, %bb.0, %inc, %bb.1 + ; CHECK-NEXT: %inc:vr = PseudoVADD_VI_M1 $noreg, %phi, 1, %avl /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: BNE $noreg, $noreg, %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: PseudoVSE8_V_M1 %inc, $noreg, %avl /* vl */, 3 /* e8 */ + bb.0: + liveins: $x8 + %avl:gprnox0 = COPY $x8 + %start:vr = PseudoVMV_V_I_M1 $noreg, 0, -1, 3 /* e8 */, 3, /* ta, ma */ + PseudoBR %bb.1 + bb.1: + %phi:vr = PHI %start, %bb.0, %inc, %bb.1 + %inc:vr = PseudoVADD_VI_M1 $noreg, %phi, 1, -1, 3 /* e8 */, 3 /* ta, ma */ + BNE $noreg, $noreg, %bb.1 + bb.2: + PseudoVSE8_V_M1 %inc, $noreg, %avl, 3 /* e8 */ +... +--- +name: recurrence_cant_reduce +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: recurrence_cant_reduce + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x8, $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl1:gprnox0 = COPY $x8 + ; CHECK-NEXT: %avl2:gprnox0 = COPY $x8 + ; CHECK-NEXT: %start:vr = PseudoVMV_V_I_M1 $noreg, 0, %avl1 /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %phi:vr = PHI %start, %bb.0, %inc, %bb.1 + ; CHECK-NEXT: %inc:vr = PseudoVADD_VI_M1 $noreg, %phi, 1, %avl1 /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: BNE $noreg, $noreg, %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: PseudoVSE8_V_M1 %inc, $noreg, %avl2 /* vl */, 3 /* e8 */ + bb.0: + liveins: $x8, $x9 + %avl1:gprnox0 = COPY $x8 + %avl2:gprnox0 = COPY $x8 + %start:vr = PseudoVMV_V_I_M1 $noreg, 0, -1, 3 /* e8 */, 3, /* ta, ma */ + PseudoBR %bb.1 + bb.1: + %phi:vr = PHI %start, %bb.0, %inc, %bb.1 + %inc:vr = PseudoVADD_VI_M1 $noreg, %phi, 1, %avl1, 3 /* e8 */, 3 /* ta, ma */ + BNE $noreg, $noreg, %bb.1 + bb.2: + PseudoVSE8_V_M1 %inc, $noreg, %avl2, 3 /* e8 */ +... +--- +name: dbg_value +body: | + bb.0: + ; CHECK-LABEL: name: dbg_value + ; CHECK: DBG_VALUE %0:vr + DBG_VALUE %0:vr +... +--- +name: vslidedown_vx +tracksRegLiveness: true +body: | + bb.0: + liveins: $x8 + ; CHECK-LABEL: name: vslidedown_vx + ; CHECK: liveins: $x8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:gprnox0 = COPY $x8 + ; CHECK-NEXT: %y:gprnox0 = ADDI %x, -1 + ; CHECK-NEXT: %v:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %x /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %w:vr = PseudoVSLIDEDOWN_VX_M1 $noreg, %v, %y, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + %x:gpr = COPY $x8 + %y:gprnox0 = ADDI %x, -1 + %v:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ + %w:vr = PseudoVSLIDEDOWN_VX_M1 $noreg, %v, %y, 1, 5 /* e32 */, 0 /* tu, mu */ +... +--- +# Make sure we ignore LIs (ADDI $x0, -1) +name: vslidedown_vx_li +tracksRegLiveness: true +body: | + bb.0: + liveins: $x8 + ; CHECK-LABEL: name: vslidedown_vx_li + ; CHECK: liveins: $x8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %y:gprnox0 = ADDI $x0, -1 + ; CHECK-NEXT: %v:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %w:vr = PseudoVSLIDEDOWN_VX_M1 $noreg, %v, %y, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + %y:gprnox0 = ADDI $x0, -1 + %v:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ + %w:vr = PseudoVSLIDEDOWN_VX_M1 $noreg, %v, %y, 1, 5 /* e32 */, 0 /* tu, mu */ +... +--- +name: vabs_v +body: | + bb.0: + liveins: $x8 + ; CHECK-LABEL: name: vabs_v + ; CHECK: liveins: $x8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = PseudoVABS_V_M1 $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVABS_V_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + $v8 = COPY %y +... +--- +name: vl_doesnt_dominate_sink +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: vl_doesnt_dominate_sink + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 + %vl:gprnox0 = COPY $x1 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vl_doesnt_dominate_sink_load +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: vl_doesnt_dominate_sink_load + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVLE32_V_M1 $noreg, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVLE32_V_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size) + %vl:gprnox0 = COPY $x1 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vl_doesnt_dominate_cant_sink_load +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: vl_doesnt_dominate_cant_sink_load + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = PseudoVLE32_V_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: PseudoVSE32_V_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */ + ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVLE32_V_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size) + PseudoVSE32_V_M1 $noreg, $noreg, -1, 5 /* e32 */ + %vl:gprnox0 = COPY $x1 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vl_doesnt_dominate_can_sink_vxsat +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: vl_doesnt_dominate_can_sink_vxsat + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit-def dead $vxsat + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */, implicit-def dead $vxsat + %vl:gprnox0 = COPY $x1 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vl_doesnt_dominate_cant_sink_vxsat +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: vl_doesnt_dominate_cant_sink_vxsat + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit-def dead $vxsat + ; CHECK-NEXT: $x2 = COPY $vxsat + ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */, implicit-def dead $vxsat + $x2 = COPY $vxsat + %vl:gprnox0 = COPY $x1 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 5 /* e32 */, 0 + $v8 = COPY %y +... +--- +name: vl_doesnt_dominate_cant_sink_other_user +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: vl_doesnt_dominate_cant_sink_other_user + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, -1, 5 /* e32 */, 0 + %vl:gprnox0 = COPY $x1 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 5 /* e32 */, 0 + $v8 = COPY %z +... +--- +name: vl_doesnt_dominate_can_sink_other_user +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: vl_doesnt_dominate_can_sink_other_user + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %z + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 + %vl:gprnox0 = COPY $x1 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, -1, 5 /* e32 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 5 /* e32 */, 0 + $v8 = COPY %z +... +--- +# Although %vl doesn't dominate all uses of %x, we only need it to dominate the uses of %x in %bb.1 in order to sink it. +name: vl_doesnt_dominate_sink_use_in_other_block +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: vl_doesnt_dominate_sink_use_in_other_block + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BEQ $x1, $x0, %bb.1 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: liveins: $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %vl:gprnox0 = COPY $x2 + ; CHECK-NEXT: %x:vr = PseudoVLE32_V_M1 $noreg, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %z:vr = COPY $noreg + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: %phi:vr = PHI %x, %bb.1, %z, %bb.2 + bb.0: + liveins: $x1 + BEQ $x1, $x0, %bb.1 + PseudoBR %bb.2 + bb.1: + liveins: $x2 + %x:vr = PseudoVLE32_V_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size) + %vl:gprnox0 = COPY $x2 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 5 /* e32 */, 0 + $v8 = COPY %y + PseudoBR %bb.3 + bb.2: + %z:vr = COPY $noreg + PseudoBR %bb.3 + bb.3: + %phi:vr = PHI %x, %bb.1, %z, %bb.2 +... +--- +name: vabd_v +body: | + bb.0: + liveins: $x8 + ; CHECK-LABEL: name: vabd_v + ; CHECK: liveins: $x8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = PseudoVABD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVABD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + $v8 = COPY %y +... +--- +name: vabdu_v +body: | + bb.0: + liveins: $x8 + ; CHECK-LABEL: name: vabdu_v + ; CHECK: liveins: $x8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = PseudoVABD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVABD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + $v8 = COPY %y +... +--- +name: vwabda_vv +body: | + bb.0: + liveins: $x8 + ; CHECK-LABEL: name: vwabda_vv + ; CHECK: liveins: $x8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: early-clobber %x:vr = PseudoVWABDA_VV_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVWABDA_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + $v8 = COPY %y +... +--- +name: vwabdau_vv +body: | + bb.0: + liveins: $x8 + ; CHECK-LABEL: name: vwabdau_vv + ; CHECK: liveins: $x8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: early-clobber %x:vr = PseudoVWABDAU_VV_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v8 = COPY %y + %x:vr = PseudoVWABDAU_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + $v8 = COPY %y +... +name: vl_sink_end_of_bb +body: | + ; CHECK-LABEL: name: vl_sink_end_of_bb + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, 1 + ; CHECK-NEXT: early-clobber %1:vrm4 = PseudoVRGATHER_VI_M4 $noreg, [[COPY]], 0, [[ADDI]] /* vl */, 6 /* e64 */, 1 /* ta, mu */ + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: early-clobber %3:vr = PseudoVMSEQ_VI_M4 %1, 0, [[ADDI]] /* vl */, 6 /* e64 */ + ; CHECK-NEXT: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 [[ADDI]] /* vl */, 0 /* e8 */ + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B16_]] + ; CHECK-NEXT: [[PseudoVFIRST_M_B16_MASK:%[0-9]+]]:gpr = PseudoVFIRST_M_B16_MASK killed %3, killed [[COPY1]], [[ADDI]] /* vl */, 0 /* e8 */ + ; CHECK-NEXT: $x10 = COPY [[PseudoVFIRST_M_B16_MASK]] + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0: + liveins: $v8m4 + + %2:vrm4 = COPY $v8m4 + early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 $noreg, %2, 0, -1 /* vl=VLMAX */, 6 /* e64 */, 1 /* ta, mu */ + %1:gprnox0 = ADDI $x0, 1 + + bb.1: + early-clobber %3:vr = PseudoVMSEQ_VI_M4 %0, 0, -1 /* vl=VLMAX */, 6 /* e64 */ + %4:vr = PseudoVMCLR_M_B16 -1 /* vl=VLMAX */, 0 /* e8 */ + %6:vmv0 = COPY %4 + %5:gpr = PseudoVFIRST_M_B16_MASK killed %3, killed %6, %1 /* vl */, 0 /* e8 */ + $x10 = COPY %5 + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vl-optimizer-subreg-assert.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vl-optimizer-subreg-assert.mir new file mode 100644 index 0000000..aaaf15b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vl-optimizer-subreg-assert.mir @@ -0,0 +1,32 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -o - %s | FileCheck %s +# Check that there is no assert on subregister uses. + +--- +name: vl_optimizer_subreg_assert +tracksRegLiveness: true +body: | + bb.0: + liveins: $v8m2 + + ; CHECK-LABEL: name: vl_optimizer_subreg_assert + ; CHECK: liveins: $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 $noreg, killed [[DEF2]], [[DEF]], [[DEF1]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; CHECK-NEXT: [[PseudoVREDMAXU_VS_M8_E64_:%[0-9]+]]:vr = PseudoVREDMAXU_VS_M8_E64 $noreg, [[PseudoVMERGE_VVM_M8_]], [[PseudoVMERGE_VVM_M8_]].sub_vrm1_0, -1 /* vl=VLMAX */, 6 /* e64 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S killed [[PseudoVREDMAXU_VS_M8_E64_]], 6 /* e64 */ + ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:vrm8nov0 = IMPLICIT_DEF + %1:vmv0 = IMPLICIT_DEF + %2:vrm8nov0 = IMPLICIT_DEF + %3:vrm8nov0 = PseudoVMERGE_VVM_M8 $noreg, killed %2, %0, %1, -1, 6 /* e64 */ + %4:vr = PseudoVREDMAXU_VS_M8_E64 $noreg, %3, %3.sub_vrm1_0, -1, 6 /* e64 */, 1 /* ta, mu */ + %5:gpr = PseudoVMV_X_S killed %4, 6 /* e64 */ + $x10 = COPY %5 + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vlopt-volatile-ld.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vlopt-volatile-ld.mir new file mode 100644 index 0000000..5d86b68 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vlopt-volatile-ld.mir @@ -0,0 +1,13 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s + +--- +name: vleN_v_volatile +body: | + bb.0: + ; CHECK-LABEL: name: vleN_v_volatile + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ :: (volatile load ()) + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 :: (volatile load ()) + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir new file mode 100644 index 0000000..355a50f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir @@ -0,0 +1,271 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole -verify-machineinstrs | FileCheck %s + +--- +name: vle32 +body: | + bb.0: + liveins: $x8, $v0, $v8 + ; CHECK-LABEL: name: vle32 + ; CHECK: liveins: $x8, $v0, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %y:vrnov0 = PseudoVLE32_V_M1_MASK %passthru, $noreg, %mask, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + %avl:gprnox0 = COPY $x8 + %passthru:vrnov0 = COPY $v8 + %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size) + %mask:vmv0 = COPY $v0 + %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %x, %mask, %avl, 5 /* e32 */ +... +--- +name: vle32_no_passthru +body: | + bb.0: + liveins: $x8, $v0, $v8 + ; CHECK-LABEL: name: vle32_no_passthru + ; CHECK: liveins: $x8, $v0, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %false:vrnov0 = COPY $v8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %y:vrnov0 = PseudoVLE32_V_M1_MASK %false, $noreg, %mask, %avl /* vl */, 5 /* e32 */, 1 /* ta, mu */ :: (load unknown-size, align 1) + %avl:gprnox0 = COPY $x8 + %false:vrnov0 = COPY $v8 + %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size) + %mask:vmv0 = COPY $v0 + %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %false, %x, %mask, %avl, 5 /* e32 */ +... +--- +name: vle32_move_past_passthru +body: | + bb.0: + liveins: $x8, $v0, $v8 + ; CHECK-LABEL: name: vle32_move_past_passthru + ; CHECK: liveins: $x8, $v0, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %y:vrnov0 = PseudoVLE32_V_M1_MASK %passthru, $noreg, %mask, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + %avl:gprnox0 = COPY $x8 + %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size) + %passthru:vrnov0 = COPY $v8 + %mask:vmv0 = COPY $v0 + %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %x, %mask, %avl, 5 /* e32 */ +... +--- +name: vnclip_move_past_passthru +body: | + bb.0: + liveins: $x8, $v0, $v8 + ; CHECK-LABEL: name: vnclip_move_past_passthru + ; CHECK: liveins: $x8, $v0, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %y:vrnov0 = PseudoVNCLIPU_WV_MF2_MASK %passthru, $noreg, $noreg, %mask, 0 /* vxrm=rnu */, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit-def $vxsat + %avl:gprnox0 = COPY $x8 + %x:vrnov0 = PseudoVNCLIPU_WV_MF2 $noreg, $noreg, $noreg, 0, -1, 5, 3, implicit-def $vxsat + %passthru:vrnov0 = COPY $v8 + %mask:vmv0 = COPY $v0 + %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %x, %mask, %avl, 5 /* e32 */ +... +--- +name: vnclip_cant_move_past_passthru +body: | + bb.0: + liveins: $x8, $v0, $v8 + ; CHECK-LABEL: name: vnclip_cant_move_past_passthru + ; CHECK: liveins: $x8, $v0, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %x:vrnov0 = PseudoVNCLIPU_WV_MF2 $noreg, $noreg, $noreg, 0 /* vxrm=rnu */, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */, implicit-def $vxsat + ; CHECK-NEXT: %vxsat:gpr = COPY $vxsat + ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %x, %mask, %avl /* vl */, 5 /* e32 */ + %avl:gprnox0 = COPY $x8 + %x:vrnov0 = PseudoVNCLIPU_WV_MF2 $noreg, $noreg, $noreg, 0, -1, 5, 3, implicit-def $vxsat + %vxsat:gpr = COPY $vxsat + %passthru:vrnov0 = COPY $v8 + %mask:vmv0 = COPY $v0 + %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %x, %mask, %avl, 5 /* e32 */ +... +--- +name: commute_vfmadd +body: | + bb.0: + liveins: $x8, $v0, $v8, $v9, $v10 + ; CHECK-LABEL: name: commute_vfmadd + ; CHECK: liveins: $x8, $v0, $v8, $v9, $v10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %x:vr = COPY $v9 + ; CHECK-NEXT: %y:vr = COPY $v10 + ; CHECK-NEXT: %vmerge:vrnov0 = nofpexcept PseudoVFMACC_VV_M1_E32_MASK %passthru, %y, %x, %mask, 7 /* frm=dyn */, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $frm + %avl:gprnox0 = COPY $x8 + %mask:vmv0 = COPY $v0 + %passthru:vrnov0 = COPY $v8 + %x:vr = COPY $v9 + %y:vr = COPY $v10 + %vfmadd:vrnov0 = nofpexcept PseudoVFMADD_VV_M1_E32 %x, %y, %passthru, 7, -1, 5 /* e32 */, 3 /* ta, ma */, implicit $frm + %vmerge:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %vfmadd, %mask, %avl, 5 +... +--- +name: true_copy +body: | + bb.0: + liveins: $x8, $v0, $v8 + ; CHECK-LABEL: name: true_copy + ; CHECK: liveins: $x8, $v0, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %z:vrnov0 = PseudoVLE32_V_M1_MASK %passthru, $noreg, %mask, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + %avl:gprnox0 = COPY $x8 + %passthru:vrnov0 = COPY $v8 + %x:vr = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size) + %mask:vmv0 = COPY $v0 + %y:vrnov0 = COPY %x + %z:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %y, %mask, %avl, 5 /* e32 */ +... +--- +name: copy_is_killed +body: | + bb.0: + liveins: $v0, $v8, $v9 + ; CHECK-LABEL: name: copy_is_killed + ; CHECK: liveins: $v0, $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = COPY $v8 + ; CHECK-NEXT: %y:vr = COPY $v9 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %add0:vr = PseudoVADD_VV_M1 $noreg, %x, %y, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: %add1:vrnov0 = COPY %add:vrnov0 + ; CHECK-NEXT: %merge:vrnov0 = PseudoVOR_VV_M1_MASK %add:vrnov0, %add1, %y, %mask, -1 /* vl=VLMAX */, 5 /* e32 */, 1 /* ta, mu */ + %x:vr = COPY $v8 + %y:vr = COPY $v9 + %mask:vmv0 = COPY $v0 + %add0:vr = PseudoVADD_VV_M1 $noreg, %x:vr, %y:vr, -1, 5, 3 + %add1:vrnov0 = COPY killed %add:vr + %or:vrnov0 = PseudoVOR_VV_M1 $noreg, %add1:vrnov0, %y:vr, -1, 5, 3 + %merge:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %add1:vrnov0, killed %or:vrnov0, killed %mask:vmv0, -1, 5 /* e32 */ + +... +--- +name: copy_multiple_use +body: | + bb.0: + liveins: $x8, $v0, $v8 + ; CHECK-LABEL: name: copy_multiple_use + ; CHECK: liveins: $x8, $v0, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl /* vl */, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %copy:vrnov0 = COPY %x + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: PseudoVSE8_V_M1 %copy, $noreg, %avl /* vl */, 5 /* e32 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %copy, %mask, %avl /* vl */, 5 /* e32 */ + %avl:gprnox0 = COPY $x8 + %passthru:vrnov0 = COPY $v8 + %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size) + %copy:vrnov0 = COPY %x + %mask:vmv0 = COPY $v0 + PseudoVSE8_V_M1 %copy, $noreg, %avl, 5 /* e8 */ + %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %copy, %mask, %avl, 5 /* e32 */ +... +--- +name: true_copy_elimination +body: | + ; CHECK-LABEL: name: true_copy_elimination + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF + ; CHECK-NEXT: early-clobber %5:vrm8nov0 = PseudoVZEXT_VF8_M8_MASK $noreg, $noreg, [[DEF]], 16 /* vl */, 6 /* e64 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY %5 + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.1 + + PseudoBR %bb.1 + + bb.1: + + %102:vrm8 = PseudoVZEXT_VF8_M8 $noreg, $noreg, 16, 6 /* e64 */, 3 /* ta, ma */ + %123:vrm8nov0 = COPY %102 + %a123:vrm8 = COPY %123 + %b123:vrm8nov0 = COPY %a123 + %124:vmv0 = IMPLICIT_DEF + %121:vrm8nov0 = PseudoVMERGE_VVM_M8 $noreg, $noreg, %b123, undef %124, 16, 6 /* e64 */ + %125:vrm8 = COPY %121 + PseudoRET +... +--- +name: increase_vl +body: | + bb.0: + ; CHECK-LABEL: name: increase_vl + ; CHECK: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %merge:vrnov0 = PseudoVADD_VV_M1_MASK %passthru, %x:vr, %y:vr, %mask, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + %passthru:vrnov0 = COPY $v8 + %avl:gprnox0 = COPY $x8 + %mask:vmv0 = COPY $v0 + %add:vrnov0 = PseudoVADD_VV_M1 $noreg, %x:vr, %y:vr, 1, 5 /* e32 */, 0 /* tu, mu */ + %merge:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %add, %mask, %avl, 5 /* e32 */ +... +--- +# Negative test: Shouldn't fold vmerge into the load because we may increase vl. +name: increase_vl_load +body: | + bb.0: + ; CHECK-LABEL: name: increase_vl_load + ; CHECK: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %load:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %merge:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %load, %mask, %avl /* vl */, 5 /* e32 */ + %passthru:vrnov0 = COPY $v8 + %avl:gprnox0 = COPY $x8 + %mask:vmv0 = COPY $v0 + %load:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size) + %merge:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %load, %mask, %avl, 5 /* e32 */ +... +--- +name: sink_past_false +body: | + bb.0: + ; CHECK-LABEL: name: sink_past_false + ; CHECK: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: %z:vrnov0 = PseudoVADD_VV_M1_MASK %y, $noreg, $noreg, %mask, -1 /* vl=VLMAX */, 5 /* e32 */, 1 /* ta, mu */ + %mask:vmv0 = COPY $v0 + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5, 3 + %y:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5, 3 + %z:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %y:vrnov0, %x:vrnov0, %mask, -1, 5 +... +--- +name: sink_past_avl +body: | + bb.0: + ; CHECK-LABEL: name: sink_past_avl + ; CHECK: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %avl:gprnox0 = ADDI $noreg, 1 + ; CHECK-NEXT: %z:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %mask, %avl /* vl */, 5 /* e32 */, 1 /* ta, mu */ + %mask:vmv0 = COPY $v0 + %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5, 3 + %avl:gprnox0 = ADDI $noreg, 1 + %z:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x:vrnov0, %mask, %avl, 5 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir new file mode 100644 index 0000000..aba2e48 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir @@ -0,0 +1,334 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -verify-machineinstrs -mtriple riscv64 -run-pass=postrapseudos %s -o - | FileCheck %s +# RUN: llc -verify-machineinstrs -mtriple riscv64 -passes=post-ra-pseudos %s -o - | FileCheck %s + +... +--- +name: copy_different_lmul +tracksRegLiveness: true +body: | + bb.0: + liveins: $x14, $x16 + ; CHECK-LABEL: name: copy_different_lmul + ; CHECK: liveins: $x14, $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m2 = VMV2R_V $v28m2, implicit $vtype, implicit $v28m2 + $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype + $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype + $v12m2 = COPY $v28m2 +... +--- +name: copy_convert_to_vmv_v_v +tracksRegLiveness: true +body: | + bb.0: + liveins: $x14, $x16 + ; CHECK-LABEL: name: copy_convert_to_vmv_v_v + ; CHECK: liveins: $x14, $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m4 = PseudoVMV_V_V_M4 undef $v12m4, $v28m4, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit $v28m4 + $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype + $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype + $v12m4 = COPY $v28m4 +... +--- +name: copy_convert_to_vmv_v_i +tracksRegLiveness: true +body: | + bb.0: + liveins: $x14 + ; CHECK-LABEL: name: copy_convert_to_vmv_v_i + ; CHECK: liveins: $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m4 = PseudoVMV_V_I_M4 undef $v12m4, 0, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit $v28m4 + $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype + $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg, 5, 0, implicit $vl, implicit $vtype + $v12m4 = COPY $v28m4 +... +--- +name: copy_from_whole_load_store +tracksRegLiveness: true +body: | + bb.0: + liveins: $x14, $x16 + ; CHECK-LABEL: name: copy_from_whole_load_store + ; CHECK: liveins: $x14, $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v28m4 = VL4RE32_V $x16 + ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype, implicit $v28m4 + $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype + $v28m4 = VL4RE32_V $x16 + $v12m4 = COPY $v28m4 +... +--- +name: copy_with_vleff +tracksRegLiveness: true +body: | + bb.0: + liveins: $x14, $x16 + ; CHECK-LABEL: name: copy_with_vleff + ; CHECK: liveins: $x14, $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v4m4, $x0 = PseudoVLE32FF_V_M4 undef $v4m4, $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit-def $vl + ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype, implicit $v28m4 + $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype + $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg, 5, 0, implicit $vl, implicit $vtype + $v4m4,$x0 = PseudoVLE32FF_V_M4 undef $v4m4, $x16, $noreg, 5, 0, implicit-def $vl + $v12m4 = COPY $v28m4 +... +--- +name: copy_with_vsetvl_x0_x0_1 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x14, $x16, $x17, $x18 + ; CHECK-LABEL: name: copy_with_vsetvl_x0_x0_1 + ; CHECK: liveins: $x14, $x16, $x17, $x18 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x17, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype, implicit $v28m4 + $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype + $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype + $x15 = PseudoVSETVLI $x17, 73, implicit-def $vl, implicit-def $vtype + $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4, 0, implicit $vl, implicit $vtype + $x0 = PseudoVSETVLIX0X0 $x0, 82, implicit-def $vl, implicit-def $vtype + $v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg, 5, 0, implicit $vl, implicit $vtype + $v12m4 = COPY $v28m4 +... +--- +name: copy_with_vsetvl_x0_x0_2 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x14, $x16, $x17, $x18 + ; CHECK-LABEL: name: copy_with_vsetvl_x0_x0_2 + ; CHECK: liveins: $x14, $x16, $x17, $x18 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m4 = PseudoVMV_V_V_M4 undef $v12m4, $v28m4, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit $v28m4 + $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype + $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype + $x0 = PseudoVSETVLIX0X0 $x0, 73, implicit-def $vl, implicit-def $vtype + $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4, 0, implicit $vl, implicit $vtype + $x0 = PseudoVSETVLIX0X0 $x0, 82, implicit-def $vl, implicit-def $vtype + $v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg, 5, 0, implicit $vl, implicit $vtype + $v12m4 = COPY $v28m4 +... +--- +name: copy_with_vsetvl_x0_x0_3 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x14, $x16, $x17, $x18 + ; CHECK-LABEL: name: copy_with_vsetvl_x0_x0_3 + ; CHECK: liveins: $x14, $x16, $x17, $x18 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype, implicit $v28m4 + $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype + $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype + $x0 = PseudoVSETVLIX0X0 $x0, 73, implicit-def $vl, implicit-def $vtype + $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4, 0, implicit $vl, implicit $vtype + $v12m4 = COPY $v28m4 +... +--- +name: copy_subregister +tracksRegLiveness: true +body: | + bb.0: + liveins: $x16, $x17 + ; CHECK-LABEL: name: copy_subregister + ; CHECK: liveins: $x16, $x17 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETIVLI 4, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v26m2 = PseudoVLE16_V_M2 undef $v26m2, killed $x16, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8m2 = PseudoVLE16_V_M2 undef $v8m2, killed $x17, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber $v28m4 = PseudoVWADD_VV_M2 undef $v28m4, $v26m2, $v8m2, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m2 = VMV2R_V $v28m2, implicit $vtype, implicit $v28m2 + $x15 = PseudoVSETIVLI 4, 73, implicit-def $vl, implicit-def $vtype + $v26m2 = PseudoVLE16_V_M2 undef $v26m2, killed $x16, $noreg, 4, 0, implicit $vl, implicit $vtype + $v8m2 = PseudoVLE16_V_M2 undef $v8m2, killed $x17, $noreg, 4, 0, implicit $vl, implicit $vtype + + $v28m4 = PseudoVWADD_VV_M2 undef $v28m4, $v26m2, $v8m2, $noreg, 4, 0, implicit $vl, implicit $vtype + $v12m2 = COPY $v28m2 +... +--- +name: copy_with_different_vlmax +tracksRegLiveness: true +body: | + bb.0: + liveins: $x14, $x16 + ; CHECK-LABEL: name: copy_with_different_vlmax + ; CHECK: liveins: $x14, $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 74 /* e16, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype, implicit $v28m4 + $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype + $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype + $x0 = PseudoVSETVLIX0X0 $x0, 74, implicit-def $vl, implicit-def $vtype + $v12m4 = COPY $v28m4 +... +--- +name: copy_with_widening_reduction +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $v8, $v26, $v27 + ; CHECK-LABEL: name: copy_with_widening_reduction + ; CHECK: liveins: $x10, $v8, $v26, $v27 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = PseudoVSETIVLI 1, 64 /* e8, m1, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v8 = PseudoVWREDSUM_VS_M1_E8 killed renamable $v8, killed renamable $v26, killed renamable $v27, 1 /* vl */, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v26 = VMV1R_V killed $v8, implicit $vtype, implicit $v8 + ; CHECK-NEXT: $x10 = PseudoVSETVLI killed renamable $x10, 75 /* e16, m8, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v8m8 = VL8RE8_V killed $x10 + $x11 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype + $v8 = PseudoVWREDSUM_VS_M1_E8 killed renamable $v8, killed renamable $v26, killed renamable $v27, 1, 3, 1, implicit $vl, implicit $vtype + $v26 = COPY killed renamable $v8 + $x10 = PseudoVSETVLI killed renamable $x10, 75, implicit-def $vl, implicit-def $vtype + $v8m8 = VL8RE8_V killed $x10 +... +--- +name: copy_zvlsseg_reg +tracksRegLiveness: true +body: | + bb.0: + liveins: $x14, $x16 + ; CHECK-LABEL: name: copy_zvlsseg_reg + ; CHECK: liveins: $x14, $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v10 = VMV1R_V $v8, implicit $vtype, implicit $v8 + $x15 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype + $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype + $v10 = COPY $v8 +... +--- +name: copy_zvlsseg_reg_2 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x14, $x16 + ; CHECK-LABEL: name: copy_zvlsseg_reg_2 + ; CHECK: liveins: $x14, $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v10m2 = VMV2R_V $v8m2, implicit $vtype, implicit $v8_v9 + $x15 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype + $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype + $v10_v11 = COPY $v8_v9 +... +--- +name: copy_fractional_lmul +tracksRegLiveness: true +body: | + bb.0: + liveins: $x14, $x16 + ; CHECK-LABEL: name: copy_fractional_lmul + ; CHECK: liveins: $x14, $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 87 /* e32, mf2, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v28 = PseudoVLE32_V_MF2 undef $v28, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12 = VMV1R_V $v28, implicit $vtype, implicit $v28 + $x15 = PseudoVSETVLI $x14, 87, implicit-def $vl, implicit-def $vtype + $v28 = PseudoVLE32_V_MF2 undef $v28, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype + $v12 = COPY $v28 +... +--- +name: copy_implicit_def +tracksRegLiveness: true +body: | + bb.0: + liveins: $x12, $x14, $x16 + ; CHECK-LABEL: name: copy_implicit_def + ; CHECK: liveins: $x12, $x14, $x16 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x0 = PseudoVSETVLI $x14, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v8_v9_v10_v11_v12_v13_v14_v15 = PseudoVLSEG8E32_V_M1 undef $v8_v9_v10_v11_v12_v13_v14_v15, killed $x12, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $x0 = PseudoVSETIVLI 10, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v15 = PseudoVLE32_V_M1 undef $v15, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit killed $v8_v9_v10_v11_v12_v13_v14_v15, implicit-def $v8_v9_v10_v11_v12_v13_v14_v15 + ; CHECK-NEXT: $v24m8 = VMV8R_V killed $v8m8, implicit $vtype, implicit $v8_v9_v10_v11_v12_v13_v14_v15 + $x0 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype + $v8_v9_v10_v11_v12_v13_v14_v15 = PseudoVLSEG8E32_V_M1 undef $v8_v9_v10_v11_v12_v13_v14_v15, killed $x12, $noreg, 5, 0, implicit $vl, implicit $vtype + $x0 = PseudoVSETIVLI 10, 80, implicit-def $vl, implicit-def $vtype + $v15 = PseudoVLE32_V_M1 undef $v15, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype, implicit killed $v8_v9_v10_v11_v12_v13_v14_v15, implicit-def $v8_v9_v10_v11_v12_v13_v14_v15 + $v24_v25_v26_v27_v28_v29_v30_v31 = COPY killed $v8_v9_v10_v11_v12_v13_v14_v15 +... +--- +name: copy_sifive_custom_macc +tracksRegLiveness: true +body: | + bb.0: + liveins: $x2, $x10, $v8, $v13, $v4m4, $v16m4 + ; CHECK-LABEL: name: copy_sifive_custom_macc + ; CHECK: liveins: $x2, $x10, $v8, $v13, $v4m4, $v16m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x0 = PseudoVSETVLI $x10, 66 /* e8, m4, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: early-clobber $v4m4 = PseudoSF_VQMACCUS_2x8x2_M4 renamable $v4m4, killed renamable $v13, killed renamable $v16m4, $noreg /* vl */, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v16m4 = PseudoVMV_V_V_M4 undef $v16m4, $v4m4, $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit $v4m4 + $x0 = PseudoVSETVLI $x10, 66, implicit-def $vl, implicit-def $vtype + early-clobber $v4m4 = PseudoSF_VQMACCUS_2x8x2_M4 renamable $v4m4, killed renamable $v13, killed renamable $v16m4, $noreg, 3, 1, implicit $vl, implicit $vtype + $v16m4 = COPY renamable $v4m4 +... +--- +name: copy_sifive_custom_macc1 +tracksRegLiveness: true +body: | + bb.0: + liveins: $x2, $x10, $v8, $v13, $v4m4, $v16m2 + ; CHECK-LABEL: name: copy_sifive_custom_macc1 + ; CHECK: liveins: $x2, $x10, $v8, $v13, $v4m4, $v16m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x0 = PseudoVSETVLI $x10, 65 /* e8, m2, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: early-clobber $v4m4 = PseudoSF_VQMACCUS_4x8x4_M2 renamable $v4m4, killed renamable $v13, killed renamable $v16m2, $noreg /* vl */, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v16m4 = VMV4R_V $v4m4, implicit $vtype, implicit $v4m4 + $x0 = PseudoVSETVLI $x10, 65, implicit-def $vl, implicit-def $vtype + early-clobber $v4m4 = PseudoSF_VQMACCUS_4x8x4_M2 renamable $v4m4, killed renamable $v13, killed renamable $v16m2, $noreg, 3, 1, implicit $vl, implicit $vtype + $v16m4 = COPY renamable $v4m4 +... +--- +name: copy_narrow_copies_in_between +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $v8, $v9 + ; CHECK-LABEL: name: copy_narrow_copies_in_between + ; CHECK: liveins: $x10, $x11, $v8, $v9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x0 = PseudoVSETVLI $x10, 201 /* e16, m2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v10m2 = PseudoVLE16_V_M2 undef $v10m2, killed $x11, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v10 = VMV1R_V $v8, implicit $vtype, implicit $v8 + ; CHECK-NEXT: $v11 = VMV1R_V $v9, implicit $vtype, implicit $v9 + ; CHECK-NEXT: $v12m2 = VMV2R_V $v10m2, implicit $vtype, implicit $v10m2 + $x0 = PseudoVSETVLI $x10, 201, implicit-def $vl, implicit-def $vtype + $v10m2 = PseudoVLE16_V_M2 undef $v10m2, killed $x11, $noreg, 4, 0, implicit $vl, implicit $vtype + $v10 = COPY $v8 + $v11 = COPY $v9 + $v12m2 = COPY $v10m2 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir new file mode 100644 index 0000000..50c87ed --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir @@ -0,0 +1,190 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \ +# RUN: -verify-machineinstrs | FileCheck %s + +--- +name: move_src +body: | + bb.0: + liveins: $v8 + ; CHECK-LABEL: name: move_src + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %passthru:vr = COPY $v8 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:gpr = ADDI $x0, 1 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ + %passthru:vr = COPY $v8 + %y:gpr = ADDI $x0, 1 + %z:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 0 /* tu, mu */ +... +--- +name: tail_agnostic +body: | + bb.0: + liveins: $v8 + ; CHECK-LABEL: name: tail_agnostic + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %passthru:vr = COPY $v8 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4 /* vl */, 5 /* e32 */, 1 /* ta, mu */ + %passthru:vr = COPY $v8 + %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ + %y:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 1 /* ta, mu */ +... +--- +name: tail_agnostic_larger_vl +body: | + bb.0: + liveins: $v8 + ; CHECK-LABEL: name: tail_agnostic_larger_vl + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %passthru:vr = COPY $v8 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + %passthru:vr = COPY $v8 + %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ + %y:vr = PseudoVMV_V_V_M1 %passthru, %x, 5, 5 /* e32 */, 1 /* ta, mu */ +... +--- +name: undef_passthru_src_undef_passthru +body: | + bb.0: + liveins: $v8 + ; CHECK-LABEL: name: undef_passthru_src_undef_passthru + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %passthru:vr = COPY $v8 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 4 /* vl */, 5 /* e32 */, 1 /* ta, mu */ + %passthru:vr = COPY $v8 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ + %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 0 /* tu, mu */ +... +--- +name: undef_passthru +body: | + bb.0: + liveins: $v8 + ; CHECK-LABEL: name: undef_passthru + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %passthru:vr = COPY $v8 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4 /* vl */, 5 /* e32 */, 1 /* ta, mu */ + %passthru:vr = COPY $v8 + %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ + %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 1 /* ta, mu */ +... +--- +# Shouldn't be folded because the EEWs don't match +name: different_eew +body: | + bb.0: + liveins: $v8 + ; CHECK-LABEL: name: different_eew + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %passthru:vr = COPY $v8 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 %passthru, $noreg, $noreg, 4 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_MF8 %passthru, %x, 4 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + %passthru:vr = COPY $v8 + %x:vr = PseudoVADD_VV_MF4 %passthru, $noreg, $noreg, 4, 4 /* e16 */, 0 /* tu, mu */ + %y:vr = PseudoVMV_V_V_MF8 %passthru, %x, 4, 3 /* e8 */, 0 /* tu, mu */ +... +--- +name: kill_flag +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: name: kill_flag + ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY [[PseudoVADD_VV_M1_]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY [[PseudoVADD_VV_M1_]] + %0:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ + %1:vr = PseudoVMV_V_V_M1 $noreg, %0, -1, 4 /* e16 */, 0 /* tu, mu */ + %2:vr = COPY killed %1 + %3:vr = COPY %0 +... +--- +name: diff_regclass +body: | + bb.0.entry: + liveins: $v8 + ; CHECK-LABEL: name: diff_regclass + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0 /* vl */, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8 + ; CHECK-NEXT: [[PseudoVADD_VV_M1_MASK:%[0-9]+]]:vrnov0 = PseudoVADD_VV_M1_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + %0:vr = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 0 /* tu, mu */ + %1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */ + %2:vmv0 = COPY $v8 + %3:vrnov0 = PseudoVADD_VV_M1_MASK %1, $noreg, $noreg, %2, 0, 5 /* e32 */, 0 /* tu, mu */ +... +--- +name: diff_regclass_passthru +body: | + bb.0.entry: + liveins: $v8 + ; CHECK-LABEL: name: diff_regclass_passthru + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0 /* vl */, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8 + ; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4) + %2:vr = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 0 /* tu, mu */ + %3:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %2, 0, 5 /* e32 */, 0 /* tu, mu */ + %7:vmv0 = COPY $v8 + %6:vrnov0 = PseudoVLSE32_V_MF2_MASK %3, $noreg, $noreg, %7, 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4) +... +--- +name: move_vleff +body: | + bb.0: + liveins: $v8 + ; CHECK-LABEL: name: move_vleff + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %passthru:vr = COPY $v8 + ; CHECK-NEXT: %x:vr, %vl:gpr = PseudoVLE32FF_V_M1 %passthru, $noreg, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %y:gpr = ADDI $x0, 1 + %x:vr, %vl:gpr = PseudoVLE32FF_V_M1 $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size) + %passthru:vr = COPY $v8 + %y:gpr = ADDI $x0, 1 + %z:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 0 /* tu, mu */ +... +--- +name: vmerge_vvm +body: | + bb.0: + liveins: $v8, $v0 + ; CHECK-LABEL: name: vmerge_vvm + ; CHECK: liveins: $v8, $v0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %x:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, $noreg, %mask, 4 /* vl */, 5 /* e32 */ + %passthru:vrnov0 = COPY $v8 + %mask:vmv0 = COPY $v0 + %x:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %passthru, $noreg, %mask, 4, 5 /* e32 */ + %z:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 0 /* tu, mu */ +... +--- +name: commute_vfmadd +body: | + bb.0: + liveins: $x8, $v0, $v8, $v9, $v10 + ; CHECK-LABEL: name: commute_vfmadd + ; CHECK: liveins: $x8, $v0, $v8, $v9, $v10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %x:vr = COPY $v9 + ; CHECK-NEXT: %y:vr = COPY $v10 + ; CHECK-NEXT: %vfmadd:vrnov0 = nofpexcept PseudoVFMACC_VV_M1_E32 %passthru, %y, %x, 7 /* frm=dyn */, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $frm + %avl:gprnox0 = COPY $x8 + %passthru:vrnov0 = COPY $v8 + %x:vr = COPY $v9 + %y:vr = COPY $v10 + %vfmadd:vrnov0 = nofpexcept PseudoVFMADD_VV_M1_E32 %x, %y, %passthru, 7, %avl, 5 /* e32 */, 3 /* ta, ma */, implicit $frm + %vmerge:vrnov0 = PseudoVMV_V_V_M1 %passthru, %vfmadd, %avl, 5 /* e32 */, 0 /* tu, mu */ +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.mir new file mode 100644 index 0000000..5125d07 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.mir @@ -0,0 +1,22 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vmv0-elimination -verify-machineinstrs | FileCheck %s + +# If we peek through a COPY to vmv0, we may leave it dead. Make sure we delete +# it so the register allocator doesn't try to allocate it, which can lead to a +# regalloc error. +# https://github.com/llvm/llvm-project/pull/126850#issuecomment-2685166388 + +--- +name: dead_copy +body: | + bb.0: + liveins: $v8 + ; CHECK-LABEL: name: dead_copy + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:vr = COPY $v8 + ; CHECK-NEXT: $v0 = COPY %x + ; CHECK-NEXT: PseudoVSE8_V_M1_MASK $noreg, $noreg, $v0, -1 /* vl=VLMAX */, 3 /* e8 */ + %x:vr = COPY $v8 + %y:vmv0 = COPY %x:vr + PseudoVSE8_V_M1_MASK $noreg, $noreg, %y:vmv0, -1, 3 diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-coalesce.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-coalesce.mir new file mode 100644 index 0000000..498c44f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-coalesce.mir @@ -0,0 +1,69 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=liveintervals,riscv-insert-vsetvli %s -o - | FileCheck %s + +--- +name: coalesce +tracksRegLiveness: true +noPhis: true +body: | + ; CHECK-LABEL: name: coalesce + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gprnox0 = IMPLICIT_DEF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v10m2 = PseudoVMV_V_I_M2 undef renamable $v10m2, 0, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.2(0x7c000000) + ; CHECK-NEXT: liveins: $v10m2, $v12m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BEQ undef %2:gpr, $x0, %bb.2 + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.4(0x04000000) + ; CHECK-NEXT: liveins: $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x0 = PseudoVSETVLI [[DEF]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v10 = PseudoVMV_S_X undef renamable $v10, undef %2:gpr, $noreg /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead renamable $v8 = PseudoVREDSUM_VS_M2_E32 undef renamable $v8, killed undef renamable $v8m2, killed undef renamable $v10, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: BNE undef %3:gpr, $x0, %bb.1 + ; CHECK-NEXT: PseudoBR %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.1(0x80000000) + + %78:gprnox0 = IMPLICIT_DEF + + bb.1: + successors: %bb.2(0x80000000) + + %46:gprnox0 = PseudoVSETVLI %78, 199 /* e8, mf2, ta, ma */, implicit-def dead $vl, implicit-def dead $vtype + renamable $v10m2 = PseudoVMV_V_I_M2 undef renamable $v10m2, 0, -1, 5 /* e32 */, 0 /* tu, mu */ + + bb.2: + successors: %bb.3(0x04000000), %bb.2(0x7c000000) + liveins: $v10m2, $v12m2 + + BEQ undef %54:gpr, $x0, %bb.2 + PseudoBR %bb.3 + + bb.3: + successors: %bb.1(0x7c000000), %bb.4(0x04000000) + liveins: $v8m2 + + renamable $v10 = PseudoVMV_S_X undef renamable $v10, undef %54:gpr, %46, 5 /* e32 */ + dead renamable $v8 = PseudoVREDSUM_VS_M2_E32 undef renamable $v8, killed undef renamable $v8m2, killed undef renamable $v10, %46, 5 /* e32 */, 0 /* tu, mu */ + BNE undef %29:gpr, $x0, %bb.1 + PseudoBR %bb.4 + + bb.4: + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir new file mode 100644 index 0000000..84182cc --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir @@ -0,0 +1,1109 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc %s -o - -mtriple=riscv64 -mattr=v -verify-machineinstrs \ +# RUN: -run-pass=phi-node-elimination,register-coalescer,riscv-insert-vsetvli | FileCheck %s + +--- | + source_filename = "vsetvli-insert.ll" + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" + target triple = "riscv64" + + define @load_add_or_sub(i8 zeroext %cond, ptr %0, %1, i64 %2) #0 { + entry: + %a = call @llvm.riscv.vle.nxv1i64.i64( undef, ptr %0, i64 %2) + %tobool = icmp eq i8 %cond, 0 + br i1 %tobool, label %if.else, label %if.then + + if.then: ; preds = %entry + %b = call @llvm.riscv.vadd.nxv1i64.nxv1i64.i64( undef, %a, %1, i64 %2) + br label %if.end + + if.else: ; preds = %entry + %c = call @llvm.riscv.vsub.nxv1i64.nxv1i64.i64( undef, %a, %1, i64 %2) + br label %if.end + + if.end: ; preds = %if.else, %if.then + %d = phi [ %b, %if.then ], [ %c, %if.else ] + ret %d + } + + define void @load_zext_or_sext(i8 zeroext %cond, ptr %0, ptr %1, i64 %2) #0 { + entry: + %a = call @llvm.riscv.vle.nxv1i32.i64( undef, ptr %0, i64 %2) + %tobool = icmp eq i8 %cond, 0 + br i1 %tobool, label %if.else, label %if.then + + if.then: ; preds = %entry + %b = call @llvm.riscv.vzext.nxv1i64.nxv1i32.i64( undef, %a, i64 %2) + br label %if.end + + if.else: ; preds = %entry + %c = call @llvm.riscv.vsext.nxv1i64.nxv1i32.i64( undef, %a, i64 %2) + br label %if.end + + if.end: ; preds = %if.else, %if.then + %d = phi [ %b, %if.then ], [ %c, %if.else ] + call void @llvm.riscv.vse.nxv1i64.i64( %d, ptr %1, i64 %2) + ret void + } + + define i64 @vmv_x_s(i8 zeroext %cond, %0, %1, i64 %2) #0 { + entry: + %tobool = icmp eq i8 %cond, 0 + br i1 %tobool, label %if.else, label %if.then + + if.then: ; preds = %entry + %a = call @llvm.riscv.vadd.nxv1i64.nxv1i64.i64( undef, %0, %1, i64 %2) + br label %if.end + + if.else: ; preds = %entry + %b = call @llvm.riscv.vsub.nxv1i64.nxv1i64.i64( undef, %1, %1, i64 %2) + br label %if.end + + if.end: ; preds = %if.else, %if.then + %c = phi [ %a, %if.then ], [ %b, %if.else ] + %d = call i64 @llvm.riscv.vmv.x.s.nxv1i64( %c) + ret i64 %d + } + + define @vsetvli_add_or_sub(i8 zeroext %cond, %0, %1, i64 %avl) #0 { + entry: + %vl = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 3, i64 0) + %tobool = icmp eq i8 %cond, 0 + br i1 %tobool, label %if.else, label %if.then + + if.then: ; preds = %entry + %b = call @llvm.riscv.vadd.nxv1i64.nxv1i64.i64( undef, %0, %1, i64 %vl) + br label %if.end + + if.else: ; preds = %entry + %c = call @llvm.riscv.vsub.nxv1i64.nxv1i64.i64( undef, %0, %1, i64 %vl) + br label %if.end + + if.end: ; preds = %if.else, %if.then + %d = phi [ %b, %if.then ], [ %c, %if.else ] + ret %d + } + + define void @vsetvli_vcpop() { + ret void + } + + define void @vsetvli_loop_store() { + ret void + } + + define void @vsetvli_loop_store2() { + ret void + } + + define void @redusum_loop(ptr nocapture noundef readonly %a, i32 noundef signext %n, ptr nocapture noundef writeonly %res) #0 { + entry: + br label %vector.body + + vector.body: ; preds = %vector.body, %entry + %lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %a, %entry ] + %lsr.iv = phi i64 [ %lsr.iv.next, %vector.body ], [ 2048, %entry ] + %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %0, %vector.body ] + %lsr.iv12 = bitcast ptr %lsr.iv1 to ptr + %wide.load = load <4 x i32>, ptr %lsr.iv12, align 4 + %0 = add <4 x i32> %wide.load, %vec.phi + %lsr.iv.next = add nsw i64 %lsr.iv, -4 + %scevgep = getelementptr i32, ptr %lsr.iv1, i64 4 + %1 = icmp eq i64 %lsr.iv.next, 0 + br i1 %1, label %middle.block, label %vector.body + + middle.block: ; preds = %vector.body + %2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %0) + store i32 %2, ptr %res, align 4 + ret void + } + + define void @vsetvli_vluxei64_regression() { + ret void + } + + define void @if_in_loop() { + ret void + } + + define void @pre_undemanded_vl() { + ret void + } + + define void @clobberred_forwarded_avl() { + ret void + } + + define void @clobberred_forwarded_phi_avl() { + ret void + } + + define void @avl_is_last_instr() { + ret void + } + + attributes #0 = { "target-features"="+v" } + +... +--- +name: load_add_or_sub +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vr } + - { id: 1, class: vr } + - { id: 2, class: vr } + - { id: 3, class: vr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } + - { id: 6, class: vr } + - { id: 7, class: gprnox0 } + - { id: 8, class: gpr } +liveins: + - { reg: '$x10', virtual-reg: '%4' } + - { reg: '$x11', virtual-reg: '%5' } + - { reg: '$v8', virtual-reg: '%6' } + - { reg: '$x12', virtual-reg: '%7' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + ; CHECK-LABEL: name: load_add_or_sub + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $x10, $x11, $v8, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.if.then: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.if.else: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.if.end: + ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8 + bb.0.entry: + successors: %bb.2(0x30000000), %bb.1(0x50000000) + liveins: $x10, $x11, $v8, $x12 + + %7:gprnox0 = COPY $x12 + %6:vr = COPY $v8 + %5:gpr = COPY $x11 + %4:gpr = COPY $x10 + %0:vr = PseudoVLE64_V_M1 undef $noreg, %5, %7, 6, 0 + %8:gpr = COPY $x0 + BEQ %4, %8, %bb.2 + PseudoBR %bb.1 + + bb.1.if.then: + %1:vr = PseudoVADD_VV_M1 undef $noreg, %0, %6, %7, 6, 0 + PseudoBR %bb.3 + + bb.2.if.else: + %2:vr = PseudoVSUB_VV_M1 undef $noreg, %0, %6, %7, 6, 0 + + bb.3.if.end: + %3:vr = PHI %1, %bb.1, %2, %bb.2 + $v8 = COPY %3 + PseudoRET implicit $v8 + +... +--- +name: load_zext_or_sext +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vr } + - { id: 1, class: vr } + - { id: 2, class: vr } + - { id: 3, class: vr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } + - { id: 6, class: gpr } + - { id: 7, class: gprnox0 } + - { id: 8, class: gpr } +liveins: + - { reg: '$x10', virtual-reg: '%4' } + - { reg: '$x11', virtual-reg: '%5' } + - { reg: '$x12', virtual-reg: '%6' } + - { reg: '$x13', virtual-reg: '%7' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + ; CHECK-LABEL: name: load_zext_or_sext + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x13 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 undef $noreg, [[COPY2]], $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.if.then: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: early-clobber %9:vr = PseudoVZEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.if.else: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: early-clobber %9:vr = PseudoVSEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.if.end: + ; CHECK-NEXT: PseudoVSE64_V_M1 %9, [[COPY1]], $noreg /* vl */, 6 /* e64 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + bb.0.entry: + successors: %bb.2(0x30000000), %bb.1(0x50000000) + liveins: $x10, $x11, $x12, $x13 + + %7:gprnox0 = COPY $x13 + %6:gpr = COPY $x12 + %5:gpr = COPY $x11 + %4:gpr = COPY $x10 + %0:vr = PseudoVLE32_V_MF2 undef $noreg, %5, %7, 5, 0 + %8:gpr = COPY $x0 + BEQ %4, %8, %bb.2 + PseudoBR %bb.1 + + bb.1.if.then: + early-clobber %1:vr = PseudoVZEXT_VF2_M1 undef $noreg, %0, %7, 6, 0 + PseudoBR %bb.3 + + bb.2.if.else: + early-clobber %2:vr = PseudoVSEXT_VF2_M1 undef $noreg, %0, %7, 6, 0 + + bb.3.if.end: + %3:vr = PHI %1, %bb.1, %2, %bb.2 + PseudoVSE64_V_M1 %3, %6, %7, 6 + PseudoRET + +... +--- +name: vmv_x_s +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vr } + - { id: 1, class: vr } + - { id: 2, class: vr } + - { id: 3, class: gpr } + - { id: 4, class: vr } + - { id: 5, class: vr } + - { id: 6, class: gprnox0 } + - { id: 7, class: gpr } + - { id: 8, class: gpr } +liveins: + - { reg: '$x10', virtual-reg: '%3' } + - { reg: '$v8', virtual-reg: '%4' } + - { reg: '$v9', virtual-reg: '%5' } + - { reg: '$x11', virtual-reg: '%6' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + ; CHECK-LABEL: name: vmv_x_s + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $x10, $v8, $v9, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.if.then: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.if.else: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[COPY1]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.if.end: + ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S [[PseudoVADD_VV_M1_]], 6 /* e64 */, implicit $vtype + ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + bb.0.entry: + successors: %bb.2(0x30000000), %bb.1(0x50000000) + liveins: $x10, $v8, $v9, $x11 + + %6:gprnox0 = COPY $x11 + %5:vr = COPY $v9 + %4:vr = COPY $v8 + %3:gpr = COPY $x10 + %7:gpr = COPY $x0 + BEQ %3, %7, %bb.2 + PseudoBR %bb.1 + + bb.1.if.then: + %0:vr = PseudoVADD_VV_M1 undef $noreg, %4, %5, %6, 6, 0 + PseudoBR %bb.3 + + bb.2.if.else: + %1:vr = PseudoVSUB_VV_M1 undef $noreg, %5, %5, %6, 6, 0 + + bb.3.if.end: + %2:vr = PHI %0, %bb.1, %1, %bb.2 + %8:gpr = PseudoVMV_X_S %2, 6 + $x10 = COPY %8 + PseudoRET implicit $x10 + +... +--- +name: vsetvli_add_or_sub +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gprnox0 } + - { id: 1, class: vr } + - { id: 2, class: vr } + - { id: 3, class: vr } + - { id: 4, class: gpr } + - { id: 5, class: vr } + - { id: 6, class: vr } + - { id: 7, class: gprnox0 } + - { id: 8, class: gpr } +liveins: + - { reg: '$x10', virtual-reg: '%4' } + - { reg: '$v8', virtual-reg: '%5' } + - { reg: '$v9', virtual-reg: '%6' } + - { reg: '$x11', virtual-reg: '%7' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + ; CHECK-LABEL: name: vsetvli_add_or_sub + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $x10, $v8, $v9, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.if.then: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.if.else: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.if.end: + ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8 + bb.0.entry: + successors: %bb.2(0x30000000), %bb.1(0x50000000) + liveins: $x10, $v8, $v9, $x11 + + %7:gprnox0 = COPY $x11 + %6:vr = COPY $v9 + %5:vr = COPY $v8 + %4:gpr = COPY $x10 + %0:gprnox0 = PseudoVSETVLI %7, 88, implicit-def dead $vl, implicit-def dead $vtype + %8:gpr = COPY $x0 + BEQ %4, %8, %bb.2 + PseudoBR %bb.1 + + bb.1.if.then: + %1:vr = PseudoVADD_VV_M1 undef $noreg, %5, %6, %0, 6, 0 + PseudoBR %bb.3 + + bb.2.if.else: + %2:vr = PseudoVSUB_VV_M1 undef $noreg, %5, %6, %0, 6, 0 + + bb.3.if.end: + %3:vr = PHI %1, %bb.1, %2, %bb.2 + $v8 = COPY %3 + PseudoRET implicit $v8 + +... +--- +name: vsetvli_vcpop +tracksRegLiveness: true +registers: + - { id: 0, class: gpr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: gpr, preferred-register: '' } + - { id: 3, class: vr, preferred-register: '' } + - { id: 4, class: vrnov0, preferred-register: '' } + - { id: 5, class: vmv0, preferred-register: '' } + - { id: 6, class: vrnov0, preferred-register: '' } + - { id: 7, class: gpr, preferred-register: '' } + - { id: 8, class: gpr, preferred-register: '' } + - { id: 9, class: gpr, preferred-register: '' } + - { id: 10, class: gpr, preferred-register: '' } + - { id: 11, class: vr, preferred-register: '' } +body: | + ; CHECK-LABEL: name: vsetvli_vcpop + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 undef $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 undef $noreg, 0, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PseudoVMSEQ_VI_MF2_:%[0-9]+]]:vmv0 = PseudoVMSEQ_VI_MF2 [[PseudoVID_V_MF2_]], 0, -1 /* vl=VLMAX */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0 = COPY [[PseudoVMSEQ_VI_MF2_]], implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 23 /* e32, mf2, tu, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: [[PseudoVLE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[COPY]], $v0, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSEQ_VI_MF2_]], -1 /* vl=VLMAX */, 0 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF + ; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B64_]], $x0, %bb.3 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = LWU [[COPY1]], 0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: [[PseudoVADD_VX_MF2_:%[0-9]+]]:vr = nsw PseudoVADD_VX_MF2 undef $noreg, [[PseudoVLE32_V_MF2_MASK]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0 = COPY [[PseudoVADD_VX_MF2_]], implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v0 + bb.0: + successors: %bb.1(0x80000000) + liveins: $x10, $x11 + + %0:gpr = COPY $x11 + %1:gpr = COPY $x10 + %2:gpr = IMPLICIT_DEF + %3:vr = PseudoVID_V_MF2 undef $noreg, -1, 6, 0 + %4:vrnov0 = PseudoVMV_V_I_MF2 undef $noreg, 0, -1, 5, 0 + + bb.1: + successors: %bb.2(0x40000000), %bb.3(0x40000000) + + %5:vmv0 = PseudoVMSEQ_VI_MF2 killed %3, 0, -1, 5 + $v0 = COPY %5 + %6:vrnov0 = PseudoVLE32_V_MF2_MASK %4, killed %0, $v0, -1, 5, 0 + %7:gpr = PseudoVCPOP_M_B64 %5, -1, 0 + %8:gpr = COPY $x0 + BEQ killed %7, %8, %bb.3 + PseudoBR %bb.2 + + bb.2: + successors: %bb.3(0x80000000) + + %9:gpr = LWU %1, 0 + + bb.3: + %10:gpr = PHI %2, %bb.1, %9, %bb.2 + %11:vr = nsw PseudoVADD_VX_MF2 undef $noreg, %6, %10, -1, 5, 0 + $v0 = COPY %11 + PseudoRET implicit $v0 +... +--- +name: vsetvli_loop_store +tracksRegLiveness: true +registers: + - { id: 0, class: gpr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: gpr, preferred-register: '' } + - { id: 3, class: gpr, preferred-register: '' } + - { id: 4, class: vr, preferred-register: '' } + - { id: 5, class: gpr, preferred-register: '' } + - { id: 6, class: gpr, preferred-register: '' } + - { id: 7, class: vr, preferred-register: '' } + - { id: 8, class: gpr, preferred-register: '' } + - { id: 9, class: gpr, preferred-register: '' } + - { id: 10, class: gpr, preferred-register: '' } +body: | + ; CHECK-LABEL: name: vsetvli_loop_store + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[COPY2]], -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY2]], [[SRLI]] + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]] + ; CHECK-NEXT: PseudoVSE32_V_MF2 [[PseudoVADD_VX_M1_]], [[ADD]], -1 /* vl=VLMAX */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = ADDI [[COPY2]], 1 + ; CHECK-NEXT: BLTU [[COPY2]], [[COPY1]], %bb.1 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: PseudoRET + bb.0: + liveins: $x10, $x11 + %0:gpr = COPY $x10 + %1:gpr = PseudoReadVLENB + %2:gpr = SRLI %1:gpr, 3 + %3:gpr = COPY $x11 + %4:vr = PseudoVID_V_M1 undef $noreg, -1, 6, 0 + %5:gpr = COPY $x0 + + bb.1: + successors: %bb.1, %bb.2 + + %6:gpr = PHI %5:gpr, %bb.0, %10:gpr, %bb.1 + %7:vr = PseudoVADD_VX_M1 undef $noreg, %4:vr, %6:gpr, -1, 6, 0 + %8:gpr = MUL %6:gpr, %2:gpr + %9:gpr = ADD %0:gpr, %8:gpr + PseudoVSE32_V_MF2 killed %7:vr, killed %9:gpr, -1, 5 + %10:gpr = ADDI %6:gpr, 1 + BLTU %10:gpr, %3:gpr, %bb.1 + PseudoBR %bb.2 + + bb.2: + + PseudoRET +... +--- +name: vsetvli_loop_store2 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: gpr, preferred-register: '' } + - { id: 3, class: gpr, preferred-register: '' } + - { id: 4, class: vr, preferred-register: '' } + - { id: 5, class: gpr, preferred-register: '' } + - { id: 6, class: gpr, preferred-register: '' } + - { id: 7, class: vr, preferred-register: '' } + - { id: 8, class: gpr, preferred-register: '' } + - { id: 9, class: gpr, preferred-register: '' } + - { id: 10, class: gpr, preferred-register: '' } +body: | + ; CHECK-LABEL: name: vsetvli_loop_store2 + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[COPY2]], -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY2]], [[SRLI]] + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]] + ; CHECK-NEXT: PseudoVSE32_V_MF2 [[PseudoVADD_VX_M1_]], [[ADD]], -1 /* vl=VLMAX */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = ADDI [[COPY2]], 1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BLTU [[COPY2]], [[COPY1]], %bb.1 + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: PseudoRET + bb.0: + liveins: $x10, $x11 + %0:gpr = COPY $x10 + %1:gpr = PseudoReadVLENB + %2:gpr = SRLI %1:gpr, 3 + %3:gpr = COPY $x11 + %4:vr = PseudoVID_V_M1 undef $noreg, -1, 6, 3 + %5:gpr = COPY $x0 + + bb.1: + successors: %bb.3 + + %6:gpr = PHI %5:gpr, %bb.0, %10:gpr, %bb.3 + %7:vr = PseudoVADD_VX_M1 undef $noreg, %4:vr, %6:gpr, -1, 6, 0 + %8:gpr = MUL %6:gpr, %2:gpr + %9:gpr = ADD %0:gpr, %8:gpr + PseudoVSE32_V_MF2 killed %7:vr, killed %9:gpr, -1, 5 + %10:gpr = ADDI %6:gpr, 1 + + bb.3: + successors: %bb.1, %bb.2 + BLTU %10:gpr, %3:gpr, %bb.1 + PseudoBR %bb.2 + + bb.2: + + PseudoRET +... +--- +name: redusum_loop +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: vr } + - { id: 3, class: vr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } + - { id: 6, class: gpr } + - { id: 7, class: gpr } + - { id: 8, class: gpr } + - { id: 9, class: gpr } + - { id: 10, class: vr } + - { id: 11, class: vr } + - { id: 12, class: vr } + - { id: 13, class: gpr } + - { id: 14, class: vr } + - { id: 15, class: vr } + - { id: 16, class: vr } + - { id: 17, class: vr } + - { id: 18, class: gpr } + - { id: 19, class: gpr } + - { id: 20, class: vr } + - { id: 21, class: vr } + - { id: 22, class: vr } + - { id: 23, class: vr } + - { id: 24, class: vr } +liveins: + - { reg: '$x10', virtual-reg: '%6' } + - { reg: '$x12', virtual-reg: '%8' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + ; CHECK-LABEL: name: redusum_loop + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x10, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 0, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1 + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], -2048 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 undef $noreg, [[COPY1]], 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.lsr.iv12, align 4) + ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE32_V_M1_]], [[PseudoVMV_V_I_M1_]], 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = nsw ADDI [[ADDIW]], -4 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = ADDI [[COPY1]], 16 + ; CHECK-NEXT: BNE [[ADDIW]], $x0, %bb.1 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.middle.block: + ; CHECK-NEXT: [[PseudoVMV_S_X:%[0-9]+]]:vr = PseudoVMV_S_X undef $noreg, $x0, 1 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, [[PseudoVMV_V_I_M1_]], [[PseudoVMV_S_X]], 4 /* vl */, 5 /* e32 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: PseudoVSE32_V_M1 [[PseudoVREDSUM_VS_M1_E8_]], [[COPY]], 1 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype :: (store (s32) into %ir.res) + ; CHECK-NEXT: PseudoRET + bb.0.entry: + liveins: $x10, $x12 + + %8:gpr = COPY $x12 + %6:gpr = COPY $x10 + %11:vr = PseudoVMV_V_I_M1 undef $noreg, 0, 4, 5, 0 + %12:vr = COPY %11 + %10:vr = COPY %12 + %13:gpr = LUI 1 + %9:gpr = ADDIW killed %13, -2048 + + bb.1.vector.body: + successors: %bb.2(0x04000000), %bb.1(0x7c000000) + + %0:gpr = PHI %6, %bb.0, %5, %bb.1 + %1:gpr = PHI %9, %bb.0, %4, %bb.1 + %2:vr = PHI %10, %bb.0, %16, %bb.1 + %14:vr = PseudoVLE32_V_M1 undef $noreg, %0, 4, 5, 0 :: (load (s128) from %ir.lsr.iv12, align 4) + %16:vr = PseudoVADD_VV_M1 undef $noreg, killed %14, %2, 4, 5, 0 + %4:gpr = nsw ADDI %1, -4 + %5:gpr = ADDI %0, 16 + %18:gpr = COPY $x0 + BNE %4, %18, %bb.1 + PseudoBR %bb.2 + + bb.2.middle.block: + %19:gpr = COPY $x0 + %20:vr = PseudoVMV_S_X undef $noreg, %19, 1, 5 + %23:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, %16, killed %20, 4, 5, 1 + PseudoVSE32_V_M1 killed %23, %8, 1, 5 :: (store (s32) into %ir.res) + PseudoRET + +... +--- +name: vsetvli_vluxei64_regression +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: vsetvli_vluxei64_regression + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12, $v0, $v1, $v2, $v3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %a:gpr = COPY $x10 + ; CHECK-NEXT: %b:gpr = COPY $x11 + ; CHECK-NEXT: %inaddr:gpr = COPY $x12 + ; CHECK-NEXT: %idxs:vr = COPY $v0 + ; CHECK-NEXT: %t1:vr = COPY $v1 + ; CHECK-NEXT: %t3:vr = COPY $v2 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrnov0 = COPY $v3 + ; CHECK-NEXT: %t5:vrnov0 = COPY $v1 + ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1 /* vl=VLMAX */, 6 /* e64 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %mask:vr = PseudoVMANDN_MM_B64 %t6, %t3, -1 /* vl=VLMAX */, 0 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: BEQ %a, $x0, %bb.3 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $v0 = COPY %mask, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: early-clobber [[COPY]]:vrnov0 = PseudoVLUXEI64_V_M1_MF8_MASK %t5, %inaddr, %idxs, $v0, -1 /* vl=VLMAX */, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoBR %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v0 = COPY %mask, implicit $vtype + ; CHECK-NEXT: PseudoVSOXEI64_V_M1_MF8_MASK [[COPY]], %b, %idxs, $v0, -1 /* vl=VLMAX */, 3 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.1 + liveins: $x10, $x11, $x12, $v0, $v1, $v2, $v3 + + %a:gpr = COPY $x10 + %b:gpr = COPY $x11 + %inaddr:gpr = COPY $x12 + %idxs:vr = COPY $v0 + %t1:vr = COPY $v1 + %t3:vr = COPY $v2 + %t4:vr = COPY $v3 + %t5:vrnov0 = COPY $v1 + %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1, 6 + PseudoBR %bb.1 + + bb.1: + successors: %bb.3, %bb.2 + + %mask:vr = PseudoVMANDN_MM_B64 %t6, %t3, -1, 0 + %t2:gpr = COPY $x0 + BEQ %a, %t2, %bb.3 + PseudoBR %bb.2 + + bb.2: + successors: %bb.3 + + $v0 = COPY %mask + early-clobber %t0:vrnov0 = PseudoVLUXEI64_V_M1_MF8_MASK %t5, killed %inaddr, %idxs, $v0, -1, 3, 1 + %ldval:vr = COPY %t0 + PseudoBR %bb.3 + + bb.3: + %stval:vr = PHI %t4, %bb.1, %ldval, %bb.2 + $v0 = COPY %mask + PseudoVSOXEI64_V_M1_MF8_MASK killed %stval, killed %b, %idxs, $v0, -1, 3 + PseudoRET + +... +--- +name: if_in_loop +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: if_in_loop + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %dst:gpr = COPY $x10 + ; CHECK-NEXT: %src:gpr = COPY $x11 + ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: %tc:gpr = COPY $x13 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x14 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x15 + ; CHECK-NEXT: %vlenb:gpr = PseudoReadVLENB + ; CHECK-NEXT: %inc:gpr = SRLI %vlenb, 3 + ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY2]], [[COPY3]] + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[ADD]], -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVMSLTU_VX_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VX_M1 [[PseudoVADD_VX_M1_]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSLTU_VX_M1_]], -1 /* vl=VLMAX */, 0 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B64_]], $x0, %bb.3 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD %src, [[COPY3]] + ; CHECK-NEXT: [[PseudoVLE8_V_MF8_:%[0-9]+]]:vrnov0 = PseudoVLE8_V_MF8 undef $noreg, [[ADD1]], -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: [[PseudoVADD_VI_MF8_:%[0-9]+]]:vrnov0 = PseudoVADD_VI_MF8 undef $noreg, [[PseudoVLE8_V_MF8_]], 4, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD %dst, [[COPY3]] + ; CHECK-NEXT: PseudoVSE8_V_MF8 [[PseudoVADD_VI_MF8_]], [[ADD2]], -1 /* vl=VLMAX */, 3 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.4(0x04000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = ADD [[COPY3]], %inc + ; CHECK-NEXT: BLTU [[COPY3]], %tc, %bb.1 + ; CHECK-NEXT: PseudoBR %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.1(0x80000000) + liveins: $x10, $x11, $x12, $x13, $x14, $x15 + + %dst:gpr = COPY $x10 + %src:gpr = COPY $x11 + %48:gpr = COPY $x12 + %tc:gpr = COPY $x13 + %11:gpr = COPY $x14 + %12:gpr = COPY $x15 + %vlenb:gpr = PseudoReadVLENB + %inc:gpr = SRLI killed %vlenb, 3 + %10:vr = PseudoVID_V_M1 undef $noreg, -1, 6, 0 + %59:gpr = COPY $x0 + PseudoBR %bb.1 + + bb.1: + successors: %bb.2(0x40000000), %bb.3(0x40000000) + + %26:gpr = PHI %59, %bb.0, %28, %bb.3 + %61:gpr = ADD %12, %26 + %27:vr = PseudoVADD_VX_M1 undef $noreg, %10, killed %61, -1, 6, 0 + %62:vr = PseudoVMSLTU_VX_M1 %27, %11, -1, 6 + %63:gpr = PseudoVCPOP_M_B64 %62, -1, 0 + %64:gpr = COPY $x0 + BEQ killed %63, %64, %bb.3 + PseudoBR %bb.2 + + bb.2: + successors: %bb.3(0x80000000) + + %66:gpr = ADD %src, %26 + %67:vrnov0 = PseudoVLE8_V_MF8 undef $noreg, killed %66, -1, 3, 0 + %76:vrnov0 = PseudoVADD_VI_MF8 undef $noreg, %67, 4, -1, 3, 0 + %77:gpr = ADD %dst, %26 + PseudoVSE8_V_MF8 killed %76, killed %77, -1, 3 + + bb.3: + successors: %bb.1(0x7c000000), %bb.4(0x04000000) + + %28:gpr = ADD %26, %inc + BLTU %28, %tc, %bb.1 + PseudoBR %bb.4 + + bb.4: + PseudoRET + +... +--- +name: pre_undemanded_vl +body: | + ; CHECK-LABEL: name: pre_undemanded_vl + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S undef $noreg, 6 /* e64 */, implicit $vtype + ; CHECK-NEXT: PseudoBR %bb.1 + bb.0: + PseudoBR %bb.1 + bb.1: + %x:gpr = PseudoVMV_X_S undef $noreg, 6 + PseudoBR %bb.1 +... +--- +name: clobberred_forwarded_avl +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: clobberred_forwarded_avl + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x10, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY %avl + ; CHECK-NEXT: dead %outvl:gprnox0 = PseudoVSETVLI %avl, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead %avl:gprnox0 = ADDI %avl, 1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: liveins: $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, renamable $v8m2, renamable $v8m2, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, renamable $v8m2, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8m2 + bb.0: + liveins: $x10, $v8m2 + %avl:gprnox0 = COPY $x10 + %outvl:gprnox0 = PseudoVSETVLI %avl:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype + + bb.1: + liveins: $v8m2 + %avl:gprnox0 = ADDI %avl:gprnox0, 1 + + bb.2: + liveins: $v8m2 + renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, renamable $v8m2, renamable $v8m2, -1, 5, 0 + renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, killed renamable $v8m2, %outvl:gprnox0, 5, 0 + PseudoRET implicit $v8m2 +... +--- +name: clobberred_forwarded_phi_avl +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: clobberred_forwarded_phi_avl + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10, $x11, $v8m2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %v:vrm2 = COPY $v8m2 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, 1 + ; CHECK-NEXT: %x:gpr = COPY $x10 + ; CHECK-NEXT: %y:gpr = COPY $x11 + ; CHECK-NEXT: BEQ %x, %y, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, 2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY [[ADDI]] + ; CHECK-NEXT: dead %outvl:gprnox0 = PseudoVSETVLI [[ADDI]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[ADDI:%[0-9]+]]:gprnox0 = ADDI [[ADDI]], 1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, %v, %v, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, %v, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8m2 + bb.0: + liveins: $x10, $x11, $v8m2 + %v:vrm2 = COPY $v8m2 + %a:gpr = ADDI $x0, 1 + %x:gpr = COPY $x10 + %y:gpr = COPY $x11 + BEQ %x, %y, %bb.2 + + bb.1: + %b:gpr = ADDI $x0, 2 + + bb.2: + %avl:gprnox0 = PHI %a, %bb.0, %b, %bb.1 + %outvl:gprnox0 = PseudoVSETVLI %avl:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype + + bb.3: + %avl:gprnox0 = ADDI %avl:gprnox0, 1 + + bb.4: + renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, %v, %v, -1, 5, 0 + renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, killed %v, %outvl:gprnox0, 5, 0 + PseudoRET implicit $v8m2 +... +--- +name: avl_is_last_instr +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: avl_is_last_instr + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY %avl + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: dead %avl:gprnox0 = ADDI %avl, -1 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v8 = PseudoVMV_S_X undef renamable $v8, $x0, 1 /* vl */, 3 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v8 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, $noreg /* vl */, 3 /* e8 */, 3 /* ta, ma */, implicit $vl, implicit $vtype + bb.0: + liveins: $x10 + %avl:gprnox0 = COPY $x10 + + bb.1: + %vl:gprnox0 = PseudoVSETVLI %avl:gprnox0, 192, implicit-def dead $vl, implicit-def dead $vtype + %avl:gprnox0 = ADDI %avl:gprnox0, -1 + $v8 = PseudoVMV_S_X undef renamable $v8, $x0, 1, 3 + $v8 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %vl:gprnox0, 3, 3 diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir new file mode 100644 index 0000000..d71be1c --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir @@ -0,0 +1,37 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -mtriple=riscv64 -mattr=+zve64f -run-pass=riscv-insert-vsetvli -o - | FileCheck %s + +--- +name: spam +tracksRegLiveness: true +noPhis: true +isSSA: false +body: | + bb.0.entry: + liveins: $x10, $x11, $x12, $f10_f + + ; CHECK-LABEL: name: spam + ; CHECK: liveins: $x10, $x11, $x12, $f10_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 8, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v10 = PseudoVFMV_S_FPR32 undef renamable $v10, [[COPY3]], 8 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v11 = PseudoVMV_S_X undef renamable $v11, [[COPY2]], 8 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, [[COPY1]], 1 /* vl */, 6 /* e64 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 8) + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 8, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, [[COPY]], 8 /* vl */, 5 /* e32 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 4) + ; CHECK-NEXT: PseudoRET implicit $v8, implicit $v9, implicit $v10, implicit $v11 + %3:gpr = COPY $x12 + %2:gpr = COPY $x11 + %1:gpr = COPY $x10 + %0:fpr32 = COPY $f10_f + renamable $v10 = PseudoVFMV_S_FPR32 undef renamable $v10, %0, 8, 5 /* e32 */ + renamable $v11 = PseudoVMV_S_X undef renamable $v11, %1, 8, 5 /* e32 */ + renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, %2, 1, 6 /* e64 */, 2 /* tu, ma */ :: (load unknown-size, align 8) + renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, %3, 8, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size, align 4) + PseudoRET implicit $v8, implicit $v9, implicit $v10, implicit $v11 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir new file mode 100644 index 0000000..a82c1a4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir @@ -0,0 +1,699 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc %s -o - -mtriple=riscv64 -mattr=v -run-pass=liveintervals,riscv-insert-vsetvli \ +# RUN: -verify-machineinstrs | FileCheck %s + +--- | + source_filename = "vsetvli-insert.ll" + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" + target triple = "riscv64" + + define @add( %0, %1, i64 %2) #0 { + entry: + %a = call @llvm.riscv.vadd.nxv1i64.nxv1i64.i64( undef, %0, %1, i64 %2) + ret %a + } + + define @load_add(ptr %0, %1, i64 %2) #0 { + entry: + %a = call @llvm.riscv.vle.nxv1i64.i64( undef, ptr %0, i64 %2) + %b = call @llvm.riscv.vadd.nxv1i64.nxv1i64.i64( undef, %a, %1, i64 %2) + ret %b + } + + define @load_zext(ptr %0, i64 %1) #0 { + entry: + %a = call @llvm.riscv.vle.nxv1i32.i64( undef, ptr %0, i64 %1) + %b = call @llvm.riscv.vzext.nxv1i64.nxv1i32.i64( undef, %a, i64 %1) + ret %b + } + + define i64 @vmv_x_s( %0) #0 { + entry: + %a = call i64 @llvm.riscv.vmv.x.s.nxv1i64( %0) + ret i64 %a + } + + define void @add_v2i64(ptr %x, ptr %y) #0 { + %a = load <2 x i64>, ptr %x, align 16 + %b = load <2 x i64>, ptr %y, align 16 + %c = add <2 x i64> %a, %b + store <2 x i64> %c, ptr %x, align 16 + ret void + } + + define i64 @vreduce_add_v2i64(ptr %x) #0 { + %v = load <2 x i64>, ptr %x, align 16 + %red = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %v) + ret i64 %red + } + + define @vsetvli_add( %0, %1, i64 %avl) #0 { + entry: + %a = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 3, i64 0) + %b = call @llvm.riscv.vadd.nxv1i64.nxv1i64.i64( undef, %0, %1, i64 %a) + ret %b + } + + define @load_add_inlineasm(ptr %0, %1, i64 %2) #0 { + entry: + %a = call @llvm.riscv.vle.nxv1i64.i64( undef, ptr %0, i64 %2) + call void asm sideeffect "", ""() + %b = call @llvm.riscv.vadd.nxv1i64.nxv1i64.i64( undef, %a, %1, i64 %2) + ret %b + } + + define void @vmv_v_i_different_lmuls() { + ret void + } + + define void @pre_same_sewlmul_ratio() { + ret void + } + + define void @postpass_modify_vl() { + ret void + } + + define void @coalesce_dead_avl_addi() { + ret void + } + + define void @coalesce_dead_avl_nonvolatile_load() { + ret void + } + + define void @coalesce_dead_avl_volatile_load() { + ret void + } + + define void @coalesce_shrink_removed_vsetvlis_uses() { + ret void + } + + define void @coalesce_vl_avl_same_reg() { + ret void + } + + define void @coalesce_vl_clobber() { + ret void + } + + define void @vsetvli_vleff() { + ret void + } + + define void @non_li_addi() { + ret void + } + + attributes #0 = { "target-features"="+v" } + +... +--- +name: add +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vr } + - { id: 1, class: vr } + - { id: 2, class: gprnox0 } + - { id: 3, class: vr } +liveins: + - { reg: '$v8', virtual-reg: '%0' } + - { reg: '$v9', virtual-reg: '%1' } + - { reg: '$x10', virtual-reg: '%2' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8, $v9, $x10 + + ; CHECK-LABEL: name: add + ; CHECK: liveins: $v8, $v9, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8 + %2:gprnox0 = COPY $x10 + %1:vr = COPY $v9 + %0:vr = COPY $v8 + %3:vr = PseudoVADD_VV_M1 undef $noreg, %0, %1, %2, 6, 0 + $v8 = COPY %3 + PseudoRET implicit $v8 + +... +--- +name: load_add +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: vr } + - { id: 2, class: gprnox0 } + - { id: 3, class: vr } + - { id: 4, class: vr } +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$v8', virtual-reg: '%1' } + - { reg: '$x11', virtual-reg: '%2' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10, $v8, $x11 + + ; CHECK-LABEL: name: load_add + ; CHECK: liveins: $x10, $v8, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8 + %2:gprnox0 = COPY $x11 + %1:vr = COPY $v8 + %0:gpr = COPY $x10 + %3:vr = PseudoVLE64_V_M1 undef $noreg, %0, %2, 6, 0 + %4:vr = PseudoVADD_VV_M1 undef $noreg, killed %3, %1, %2, 6, 0 + $v8 = COPY %4 + PseudoRET implicit $v8 + +... +--- +name: load_zext +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gprnox0 } + - { id: 2, class: vr } + - { id: 3, class: vr } +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: load_zext + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 undef $noreg, [[COPY1]], $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %3:vr = PseudoVZEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8 = COPY %3, implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:gprnox0 = COPY $x11 + %0:gpr = COPY $x10 + %2:vr = PseudoVLE32_V_MF2 undef $noreg, %0, %1, 5, 0 + early-clobber %3:vr = PseudoVZEXT_VF2_M1 undef $noreg, killed %2, %1, 6, 0 + $v8 = COPY %3 + PseudoRET implicit $v8 + +... +--- +name: vmv_x_s +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vr } + - { id: 1, class: gpr } +liveins: + - { reg: '$v8', virtual-reg: '%0' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8 + + ; CHECK-LABEL: name: vmv_x_s + ; CHECK: liveins: $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S [[COPY]], 6 /* e64 */, implicit $vtype + ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:vr = COPY $v8 + %1:gpr = PseudoVMV_X_S %0, 6 + $x10 = COPY %1 + PseudoRET implicit $x10 + +... +--- +name: add_v2i64 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: vr } + - { id: 3, class: vr } + - { id: 4, class: vr } +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0 (%ir-block.0): + liveins: $x10, $x11 + + ; CHECK-LABEL: name: add_v2i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY1]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x) + ; CHECK-NEXT: [[PseudoVLE64_V_M1_1:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.y) + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[PseudoVLE64_V_M1_1]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE64_V_M1 [[PseudoVADD_VV_M1_]], [[COPY1]], 2 /* vl */, 6 /* e64 */, implicit $vl, implicit $vtype :: (store (s128) into %ir.x) + ; CHECK-NEXT: PseudoRET + %1:gpr = COPY $x11 + %0:gpr = COPY $x10 + %2:vr = PseudoVLE64_V_M1 undef $noreg, %0, 2, 6, 0 :: (load (s128) from %ir.x) + %3:vr = PseudoVLE64_V_M1 undef $noreg, %1, 2, 6, 0 :: (load (s128) from %ir.y) + %4:vr = PseudoVADD_VV_M1 undef $noreg, killed %2, killed %3, 2, 6, 0 + PseudoVSE64_V_M1 killed %4, %0, 2, 6 :: (store (s128) into %ir.x) + PseudoRET + +... +--- +name: vreduce_add_v2i64 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: vr } + - { id: 2, class: vr } + - { id: 3, class: vr } + - { id: 4, class: vr } + - { id: 5, class: gpr } +liveins: + - { reg: '$x10', virtual-reg: '%0' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0 (%ir-block.0): + liveins: $x10 + + ; CHECK-LABEL: name: vreduce_add_v2i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x) + ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 0, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, [[PseudoVLE64_V_M1_]], [[PseudoVMV_V_I_M1_]], 2 /* vl */, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S [[PseudoVREDSUM_VS_M1_E8_]], 6 /* e64 */, implicit $vtype + ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gpr = COPY $x10 + %1:vr = PseudoVLE64_V_M1 undef $noreg, %0, 2, 6, 0 :: (load (s128) from %ir.x) + %2:vr = PseudoVMV_V_I_M1 undef $noreg, 0, -1, 6, 0 + %3:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, killed %1, killed %2, 2, 6, 1 + %5:gpr = PseudoVMV_X_S killed %3, 6 + $x10 = COPY %5 + PseudoRET implicit $x10 + +... +--- +name: vsetvli_add +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vr } + - { id: 1, class: vr } + - { id: 2, class: gprnox0 } + - { id: 3, class: gprnox0 } + - { id: 4, class: vr } +liveins: + - { reg: '$v8', virtual-reg: '%0' } + - { reg: '$v9', virtual-reg: '%1' } + - { reg: '$x10', virtual-reg: '%2' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8, $v9, $x10 + + ; CHECK-LABEL: name: vsetvli_add + ; CHECK: liveins: $v8, $v9, $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: dead [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8 + %2:gprnox0 = COPY $x10 + %1:vr = COPY $v9 + %0:vr = COPY $v8 + %3:gprnox0 = PseudoVSETVLI %2, 88, implicit-def dead $vl, implicit-def dead $vtype + %4:vr = PseudoVADD_VV_M1 undef $noreg, %0, %1, killed %3, 6, 0 + $v8 = COPY %4 + PseudoRET implicit $v8 + +... +--- +name: load_add_inlineasm +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: vr } + - { id: 2, class: gprnox0 } + - { id: 3, class: vr } + - { id: 4, class: vr } +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$v8', virtual-reg: '%1' } + - { reg: '$x11', virtual-reg: '%2' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10, $v8, $x11 + + ; CHECK-LABEL: name: load_add_inlineasm + ; CHECK: liveins: $x10, $v8, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8 + %2:gprnox0 = COPY $x11 + %1:vr = COPY $v8 + %0:gpr = COPY $x10 + %3:vr = PseudoVLE64_V_M1 undef $noreg, %0, %2, 6, 0 + INLINEASM &"", sideeffect attdialect + %4:vr = PseudoVADD_VV_M1 undef $noreg, killed %3, %1, %2, 6, 0 + $v8 = COPY %4 + PseudoRET implicit $v8 + +... +--- +name: vmv_v_i_different_lmuls +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $v8, $x11 + + ; CHECK-LABEL: name: vmv_v_i_different_lmuls + ; CHECK: liveins: $x10, $v8, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 217 /* e64, m2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 undef $noreg, 4 /* vl */, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 198 /* e8, mf4, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 undef $noreg, 0, 4 /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %0:vrm2 = PseudoVID_V_M2 undef $noreg, 4, 6, 3 + %4:vr = PseudoVMV_V_I_MF4 undef $noreg, 0, 4, 3, 0 + PseudoRET +... +--- +# make sure we don't try to perform PRE when one of the blocks is sew/lmul ratio +# only +name: pre_same_sewlmul_ratio +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: pre_same_sewlmul_ratio + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %cond:gpr = COPY $x10 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: BEQ %cond, $x0, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: dead [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 1, 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BEQ %cond, $x0, %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: PseudoCALL $noreg, csr_ilp32_lp64 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S undef $noreg, 5 /* e32 */, implicit $vtype + ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_1:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + bb.0: + liveins: $x10 + %cond:gpr = COPY $x10 + %1:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2, 5, 0 + BEQ %cond, $x0, %bb.2 + bb.1: + %2:vr = PseudoVMV_V_I_M1 undef $noreg, 1, 2, 6, 0 + bb.2: ; the exit info here should have sew/lmul ratio only + BEQ %cond, $x0, %bb.4 + bb.3: + PseudoCALL $noreg, csr_ilp32_lp64 + bb.4: ; this block will have PRE attempted on it + %4:gpr = PseudoVMV_X_S undef $noreg, 5 + %5:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2, 5, 0 + PseudoRET +... +--- +name: postpass_modify_vl +tracksRegLiveness: true +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: postpass_modify_vl + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $vtype + ; CHECK-NEXT: $vl = COPY $x1 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, undef $noreg, undef $noreg, 3 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype + %1:gpr = COPY $vtype + $vl = COPY $x1 + dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype + %4:vr = PseudoVADD_VV_M1 undef $noreg, undef $noreg, undef $noreg, 3, 6, 0 + PseudoRET +... +--- +name: coalesce_dead_avl_addi +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: name: coalesce_dead_avl_addi + ; CHECK: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype + ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %avl:gprnox0 = ADDI $x0, 42 + dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype + %x:gpr = PseudoVMV_X_S $noreg, 6 + dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype + $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6, 0 + PseudoRET +... +--- +name: coalesce_dead_avl_nonvolatile_load +tracksRegLiveness: true +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: coalesce_dead_avl_nonvolatile_load + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %ptr:gpr = COPY $x1 + ; CHECK-NEXT: dead %avl:gprnox0 = LW %ptr, 0 :: (dereferenceable load (s32)) + ; CHECK-NEXT: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype + ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %ptr:gpr = COPY $x1 + %avl:gprnox0 = LW killed %ptr, 0 :: (dereferenceable load (s32)) + dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype + %x:gpr = PseudoVMV_X_S $noreg, 6 + dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype + $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6, 0 + PseudoRET +... +--- +name: coalesce_dead_avl_volatile_load +tracksRegLiveness: true +body: | + bb.0: + liveins: $x1 + ; CHECK-LABEL: name: coalesce_dead_avl_volatile_load + ; CHECK: liveins: $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %ptr:gpr = COPY $x1 + ; CHECK-NEXT: dead %avl:gprnox0 = LW %ptr, 0 :: (volatile dereferenceable load (s32)) + ; CHECK-NEXT: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype + ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %ptr:gpr = COPY $x1 + %avl:gprnox0 = LW killed %ptr, 0 :: (volatile dereferenceable load (s32)) + dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype + %x:gpr = PseudoVMV_X_S $noreg, 6 + dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype + $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6, 0 + PseudoRET +... +--- +name: coalesce_shrink_removed_vsetvlis_uses +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $v8 + ; CHECK-LABEL: name: coalesce_shrink_removed_vsetvlis_uses + ; CHECK: liveins: $x10, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %avl2:gprnox0 = ADDI $x0, 2 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI %avl2, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: %x:gpr = COPY $x10 + ; CHECK-NEXT: renamable $v8 = PseudoVMV_S_X undef renamable $v8, %x, 1 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8 + %avl1:gprnox0 = ADDI $x0, 1 + dead $x0 = PseudoVSETVLI %avl1:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype + %avl2:gprnox0 = ADDI $x0, 2 + dead $x0 = PseudoVSETVLI %avl2:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype + %x:gpr = COPY $x10 + renamable $v8 = PseudoVMV_S_X undef renamable $v8, killed renamable %x, 1, 5 + PseudoRET implicit $v8 +... +--- +name: coalesce_vl_avl_same_reg +tracksRegLiveness: true +body: | + bb.0: + liveins: $x8, $v8 + ; CHECK-LABEL: name: coalesce_vl_avl_same_reg + ; CHECK: liveins: $x8, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:gprnox0 = COPY $x8 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead %v:vr = COPY $v8, implicit $vtype + ; CHECK-NEXT: dead %x:gprnox0 = PseudoVSETVLI %x, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + %x:gprnox0 = COPY $x8 + dead $x0 = PseudoVSETIVLI 1, 208, implicit-def $vl, implicit-def $vtype + %v:vr = COPY $v8, implicit $vtype + %x = PseudoVSETVLI %x, 208, implicit-def $vl, implicit-def $vtype +... +--- +# Because of the %y:gprnox0 = COPY %x, we can't extend the live range of %x from +# the second vsetvli to the first vsetvli when coalescing. +name: coalesce_vl_clobber +tracksRegLiveness: true +body: | + bb.0: + liveins: $x8, $v8 + ; CHECK-LABEL: name: coalesce_vl_clobber + ; CHECK: liveins: $x8, $v8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:gprnox0 = COPY $x8 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead %y:gprnox0 = COPY %x + ; CHECK-NEXT: dead %v:vr = COPY $v8, implicit $vtype + ; CHECK-NEXT: dead %x:gprnox0 = PseudoVSETVLI %x, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + %x:gprnox0 = COPY $x8 + dead $x0 = PseudoVSETIVLI 1, 208, implicit-def $vl, implicit-def $vtype + %y:gprnox0 = COPY %x + %v:vr = COPY $v8, implicit $vtype + %x = PseudoVSETVLI %x, 208, implicit-def $vl, implicit-def $vtype +... +--- +name: vsetvli_vleff +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: vsetvli_vleff + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %vl:gpr = COPY $x0 + ; CHECK-NEXT: BNE $x0, $x0, %bb.2 + ; CHECK-NEXT: PseudoBR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 200 /* e16, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $noreg, $x0 = PseudoVLE16FF_V_M1 $noreg, $noreg, 0 /* vl */, 4 /* e16 */, 2 /* tu, ma */, implicit $vl, implicit $vtype, implicit-def $vl + ; CHECK-NEXT: %vl:gpr = PseudoReadVL implicit $vl + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: $x10 = COPY %vl + ; CHECK-NEXT: PseudoRET implicit killed $x10 + bb.0: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + + %vl:gpr = COPY $x0 + BNE $x0, $x0, %bb.2 + PseudoBR %bb.1 + + bb.1: + successors: %bb.2(0x80000000) + + $noreg, %vl:gpr = PseudoVLE16FF_V_M1 $noreg, $noreg, 0, 4 /* e16 */, 2 /* tu, ma */ + + bb.2: + $x10 = COPY %vl + PseudoRET implicit killed $x10 +... +--- +# The two vsetvlis will be coalesced so the ADDI will be made dead and removed. +# Make sure we shrink the live interval of %0. +name: non_li_addi +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: non_li_addi + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead [[PseudoVSETIVLI:%[0-9]+]]:gprnox0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gprnox0 = ADDI %0, 1 + %2:gprnox0 = PseudoVSETVLI %1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + %3:gprnox0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + PseudoRET diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vxrm.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vxrm.mir new file mode 100644 index 0000000..7457971 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/vxrm.mir @@ -0,0 +1,30 @@ +# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -stop-after prologepilog -o - %s | FileCheck %s --check-prefix=MIR +# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=ASM + +--- +name: verify_vxrm +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8, $v9, $x10 + + ; MIR-LABEL: name: verify_vxrm + ; MIR: liveins: $v8, $v9, $x10 + ; MIR-NEXT: {{ $}} + ; MIR-NEXT: WriteVXRMImm 0, implicit-def $vxrm + ; MIR-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype + ; MIR-NEXT: renamable $v8 = PseudoVAADD_VV_MF8 undef renamable $v8, killed renamable $v8, killed renamable $v9, 0 /* vxrm=rnu */, $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vxrm, implicit $vl, implicit $vtype + ; MIR-NEXT: PseudoRET implicit $v8 + ; ASM-LABEL: verify_vxrm: + ; ASM: # %bb.0: + ; ASM-NEXT: csrwi vxrm, 0 + ; ASM-NEXT: vsetvli zero, a0, e8, mf8, ta, ma + ; ASM-NEXT: vaadd.vv v8, v8, v9 + ; ASM-NEXT: ret + %0:vr = COPY $v8 + %1:vr = COPY $v9 + %2:gprnox0 = COPY $x10 + %3:vr = PseudoVAADD_VV_MF8 undef $noreg, %0, %1, 0, %2, 3 /* e8 */, 0 + $v8 = COPY %3 + PseudoRET implicit $v8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir new file mode 100644 index 0000000..7c9574e --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir @@ -0,0 +1,201 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple riscv64 -mattr=+m,+v -run-pass=prologepilog \ +# RUN: -riscv-v-vector-bits-min=512 -o - %s | FileCheck %s +# +# Stack layout of this program +# |--------------------------| -- <-- Incoming SP +# | a7 (Vaarg) | +# | ------------------------ | -- <-- New SP + vlenb + 72 +# | a6 (Vaarg) | +# | ------------------------ | -- <-- New SP + vlenb + 64 +# | ra (Callee-saved reg) | +# | ------------------------ | -- <-- New SP + vlenb + 56 +# | s0 (Callee-saved reg) | +# | ------------------------ | -- <-- New SP + vlenb + 48 +# | s1 (Callee-saved reg) | +# | ------------------------ | -- <-- New SP + vlenb + 40 +# | 8 bytes of padding | +# | ------------------------ | -- <-- New SP + vlenb +# | v8 (RVV objects) | +# | ------------------------ | -- <-- New SP + 32 +# | buf1 | +# |--------------------------| -- <-- New SP + 16 +# | Stack ID 5 | +# |--------------------------| -- <-- New SP + 8 +# | Stack ID 6 | +# |--------------------------| -- <-- New SP + +--- | + source_filename = "wrong-stack-offset-for-rvv-object.ll" + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" + target triple = "riscv64" + + %struct = type { i32 } + + define void @asm_fprintf(%struct %file, ptr %p, ptr %buf, ptr %arrayidx3, ptr %0, ptr %1, ...) #0 { + entry: + %buf1 = alloca [10 x i8], i32 0, align 8 + %arrayidx32 = getelementptr inbounds [10 x i8], ptr %buf, i64 0, i64 1 + br label %while.cond + + while.cond: ; preds = %while.cond, %sw.bb, %entry + %incdec.ptr = getelementptr inbounds i8, ptr undef, i64 1 + %2 = load i8, ptr null, align 1 + %3 = zext i8 0 to i64 + %cond = icmp eq i64 %3, 0 + br i1 %cond, label %sw.bb, label %while.cond + + sw.bb: ; preds = %while.cond + %4 = load i8, ptr null, align 1 + store <2 x i8> zeroinitializer, ptr %0, align 1 + %call = call i32 (ptr, ...) @fprintf(ptr %p) + br label %while.cond + } + + declare i32 @fprintf(ptr, ...) #0 + + attributes #0 = { "target-features"="+m,+v" } + +... +--- +name: asm_fprintf +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +failsVerification: false +tracksDebugUserValues: true +registers: [] +liveins: + - { reg: '$x11', virtual-reg: '' } + - { reg: '$x14', virtual-reg: '' } + - { reg: '$x16', virtual-reg: '' } + - { reg: '$x17', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: true + hasCalls: true + stackProtector: '' + maxCallFrameSize: 0 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: [] + restorePoint: [] +fixedStack: + - { id: 0, type: default, offset: -8, size: 8, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, type: default, offset: -16, size: 8, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, type: default, offset: -16, size: 8, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +stack: + - { id: 0, name: buf1, type: default, offset: 0, size: 1, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8, + stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: -1 + varArgsSaveSize: 16 +body: | + ; CHECK-LABEL: name: asm_fprintf + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x11, $x14, $x16, $x17, $x1, $x8, $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -80 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 80 + ; CHECK-NEXT: frame-setup SD killed $x1, $x2, 56 :: (store (s64) into %stack.2) + ; CHECK-NEXT: frame-setup SD killed $x8, $x2, 48 :: (store (s64) into %stack.3) + ; CHECK-NEXT: frame-setup SD killed $x9, $x2, 40 :: (store (s64) into %stack.4) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -40 + ; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB + ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 + ; CHECK-NEXT: renamable $x8 = COPY $x14 + ; CHECK-NEXT: renamable $x9 = COPY $x11 + ; CHECK-NEXT: $x10 = PseudoReadVLENB + ; CHECK-NEXT: $x10 = ADD $x2, killed $x10 + ; CHECK-NEXT: SD killed renamable $x17, killed $x10, 72 :: (store (s64)) + ; CHECK-NEXT: $x10 = PseudoReadVLENB + ; CHECK-NEXT: $x10 = ADD $x2, killed $x10 + ; CHECK-NEXT: SD killed renamable $x16, killed $x10, 64 :: (store (s64) into %fixed-stack.1, align 16) + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_MF8 undef $v8, 0, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $x10 = ADDI $x2, 32 + ; CHECK-NEXT: VS1R_V killed renamable $v8, killed $x10 :: (store unknown-size into %stack.1, align 8) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.while.cond: + ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $x8, $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BNE $x0, $x0, %bb.1 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.sw.bb: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x8, $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $x10 = ADDI $x2, 32 + ; CHECK-NEXT: renamable $v8 = VL1RE8_V killed $x10 :: (load unknown-size from %stack.1, align 8) + ; CHECK-NEXT: PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2 /* vl */, 3 /* e8 */, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1) + ; CHECK-NEXT: $x10 = COPY renamable $x9 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10 + ; CHECK-NEXT: PseudoBR %bb.1 + bb.0.entry: + successors: %bb.1(0x80000000) + liveins: $x11, $x14, $x16, $x17 + + renamable $x8 = COPY $x14 + renamable $x9 = COPY $x11 + SD killed renamable $x17, %fixed-stack.0, 0 :: (store (s64)) + SD killed renamable $x16, %fixed-stack.1, 0 :: (store (s64) into %fixed-stack.1, align 16) + dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype + renamable $v8 = PseudoVMV_V_I_MF8 undef $v8, 0, 2, 3, 0, implicit $vl, implicit $vtype + VS1R_V killed renamable $v8, %stack.1 :: (store unknown-size into %stack.1, align 8) + + bb.1.while.cond: + successors: %bb.2(0x30000000), %bb.1(0x50000000) + liveins: $x8, $x9 + + BNE $x0, $x0, %bb.1 + PseudoBR %bb.2 + + bb.2.sw.bb: + successors: %bb.1(0x80000000) + liveins: $x8, $x9 + + dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype + renamable $v8 = VL1RE8_V %stack.1 :: (load unknown-size from %stack.1, align 8) + PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1) + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + $x10 = COPY renamable $x9 + PseudoCALL target-flags(riscv-call) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + PseudoBR %bb.1 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir new file mode 100644 index 0000000..e3f2a43 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir @@ -0,0 +1,94 @@ +# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -o - %s \ +# RUN: -start-before=prologepilog | FileCheck %s +# +# These tests check that we are assigning the right stack slot to GPRs and to +# vector registers (VRs). If this test changes, make sure there is no overlap +# between slots for GPRs and VRs. +--- | + define void @foo() #0 { + ; CHECK-LABEL: foo: + ; CHECK: # %bb.0: # %entry + ; CHECK-NEXT: addi sp, sp, -32 + ; CHECK-NEXT: sw s9, 28(sp) # 4-byte Folded Spill + ; CHECK-NEXT: csrr a1, vlenb + ; CHECK-NEXT: slli a1, a1, 1 + ; CHECK-NEXT: sub sp, sp, a1 + ; CHECK-NEXT: sw a0, 8(sp) # 4-byte Folded Spill + ; CHECK-NEXT: addi a0, sp, 16 + ; CHECK-NEXT: vs2r.v v30, (a0) # vscale x 16-byte Folded Spill + ; CHECK-NEXT: csrr a0, vlenb + ; CHECK-NEXT: slli a0, a0, 1 + ; CHECK-NEXT: add sp, sp, a0 + ; CHECK-NEXT: lw s9, 28(sp) # 4-byte Folded Reload + ; CHECK-NEXT: addi sp, sp, 32 + ; CHECK-NEXT: ret + entry: + ret void + } + + define void @rvv_clobbers_callee_save() #0 { + ; CHECK-LABEL: rvv_clobbers_callee_save: + ; CHECK: # %bb.0: # %entry + ; CHECK-NEXT: addi sp, sp, -80 + ; CHECK-NEXT: sw ra, 76(sp) # 4-byte Folded Spill + ; CHECK-NEXT: sw s0, 72(sp) # 4-byte Folded Spill + ; CHECK-NEXT: sw s9, 68(sp) # 4-byte Folded Spill + ; CHECK-NEXT: addi s0, sp, 80 + ; CHECK-NEXT: csrr a1, vlenb + ; CHECK-NEXT: slli a1, a1, 1 + ; CHECK-NEXT: sub sp, sp, a1 + ; CHECK-NEXT: andi sp, sp, -32 + ; CHECK-NEXT: sw a0, 32(sp) # 4-byte Folded Spill + ; CHECK-NEXT: addi a0, sp, 64 + ; CHECK-NEXT: vs2r.v v30, (a0) # vscale x 16-byte Folded Spill + ; CHECK-NEXT: addi sp, s0, -80 + ; CHECK-NEXT: lw ra, 76(sp) # 4-byte Folded Reload + ; CHECK-NEXT: lw s0, 72(sp) # 4-byte Folded Reload + ; CHECK-NEXT: lw s9, 68(sp) # 4-byte Folded Reload + ; CHECK-NEXT: addi sp, sp, 80 + ; CHECK-NEXT: ret + entry: + ret void + } + + attributes #0 = { nounwind } +... +--- +name: foo +alignment: 2 +frameInfo: + maxAlignment: 8 +stack: + - { id: 0, type: spill-slot, size: 4, alignment: 4 } + - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector } +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10, $v30m2 + + $x25 = COPY $x10 + SW renamable $x25, %stack.0, 0 :: (store (s32) into %stack.0) + VS2R_V renamable $v30m2, %stack.1 :: (store () into %stack.1, align 8) + PseudoRET + +... +--- +name: rvv_clobbers_callee_save +alignment: 2 +frameInfo: + maxAlignment: 8 +stack: + - { id: 0, type: spill-slot, size: 4, alignment: 32 } + - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector } +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10, $v30m2 + + $x25 = COPY $x10 + SW renamable $x25, %stack.0, 0 :: (store (s32) into %stack.0) + VS2R_V renamable $v30m2, %stack.1 :: (store () into %stack.1, align 8) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir new file mode 100644 index 0000000..a786915 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir @@ -0,0 +1,51 @@ +# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -o - %s \ +# RUN: -start-before=prologepilog | FileCheck %s +# +# This test checks that we are assigning the right stack slot to GPRs and to +# vector registers (VRs). If this test changes, make sure there is no overlap +# between slots for GPRs and VRs. +--- | + define void @foo() #0 { + ; CHECK-LABEL: foo: + ; CHECK: # %bb.0: # %entry + ; CHECK-NEXT: addi sp, sp, -48 + ; CHECK-NEXT: sd s9, 40(sp) # 8-byte Folded Spill + ; CHECK-NEXT: csrr a1, vlenb + ; CHECK-NEXT: slli a1, a1, 1 + ; CHECK-NEXT: sub sp, sp, a1 + ; CHECK-NEXT: sd a0, 16(sp) # 8-byte Folded Spill + ; CHECK-NEXT: addi a0, sp, 32 + ; CHECK-NEXT: vs2r.v v30, (a0) # vscale x 16-byte Folded Spill + ; CHECK-NEXT: csrr a0, vlenb + ; CHECK-NEXT: slli a0, a0, 1 + ; CHECK-NEXT: add sp, sp, a0 + ; CHECK-NEXT: ld s9, 40(sp) # 8-byte Folded Reload + ; CHECK-NEXT: addi sp, sp, 48 + ; CHECK-NEXT: ret + entry: + ret void + } + + attributes #0 = { nounwind } +... +--- +name: foo +alignment: 2 +tracksRegLiveness: true +frameInfo: + maxAlignment: 8 +stack: + - { id: 0, type: spill-slot, size: 8, alignment: 8 } + - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector } +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10, $v30m2 + + $x25 = COPY $x10 + SD renamable $x25, %stack.0, 0 :: (store (s64) into %stack.0) + VS2R_V renamable $v30m2, %stack.1 :: (store () into %stack.1, align 8) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/xsfmm-insert-vsetvl-TMTK.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/xsfmm-insert-vsetvl-TMTK.mir new file mode 100644 index 0000000..4e554d0 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/xsfmm-insert-vsetvl-TMTK.mir @@ -0,0 +1,195 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc %s -o - -mtriple=riscv64 -mattr=v,xsfmm32a32f -run-pass=liveintervals,riscv-insert-vsetvli \ +# RUN: -verify-machineinstrs | FileCheck %s + +--- | + define void @fooTK() { + ret void + } + + define void @fooTM() { + ret void + } + + define void @TMTKsameBB() { + ret void + } + + define void @TMTKdifferentBB() { + ret void + } + + define void @TMTKsameBBremoved() { + ret void + } + + define void @TMTKButDisableTWiden() { + ret void + } +... +--- +name: fooTK +tracksRegLiveness: true +body: | + bb.0: + liveins: $v8m8, $v16m8, $t0 + ; CHECK-LABEL: name: fooTK + ; CHECK: liveins: $v8m8, $v16m8, $t0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x0 + ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def dead $vtype, implicit $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[PseudoSF_VSETTK]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t0, renamable $v8m8, renamable $v16m8, 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET implicit [[PseudoSF_VSETTK]] + %1:gpr = COPY $x0 + %2:gprnox0 = COPY $x0 + %0:gprnox0 = PseudoSF_VSETTK %1:gpr, 4, 2, implicit-def dead $vtype, implicit $vtype, implicit $vtype + PseudoSF_MM_F_F $t0, killed renamable $v8m8, killed renamable $v16m8, 7, %2:gprnox0, %2:gprnox0, %0:gprnox0, 4, 2, implicit $frm, implicit $vl, implicit $vtype + PseudoRET implicit %0:gprnox0 +... +--- +name: fooTM +tracksRegLiveness: true +body: | + bb.0: + liveins: $v8m8, $v16m8, $t0 + ; CHECK-LABEL: name: fooTM + ; CHECK: liveins: $v8m8, $v16m8, $t0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x0 + ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def dead $vtype, implicit $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[PseudoSF_VSETTM]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[PseudoSF_VSETTM]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t0, renamable $v8m8, renamable $v16m8, 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET implicit [[PseudoSF_VSETTM]] + %1:gpr = COPY $x0 + %2:gprnox0 = COPY $x0 + %0:gprnox0 = PseudoSF_VSETTM %1:gpr, 4, 2, implicit-def dead $vtype, implicit $vtype, implicit $vtype + PseudoSF_MM_F_F $t0, killed renamable $v8m8, killed renamable $v16m8, 7, %0:gprnox0, %0:gprnox0, %2:gprnox0, 4, 2, implicit $frm, implicit $vl, implicit $vtype + PseudoRET implicit %0:gprnox0 +... +--- +name: TMTKsameBB +tracksRegLiveness: true +body: | + bb.0: + liveins: $v8m8, $v16m8, $t0 + ; CHECK-LABEL: name: TMTKsameBB + ; CHECK: liveins: $v8m8, $v16m8, $t0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x0 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t0, $v8m8, $v16m8, 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t0, renamable $v8m8, renamable $v16m8, 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype + %0:gprnox0 = COPY $x0 + %2:gprnox0 = COPY $x0 + PseudoSF_MM_F_F $t0, $v8m8, $v16m8, 7, %2:gprnox0, %2:gprnox0, %0:gprnox0, 4, 2, implicit $frm, implicit $vl, implicit $vtype + dead $x0 = PseudoSF_VSETTK %2:gprnox0, 4, 2, implicit-def $vtype, implicit $vtype + PseudoSF_MM_F_F $t0, killed renamable $v8m8, killed renamable $v16m8, 7, %2:gprnox0, %2:gprnox0, %0:gprnox0, 4, 2, implicit $frm, implicit $vl, implicit $vtype +... +--- +name: TMTKdifferentBB +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: TMTKdifferentBB + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $v8m8, $v16m8, $t0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x0 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t0, $v8m8, $v16m8, 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $v8m8, $v16m8, $t0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t0, renamable $v8m8, renamable $v16m8, 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype + bb.0: + liveins: $v8m8, $v16m8, $t0 + %0:gprnox0 = COPY $x0 + %2:gprnox0 = COPY $x0 + PseudoSF_MM_F_F $t0, $v8m8, $v16m8, 7, %2:gprnox0, %2:gprnox0, %0:gprnox0, 4, 2, implicit $frm, implicit $vl, implicit $vtype + dead $x0 = PseudoSF_VSETTK %2:gprnox0, 4, 2, implicit-def $vtype, implicit $vtype + bb.1: + liveins: $v8m8, $v16m8, $t0 + PseudoSF_MM_F_F $t0, killed renamable $v8m8, killed renamable $v16m8, 7, %2:gprnox0, %2:gprnox0, %0:gprnox0, 4, 2, implicit $frm, implicit $vl, implicit $vtype +... +--- +name: TMTKsameBBremoved +tracksRegLiveness: true +body: | + bb.0: + liveins: $v8m8, $v16m8, $t0 + ; CHECK-LABEL: name: TMTKsameBBremoved + ; CHECK: liveins: $v8m8, $v16m8, $t0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x0 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t0, $v8m8, $v16m8, 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t0, renamable $v8m8, renamable $v16m8, 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype + %0:gprnox0 = COPY $x0 + %2:gprnox0 = COPY $x0 + PseudoSF_MM_F_F $t0, $v8m8, $v16m8, 7, %2:gprnox0, %2:gprnox0, %0:gprnox0, 4, 2, implicit $frm, implicit $vl, implicit $vtype + PseudoSF_MM_F_F $t0, killed renamable $v8m8, killed renamable $v16m8, 7, %2:gprnox0, %2:gprnox0, %0:gprnox0, 4, 2, implicit $frm, implicit $vl, implicit $vtype +... +--- +name: TMTKButDisableTWiden +tracksRegLiveness: true +body: | + bb.0: + liveins: $v8m8, $v16m8, $t0, $x10, $x11 + ; CHECK-LABEL: name: TMTKButDisableTWiden + ; CHECK: liveins: $v8m8, $v16m8, $t0, $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x0 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t0, $v8m8, $v16m8, 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVLE64_V_M1_1:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY3]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[PseudoVLE64_V_M1_1]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t0, renamable $v8m8, renamable $v16m8, 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype + %0:gprnox0 = COPY $x0 + %2:gprnox0 = COPY $x0 + PseudoSF_MM_F_F $t0, $v8m8, $v16m8, 7, %2:gprnox0, %2:gprnox0, %0:gprnox0, 4, 2, implicit $frm, implicit $vl, implicit $vtype + dead $x0 = PseudoSF_VSETTK %2:gprnox0, 4, 2, implicit-def $vtype, implicit $vtype + %3:gpr = COPY $x11 + %4:gpr = COPY $x10 + %5:vr = PseudoVLE64_V_M1 undef $noreg, %3, 2, 6, 0 + %6:vr = PseudoVLE64_V_M1 undef $noreg, %4, 2, 6, 0 + %7:vr = PseudoVADD_VV_M1 undef $noreg, killed %5, killed %6, 2, 6, 0 + PseudoSF_MM_F_F $t0, killed renamable $v8m8, killed renamable $v16m8, 7, %2:gprnox0, %2:gprnox0, %0:gprnox0, 4, 2, implicit $frm, implicit $vl, implicit $vtype +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir new file mode 100644 index 0000000..a44a934 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir @@ -0,0 +1,267 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple riscv64 -mattr=+v -verify-machineinstrs -run-pass=postrapseudos %s -o - | FileCheck %s + +... +--- +name: copy_zvlsseg_N2 +body: | + bb.0: + ; CHECK-LABEL: name: copy_zvlsseg_N2 + ; CHECK: $v2m2 = VMV2R_V $v4m2 + ; CHECK-NEXT: $v3 = VMV1R_V $v4 + ; CHECK-NEXT: $v4 = VMV1R_V $v5 + ; CHECK-NEXT: $v6 = VMV1R_V $v5 + ; CHECK-NEXT: $v5 = VMV1R_V $v4 + ; CHECK-NEXT: $v6m2 = VMV2R_V $v4m2 + ; CHECK-NEXT: $v0m4 = VMV4R_V $v4m4 + ; CHECK-NEXT: $v2m2 = VMV2R_V $v4m2 + ; CHECK-NEXT: $v4m2 = VMV2R_V $v6m2 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v6m2 + ; CHECK-NEXT: $v6m2 = VMV2R_V $v4m2 + ; CHECK-NEXT: $v8m4 = VMV4R_V $v4m4 + ; CHECK-NEXT: $v0m8 = VMV8R_V $v8m8 + ; CHECK-NEXT: $v4m4 = VMV4R_V $v8m4 + ; CHECK-NEXT: $v8m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v12m4 = VMV4R_V $v8m4 + ; CHECK-NEXT: $v16m8 = VMV8R_V $v8m8 + $v2_v3 = COPY $v4_v5 + $v3_v4 = COPY $v4_v5 + $v5_v6 = COPY $v4_v5 + $v6_v7 = COPY $v4_v5 + + $v0m2_v2m2 = COPY $v4m2_v6m2 + $v2m2_v4m2 = COPY $v4m2_v6m2 + $v6m2_v8m2 = COPY $v4m2_v6m2 + $v8m2_v10m2 = COPY $v4m2_v6m2 + + $v0m4_v4m4 = COPY $v8m4_v12m4 + $v4m4_v8m4 = COPY $v8m4_v12m4 + $v12m4_v16m4 = COPY $v8m4_v12m4 + $v16m4_v20m4 = COPY $v8m4_v12m4 +... +--- +name: copy_zvlsseg_N3 +body: | + bb.0: + ; CHECK-LABEL: name: copy_zvlsseg_N3 + ; CHECK: $v2 = VMV1R_V $v5 + ; CHECK-NEXT: $v3 = VMV1R_V $v6 + ; CHECK-NEXT: $v4 = VMV1R_V $v7 + ; CHECK-NEXT: $v3 = VMV1R_V $v5 + ; CHECK-NEXT: $v4m2 = VMV2R_V $v6m2 + ; CHECK-NEXT: $v4 = VMV1R_V $v5 + ; CHECK-NEXT: $v5 = VMV1R_V $v6 + ; CHECK-NEXT: $v6 = VMV1R_V $v7 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v6m2 + ; CHECK-NEXT: $v7 = VMV1R_V $v5 + ; CHECK-NEXT: $v9 = VMV1R_V $v5 + ; CHECK-NEXT: $v10m2 = VMV2R_V $v6m2 + ; CHECK-NEXT: $v0m2 = VMV2R_V $v6m2 + ; CHECK-NEXT: $v2m2 = VMV2R_V $v8m2 + ; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v2m2 = VMV2R_V $v6m2 + ; CHECK-NEXT: $v4m4 = VMV4R_V $v8m4 + ; CHECK-NEXT: $v12m4 = VMV4R_V $v8m4 + ; CHECK-NEXT: $v10m2 = VMV2R_V $v6m2 + ; CHECK-NEXT: $v12m2 = VMV2R_V $v6m2 + ; CHECK-NEXT: $v14m2 = VMV2R_V $v8m2 + ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m2 + $v2_v3_v4 = COPY $v5_v6_v7 + $v3_v4_v5 = COPY $v5_v6_v7 + $v4_v5_v6 = COPY $v5_v6_v7 + $v7_v8_v9 = COPY $v5_v6_v7 + $v9_v10_v11 = COPY $v5_v6_v7 + + $v0m2_v2m2_v4m2 = COPY $v6m2_v8m2_v10m2 + $v2m2_v4m2_v6m2 = COPY $v6m2_v8m2_v10m2 + $v10m2_v12m2_v14m2 = COPY $v6m2_v8m2_v10m2 + $v12m2_v14m2_v16m2 = COPY $v6m2_v8m2_v10m2 +... +--- +name: copy_zvlsseg_N4 +body: | + bb.0: + ; CHECK-LABEL: name: copy_zvlsseg_N4 + ; CHECK: $v6m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v7 = VMV1R_V $v10 + ; CHECK-NEXT: $v8 = VMV1R_V $v11 + ; CHECK-NEXT: $v9 = VMV1R_V $v12 + ; CHECK-NEXT: $v10 = VMV1R_V $v13 + ; CHECK-NEXT: $v16 = VMV1R_V $v13 + ; CHECK-NEXT: $v15 = VMV1R_V $v12 + ; CHECK-NEXT: $v14 = VMV1R_V $v11 + ; CHECK-NEXT: $v13 = VMV1R_V $v10 + ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v16m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v2m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v4m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v16m2 + ; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v14m2 + ; CHECK-NEXT: $v10m2 = VMV2R_V $v16m2 + ; CHECK-NEXT: $v22m2 = VMV2R_V $v16m2 + ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2 + ; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v18m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v20m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v24m2 = VMV2R_V $v16m2 + $v6_v7_v8_v9 = COPY $v10_v11_v12_v13 + $v7_v8_v9_v10 = COPY $v10_v11_v12_v13 + $v13_v14_v15_v16 = COPY $v10_v11_v12_v13 + $v14_v15_v16_v17 = COPY $v10_v11_v12_v13 + + $v2m2_v4m2_v6m2_v8m2 = COPY $v10m2_v12m2_v14m2_v16m2 + $v4m2_v6m2_v8m2_v10m2 = COPY $v10m2_v12m2_v14m2_v16m2 + $v16m2_v18m2_v20m2_v22m2 = COPY $v10m2_v12m2_v14m2_v16m2 + $v18m2_v20m2_v22m2_v24m2 = COPY $v10m2_v12m2_v14m2_v16m2 +... +--- +name: copy_zvlsseg_N5 +body: | + bb.0: + ; CHECK-LABEL: name: copy_zvlsseg_N5 + ; CHECK: $v5 = VMV1R_V $v10 + ; CHECK-NEXT: $v6 = VMV1R_V $v11 + ; CHECK-NEXT: $v7 = VMV1R_V $v12 + ; CHECK-NEXT: $v8 = VMV1R_V $v13 + ; CHECK-NEXT: $v9 = VMV1R_V $v14 + ; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v10 = VMV1R_V $v14 + ; CHECK-NEXT: $v18 = VMV1R_V $v14 + ; CHECK-NEXT: $v16m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v15 = VMV1R_V $v10 + ; CHECK-NEXT: $v16 = VMV1R_V $v11 + ; CHECK-NEXT: $v17 = VMV1R_V $v12 + ; CHECK-NEXT: $v18 = VMV1R_V $v13 + ; CHECK-NEXT: $v19 = VMV1R_V $v14 + ; CHECK-NEXT: $v7 = VMV1R_V $v11 + ; CHECK-NEXT: $v8m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v15 = VMV1R_V $v11 + $v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14 + $v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14 + $v14_v15_v16_v17_v18 = COPY $v10_v11_v12_v13_v14 + $v15_v16_v17_v18_v19 = COPY $v10_v11_v12_v13_v14 + $v7_v8_v9_v10_v11 = COPY $v11_v12_v13_v14_v15 + $v15_v16_v17_v18_v19 = COPY $v11_v12_v13_v14_v15 +... +--- +name: copy_zvlsseg_N6 +body: | + bb.0: + ; CHECK-LABEL: name: copy_zvlsseg_N6 + ; CHECK: $v4m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v14m2 + ; CHECK-NEXT: $v5 = VMV1R_V $v10 + ; CHECK-NEXT: $v6 = VMV1R_V $v11 + ; CHECK-NEXT: $v7 = VMV1R_V $v12 + ; CHECK-NEXT: $v8 = VMV1R_V $v13 + ; CHECK-NEXT: $v9 = VMV1R_V $v14 + ; CHECK-NEXT: $v10 = VMV1R_V $v15 + ; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v8m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v20 = VMV1R_V $v15 + ; CHECK-NEXT: $v19 = VMV1R_V $v14 + ; CHECK-NEXT: $v18 = VMV1R_V $v13 + ; CHECK-NEXT: $v17 = VMV1R_V $v12 + ; CHECK-NEXT: $v16 = VMV1R_V $v11 + ; CHECK-NEXT: $v15 = VMV1R_V $v10 + ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2 + $v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15 + $v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15 + $v6_v7_v8_v9_v10_v11 = COPY $v10_v11_v12_v13_v14_v15 + $v14_v15_v16_v17_v18_v19 = COPY $v10_v11_v12_v13_v14_v15 + $v15_v16_v17_v18_v19_v20 = COPY $v10_v11_v12_v13_v14_v15 + $v16_v17_v18_v19_v20_v21 = COPY $v10_v11_v12_v13_v14_v15 +... +--- +name: copy_zvlsseg_N7 +body: | + bb.0: + ; CHECK-LABEL: name: copy_zvlsseg_N7 + ; CHECK: $v3 = VMV1R_V $v10 + ; CHECK-NEXT: $v4 = VMV1R_V $v11 + ; CHECK-NEXT: $v5 = VMV1R_V $v12 + ; CHECK-NEXT: $v6 = VMV1R_V $v13 + ; CHECK-NEXT: $v7 = VMV1R_V $v14 + ; CHECK-NEXT: $v8 = VMV1R_V $v15 + ; CHECK-NEXT: $v9 = VMV1R_V $v16 + ; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v14m2 + ; CHECK-NEXT: $v10 = VMV1R_V $v16 + ; CHECK-NEXT: $v20 = VMV1R_V $v16 + ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v22 = VMV1R_V $v16 + ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2 + ; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v17 = VMV1R_V $v10 + ; CHECK-NEXT: $v18 = VMV1R_V $v11 + ; CHECK-NEXT: $v19 = VMV1R_V $v12 + ; CHECK-NEXT: $v20 = VMV1R_V $v13 + ; CHECK-NEXT: $v21 = VMV1R_V $v14 + ; CHECK-NEXT: $v22 = VMV1R_V $v15 + ; CHECK-NEXT: $v23 = VMV1R_V $v16 + ; CHECK-NEXT: $v22 = VMV1R_V $v21 + ; CHECK-NEXT: $v21 = VMV1R_V $v20 + ; CHECK-NEXT: $v20 = VMV1R_V $v19 + ; CHECK-NEXT: $v19 = VMV1R_V $v18 + ; CHECK-NEXT: $v18 = VMV1R_V $v17 + ; CHECK-NEXT: $v17 = VMV1R_V $v16 + ; CHECK-NEXT: $v16 = VMV1R_V $v15 + $v3_v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15_v16 + $v4_v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15_v16 + $v14_v15_v16_v17_v18_v19_v20 = COPY $v10_v11_v12_v13_v14_v15_v16 + $v16_v17_v18_v19_v20_v21_v22 = COPY $v10_v11_v12_v13_v14_v15_v16 + $v17_v18_v19_v20_v21_v22_v23 = COPY $v10_v11_v12_v13_v14_v15_v16 + $v16_v17_v18_v19_v20_v21_v22 = COPY $v15_v16_v17_v18_v19_v20_v21 +... +--- +name: copy_zvlsseg_N8 +body: | + bb.0: + ; CHECK-LABEL: name: copy_zvlsseg_N8 + ; CHECK: $v2m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v4m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v16m2 + ; CHECK-NEXT: $v3 = VMV1R_V $v10 + ; CHECK-NEXT: $v4 = VMV1R_V $v11 + ; CHECK-NEXT: $v5 = VMV1R_V $v12 + ; CHECK-NEXT: $v6 = VMV1R_V $v13 + ; CHECK-NEXT: $v7 = VMV1R_V $v14 + ; CHECK-NEXT: $v8 = VMV1R_V $v15 + ; CHECK-NEXT: $v9 = VMV1R_V $v16 + ; CHECK-NEXT: $v10 = VMV1R_V $v17 + ; CHECK-NEXT: $v24 = VMV1R_V $v17 + ; CHECK-NEXT: $v23 = VMV1R_V $v16 + ; CHECK-NEXT: $v22 = VMV1R_V $v15 + ; CHECK-NEXT: $v21 = VMV1R_V $v14 + ; CHECK-NEXT: $v20 = VMV1R_V $v13 + ; CHECK-NEXT: $v19 = VMV1R_V $v12 + ; CHECK-NEXT: $v18 = VMV1R_V $v11 + ; CHECK-NEXT: $v17 = VMV1R_V $v10 + ; CHECK-NEXT: $v18m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v20m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v24m2 = VMV2R_V $v16m2 + ; CHECK-NEXT: $v8m8 = VMV8R_V $v0m8 + ; CHECK-NEXT: $v0m8 = VMV8R_V $v8m8 + $v2_v3_v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15_v16_v17 + $v3_v4_v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15_v16_v17 + $v17_v18_v19_v20_v21_v22_v23_v24 = COPY $v10_v11_v12_v13_v14_v15_v16_v17 + $v18_v19_v20_v21_v22_v23_v24_v25 = COPY $v10_v11_v12_v13_v14_v15_v16_v17 + $v8_v9_v10_v11_v12_v13_v14_v15 = COPY $v0_v1_v2_v3_v4_v5_v6_v7 + $v0_v1_v2_v3_v4_v5_v6_v7 = COPY $v8_v9_v10_v11_v12_v13_v14_v15 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir new file mode 100644 index 0000000..cc9cdb4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir @@ -0,0 +1,117 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v -start-before=greedy -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s + +--- | + define void @zvlsseg_spill_0(ptr %base, i64 %vl) { + ret void + } + define void @zvlsseg_spill_1(ptr %base, i64 %vl) { + ret void + } +... +--- +name: zvlsseg_spill_0 +tracksRegLiveness: true +stack: + - { id: 0, offset: 0, size: 64, alignment: 8, stack-id: scalable-vector } +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: zvlsseg_spill_0 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB + ; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 3 + ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 undef $v0_v1_v2_v3_v4_v5_v6, renamable $x10, $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $x11 = ADDI $x2, 16 + ; CHECK-NEXT: VS4R_V $v0m4, $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store () into %stack.0, align 8) + ; CHECK-NEXT: $x12 = PseudoReadVLENB + ; CHECK-NEXT: $x12 = SLLI killed $x12, 2 + ; CHECK-NEXT: $x11 = ADD killed $x11, $x12 + ; CHECK-NEXT: VS2R_V $v4m2, $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store () into %stack.0, align 8) + ; CHECK-NEXT: $x12 = SRLI killed $x12, 1 + ; CHECK-NEXT: $x11 = ADD killed $x11, killed $x12 + ; CHECK-NEXT: VS1R_V $v6, killed $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store () into %stack.0) + ; CHECK-NEXT: $x11 = ADDI $x2, 16 + ; CHECK-NEXT: $v7 = VL1RE8_V $x11 :: (load () from %stack.0) + ; CHECK-NEXT: $x12 = PseudoReadVLENB + ; CHECK-NEXT: $x11 = ADD killed $x11, $x12 + ; CHECK-NEXT: $v8m4 = VL4RE8_V $x11 :: (load () from %stack.0, align 8) + ; CHECK-NEXT: $x12 = SLLI killed $x12, 2 + ; CHECK-NEXT: $x11 = ADD killed $x11, killed $x12 + ; CHECK-NEXT: $v12m2 = VL2RE8_V killed $x11 :: (load () from %stack.0, align 8) + ; CHECK-NEXT: VS1R_V killed $v8, killed renamable $x10 + ; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB + ; CHECK-NEXT: $x10 = frame-destroy SLLI killed $x10, 3 + ; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 16 + ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gprnox0 = COPY $x11 + $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 undef $v0_v1_v2_v3_v4_v5_v6, %0, %1, 6, 0 + PseudoVSPILL7_M1 killed renamable $v0_v1_v2_v3_v4_v5_v6, %stack.0 :: (store () into %stack.0, align 8) + renamable $v7_v8_v9_v10_v11_v12_v13 = PseudoVRELOAD7_M1 %stack.0 :: (load () from %stack.0, align 8) + VS1R_V killed $v8, %0:gpr + PseudoRET +... + +--- +name: zvlsseg_spill_1 +tracksRegLiveness: true +stack: + - { id: 0, offset: 0, size: 64, alignment: 8, stack-id: scalable-vector } +body: | + bb.0: + liveins: $x10, $x11 + ; CHECK-LABEL: name: zvlsseg_spill_1 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB + ; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 3 + ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $v1_v2_v3_v4_v5_v6_v7 = PseudoVLSEG7E64_V_M1 undef $v1_v2_v3_v4_v5_v6_v7, renamable $x10, $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $x11 = ADDI $x2, 16 + ; CHECK-NEXT: VS1R_V $v1, $x11, implicit $v1_v2_v3_v4_v5_v6_v7 :: (store () into %stack.0) + ; CHECK-NEXT: $x12 = PseudoReadVLENB + ; CHECK-NEXT: $x11 = ADD killed $x11, $x12 + ; CHECK-NEXT: VS2R_V $v2m2, $x11, implicit $v1_v2_v3_v4_v5_v6_v7 :: (store () into %stack.0, align 8) + ; CHECK-NEXT: $x12 = SLLI killed $x12, 1 + ; CHECK-NEXT: $x11 = ADD killed $x11, killed $x12 + ; CHECK-NEXT: VS4R_V $v4m4, killed $x11, implicit $v1_v2_v3_v4_v5_v6_v7 :: (store () into %stack.0, align 8) + ; CHECK-NEXT: $x11 = ADDI $x2, 16 + ; CHECK-NEXT: $v10m2 = VL2RE8_V $x11 :: (load () from %stack.0, align 8) + ; CHECK-NEXT: $x12 = PseudoReadVLENB + ; CHECK-NEXT: $x12 = SLLI killed $x12, 1 + ; CHECK-NEXT: $x11 = ADD killed $x11, $x12 + ; CHECK-NEXT: $v12m4 = VL4RE8_V $x11 :: (load () from %stack.0, align 8) + ; CHECK-NEXT: $x12 = SLLI killed $x12, 1 + ; CHECK-NEXT: $x11 = ADD killed $x11, killed $x12 + ; CHECK-NEXT: $v16 = VL1RE8_V killed $x11 :: (load () from %stack.0) + ; CHECK-NEXT: VS1R_V killed $v10, killed renamable $x10 + ; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB + ; CHECK-NEXT: $x10 = frame-destroy SLLI killed $x10, 3 + ; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 16 + ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gprnox0 = COPY $x11 + $v1_v2_v3_v4_v5_v6_v7 = PseudoVLSEG7E64_V_M1 undef $v1_v2_v3_v4_v5_v6_v7, %0, %1, 6, 0 + PseudoVSPILL7_M1 killed renamable $v1_v2_v3_v4_v5_v6_v7, %stack.0 :: (store () into %stack.0, align 8) + renamable $v10_v11_v12_v13_v14_v15_v16 = PseudoVRELOAD7_M1 %stack.0 :: (load () from %stack.0, align 8) + VS1R_V killed $v10, %0:gpr + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir new file mode 100644 index 0000000..269ba1f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir @@ -0,0 +1,34 @@ +# RUN: not --crash llc -mtriple=riscv32 -mattr=+experimental-y -run-pass machineverifier %s -o - 2>&1 \ +# RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-32 --implicit-check-not="Bad machine code" +# RUN: not --crash llc -mtriple=riscv64 -mattr=+experimental-y -run-pass machineverifier %s -o - 2>&1 \ +# RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-64 --implicit-check-not="Bad machine code" + +# CHECK: *** Bad machine code: Invalid immediate *** +# CHECK-NEXT: - function:{{ +}}verify_all_invalid +# CHECK-NEXT: - basic block: {{%bb\.[0-9]+ .*}} +# CHECK-NEXT: - instruction: $x10_y = YBNDSWI $x10_y, 0 +# CHECK-EMPTY: +# CHECK: *** Bad machine code: Invalid immediate *** +# CHECK-NEXT: - function:{{ +}}verify_all_invalid +# CHECK-NEXT: - basic block: {{%bb\.[0-9]+ .*}} +# CHECK-NEXT: - instruction: $x10 = SRLIY $x10_y, 31 +# CHECK-64-EMPTY: +# CHECK-64-NEXT: *** Bad machine code: Invalid immediate *** +# CHECK-64-NEXT: - function:{{ +}}verify_all_invalid +# CHECK-64-NEXT: - basic block: {{%bb\.[0-9]+ .*}} +# CHECK-64-NEXT: - instruction: $x10 = SRLIY $x10_y, 32 +# CHECK-32-EMPTY: +# CHECK-32-NEXT: *** Bad machine code: Invalid immediate *** +# CHECK-32-NEXT: - function:{{ +}}verify_all_invalid +# CHECK-32-NEXT: - basic block: {{%bb\.[0-9]+ .*}} +# CHECK-32-NEXT: - instruction: $x10 = SRLIY $x10_y, 64 + +--- +name: verify_all_invalid +body: | + bb.0: + $x10_y = YBNDSWI $x10_y, 0 + $x10 = SRLIY $x10_y, 31 + $x10 = SRLIY $x10_y, 32 + $x10 = SRLIY $x10_y, 64 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir new file mode 100644 index 0000000..030dfcb --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir @@ -0,0 +1,212 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \ +# RUN: | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \ +# RUN: | FileCheck -check-prefix=RV64I %s +# RUN: llc -mtriple=riscv32 -passes=finalize-isel -simplify-mir -o - %s \ +# RUN: | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -passes=finalize-isel -simplify-mir -o - %s \ +# RUN: | FileCheck -check-prefix=RV64I %s + +# Provide dummy definitions of functions and just enough metadata to create a +# DBG_VALUE. +--- | + define void @cmov_interleaved_bad() { + ret void + } + define void @cmov_interleaved_debug_value() { + ret void + } +... +--- +# Here we have a sequence of select instructions with a non-select instruction +# in the middle. Because the non-select depends on the result of a previous +# select, we cannot optimize the sequence to share control-flow. +name: cmov_interleaved_bad +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } + - { id: 6, class: gpr } + - { id: 7, class: gpr } + - { id: 8, class: gpr } + - { id: 9, class: gpr } + - { id: 10, class: gpr } +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } + - { reg: '$x12', virtual-reg: '%2' } + - { reg: '$x13', virtual-reg: '%3' } +body: | + bb.0: + liveins: $x10, $x11, $x12, $x13 + + ; RV32I-LABEL: name: cmov_interleaved_bad + ; RV32I: successors: %bb.1, %bb.2 + ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 + ; RV32I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: .1: + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: .2: + ; RV32I-NEXT: successors: %bb.3, %bb.4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 + ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: .3: + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: .4: + ; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3 + ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] + ; RV32I-NEXT: $x10 = COPY [[ADD]] + ; RV32I-NEXT: PseudoRET implicit $x10 + ; RV64I-LABEL: name: cmov_interleaved_bad + ; RV64I: successors: %bb.1, %bb.2 + ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 + ; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: .1: + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: .2: + ; RV64I-NEXT: successors: %bb.3, %bb.4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 + ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 + ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: .3: + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: .4: + ; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3 + ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] + ; RV64I-NEXT: $x10 = COPY [[ADD]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %3:gpr = COPY $x13 + %2:gpr = COPY $x12 + %1:gpr = COPY $x11 + %0:gpr = COPY $x10 + %5:gpr = ANDI %0, 1 + %6:gpr = COPY $x0 + %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2 + %8:gpr = ADDI %7, 1 + %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %3, %2 + %10:gpr = ADD %7, killed %9 + $x10 = COPY %10 + PseudoRET implicit $x10 + +... +--- +# Demonstrate that debug info associated with selects is correctly moved to +# the tail basic block, while debug info associated with non-selects is left +# in the head basic block. +name: cmov_interleaved_debug_value +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } + - { id: 6, class: gpr } + - { id: 7, class: gpr } + - { id: 8, class: gpr } + - { id: 9, class: gpr } + - { id: 10, class: gpr } +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } + - { reg: '$x12', virtual-reg: '%2' } + - { reg: '$x13', virtual-reg: '%3' } +body: | + bb.0: + liveins: $x10, $x11, $x12, $x13 + + ; RV32I-LABEL: name: cmov_interleaved_debug_value + ; RV32I: successors: %bb.1, %bb.2 + ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 + ; RV32I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1 + ; RV32I-NEXT: DBG_VALUE [[ADDI]], $noreg + ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: .1: + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: .2: + ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 + ; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 + ; RV32I-NEXT: DBG_VALUE [[PHI]], $noreg + ; RV32I-NEXT: DBG_VALUE [[PHI1]], $noreg + ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] + ; RV32I-NEXT: $x10 = COPY [[ADD]] + ; RV32I-NEXT: PseudoRET implicit $x10 + ; RV64I-LABEL: name: cmov_interleaved_debug_value + ; RV64I: successors: %bb.1, %bb.2 + ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 + ; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1 + ; RV64I-NEXT: DBG_VALUE [[ADDI]], $noreg + ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: .1: + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: .2: + ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 + ; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 + ; RV64I-NEXT: DBG_VALUE [[PHI]], $noreg + ; RV64I-NEXT: DBG_VALUE [[PHI1]], $noreg + ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] + ; RV64I-NEXT: $x10 = COPY [[ADD]] + ; RV64I-NEXT: PseudoRET implicit $x10 + %3:gpr = COPY $x13 + %2:gpr = COPY $x12 + %1:gpr = COPY $x11 + %0:gpr = COPY $x10 + %5:gpr = ANDI %0, 1 + %6:gpr = COPY $x0 + %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2 + DBG_VALUE %7, $noreg + %8:gpr = ADDI %0, 1 + DBG_VALUE %8, $noreg + %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %3, %2 + DBG_VALUE %9, $noreg + %10:gpr = ADD %7, killed %9 + $x10 = COPY %10 + PseudoRET implicit $x10 + +... +--- diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir new file mode 100644 index 0000000..f247c5f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/sextw-removal-debug.mir @@ -0,0 +1,59 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc %s -mtriple=riscv64 -run-pass=riscv-opt-w-instrs -o - | FileCheck %s + +--- | + define void @foo(i32 signext %a, i32 signext %b, ptr %c) !dbg !5 { + entry: + %add = add nsw i32 %b, %a, !dbg !11 + tail call void @llvm.dbg.value(metadata i32 %add, metadata !9, metadata !DIExpression()), !dbg !11 + store i32 %add, ptr %c, align 4, !dbg !12 + ret void, !dbg !13 + } + + + !llvm.dbg.cu = !{!0} + !llvm.debugify = !{!2, !3} + !llvm.module.flags = !{!4} + + !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) + !1 = !DIFile(filename: "test.ll", directory: "/") + !2 = !{i32 3} + !3 = !{i32 1} + !4 = !{i32 2, !"Debug Info Version", i32 3} + !5 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) + !6 = !DISubroutineType(types: !7) + !7 = !{} + !8 = !{!9} + !9 = !DILocalVariable(name: "1", scope: !5, file: !1, line: 1, type: !10) + !10 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned) + !11 = !DILocation(line: 1, column: 1, scope: !5) + !12 = !DILocation(line: 2, column: 1, scope: !5) + !13 = !DILocation(line: 3, column: 1, scope: !5) + +... +--- +name: foo +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: foo + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY2]], debug-location !11 + ; CHECK-NEXT: DBG_VALUE [[ADD]], $noreg, !9, !DIExpression(), debug-location !11 + ; CHECK-NEXT: SW killed [[ADD]], [[COPY]], 0, debug-location !12 :: (store (s32) into %ir.c) + ; CHECK-NEXT: PseudoRET debug-location !13 + %2:gpr = COPY $x12 + %1:gpr = COPY $x11 + %0:gpr = COPY $x10 + %3:gpr = ADDW %1, %0, debug-location !11 + DBG_VALUE %3, $noreg, !9, !DIExpression(), debug-location !11 + SW killed %3, %2, 0, debug-location !12 :: (store (s32) into %ir.c) + PseudoRET debug-location !13 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir new file mode 100644 index 0000000..e3cebbf --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir @@ -0,0 +1,57 @@ +# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -run-pass=machine-scheduler \ +# RUN: -debug-only=machine-scheduler -misched-dump-schedule-trace \ +# RUN: -misched-prera-direction=topdown -o - %s 2>&1 | FileCheck %s +# REQUIRES: asserts + +# The purpose of this test is to show that the VADD instructions are issued so +# that the SiFive7VA is saturated. +--- +name: add_m2 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8m2, $v10m2, $v12m2, $v14m2, $x10 + + %4:gprnox0 = COPY $x10 + %3:vrm2 = COPY $v14m2 + %2:vrm2 = COPY $v12m2 + %1:vrm2 = COPY $v10m2 + %0:vrm2 = COPY $v8m2 + dead $x0 = PseudoVSETVLI %4, 217 /* e64, m2, ta, ma */, implicit-def $vl, implicit-def $vtype + %5:vrm2 = PseudoVADD_VV_M2 undef %5, %0, %1, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + %6:vrm2 = PseudoVADD_VV_M2 undef %6, %3, %2, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + %7:vrm2 = PseudoVADD_VV_M2 undef %7, %5, %6, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + $v8m2 = COPY %7 + PseudoRET implicit $v8m2 + +# CHECK: *** Final schedule for %bb.0 *** +# CHECK-NEXT: * Schedule table (TopDown): +# CHECK-NEXT: i: issue +# CHECK-NEXT: x: resource booked +# CHECK-NEXT: Cycle | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | +# CHECK-NEXT: SU(0) | i | | | | | | | | | | | | | | | | | +# CHECK-NEXT: SiFive7PipeAB | x | | | | | | | | | | | | | | | | | +# CHECK-NEXT: SU(1) | i | | | | | | | | | | | | | | | | | +# CHECK-NEXT: SiFive7PipeAB | x | | | | | | | | | | | | | | | | | +# CHECK-NEXT: SU(2) | | i | | | | | | | | | | | | | | | | +# CHECK-NEXT: SiFive7PipeAB | | x | | | | | | | | | | | | | | | | +# CHECK-NEXT: SU(3) | | i | | | | | | | | | | | | | | | | +# CHECK-NEXT: SiFive7PipeAB | | x | | | | | | | | | | | | | | | | +# CHECK-NEXT: SU(4) | | | i | | | | | | | | | | | | | | | +# CHECK-NEXT: SiFive7PipeAB | | | x | | | | | | | | | | | | | | | +# CHECK-NEXT: SU(5) | | | | i | | | | | | | | | | | | | | +# CHECK-NEXT: SiFive7PipeA | | | | x | | | | | | | | | | | | | | +# CHECK-NEXT: SiFive7PipeAB | | | | x | | | | | | | | | | | | | | +# CHECK-NEXT: SU(7) | | | | | i | | | | | | | | | | | | | +# CHECK-NEXT: SiFive7VCQ | | | | | x | | | | | | | | | | | | | +# CHECK-NEXT: SiFive7VA1 | | | | | | x | x | x | x | | | | | | | | | +# CHECK-NEXT: SU(6) | | | | | | | | | i | | | | | | | | | +# CHECK-NEXT: SiFive7VCQ | | | | | | | | | x | | | | | | | | | +# CHECK-NEXT: SiFive7VA1 | | | | | | | | | | x | x | x | x | | | | | +# CHECK-NEXT: SU(8) | | | | | | | | | | | | | i | | | | | +# CHECK-NEXT: SiFive7VCQ | | | | | | | | | | | | | x | | | | | +# CHECK-NEXT: SiFive7VA1 | | | | | | | | | | | | | | x | x | x | x | +# CHECK-NEXT: SU(9) | | | | | | | | | | | | | | | | | i | +# CHECK-NEXT: SiFive7PipeAB | | | | | | | | | | | | | | | | | x | + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/sink-and-fold-crash.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/sink-and-fold-crash.mir new file mode 100644 index 0000000..a14c5ce --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/sink-and-fold-crash.mir @@ -0,0 +1,39 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -mtriple=riscv64 -run-pass=machine-sink -o - | FileCheck %s + +--- +name: main +tracksRegLiveness: true +registers: + - { id: 0, class: fpr32 } + - { id: 1, class: fpr32 } + - { id: 2, class: gpr } + - { id: 3, class: gpr } +liveins: + - { reg: '$f10_f', virtual-reg: '%0' } + - { reg: '$f11_f', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $f10_f, $f11_f + + ; CHECK-LABEL: name: main + ; CHECK: liveins: $f10_f, $f11_f + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f11_f + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f + ; CHECK-NEXT: [[ReadFFLAGS:%[0-9]+]]:gpr = ReadFFLAGS implicit $fflags + ; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = nofpexcept FLE_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: WriteFFLAGS killed [[ReadFFLAGS]], implicit-def $fflags + ; CHECK-NEXT: $x0 = nofpexcept FEQ_S [[COPY1]], [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[FLE_S]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:fpr32 = COPY $f11_f + %0:fpr32 = COPY $f10_f + %3:gpr = ReadFFLAGS implicit $fflags + %2:gpr = nofpexcept FLE_S %0, %1 + WriteFFLAGS killed %3, implicit-def $fflags + $x0 = nofpexcept FEQ_S %0, %1 + $x10 = COPY %2 + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/spacemitx60-sched-copy.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/spacemitx60-sched-copy.mir new file mode 100644 index 0000000..9aa4a87 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/spacemitx60-sched-copy.mir @@ -0,0 +1,60 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=riscv64 -mcpu=spacemit-x60 -run-pass=machine-scheduler %s -o - | FileCheck %s + +# The purpose of this test is to make sure COPYs from physical vector register stay at the top +# of the function in order to reduce the physical register's live range. + +--- +name: vector-copy-schedule +tracksRegLiveness: true +noPhis: true +body: | + bb.0: + liveins: $x10, $v0, $v8m8, $v16m8 + + ; CHECK-LABEL: name: vector-copy-schedule + ; CHECK: liveins: $x10, $v0, $v8m8, $v16m8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8nov0 = COPY $v16m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrm8nov0 = COPY $v8m8 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v0 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, 64 + ; CHECK-NEXT: $v0 = COPY [[COPY2]] + ; CHECK-NEXT: [[PseudoVCPOP_M_B2_:%[0-9]+]]:gprnox0 = PseudoVCPOP_M_B2 [[COPY2]], [[ADDI]] /* vl */, 0 /* e8 */ + ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVIOTA_M_M8 undef %5, [[COPY2]], [[ADDI]] /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE16_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE16_V_M8 undef [[PseudoVLE16_V_M8_]], [[COPY3]], [[PseudoVCPOP_M_B2_]] /* vl */, 4 /* e16 */, 2 /* tu, ma */ + ; CHECK-NEXT: early-clobber [[COPY1]]:vrm8nov0 = PseudoVRGATHER_VV_M8_E16_MASK [[COPY1]], [[PseudoVLE16_V_M8_]], %5, $v0, [[ADDI]] /* vl */, 4 /* e16 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVSLIDEDOWN_VI_M1_:%[0-9]+]]:vr = PseudoVSLIDEDOWN_VI_M1 undef [[PseudoVSLIDEDOWN_VI_M1_]], [[COPY2]], 8, 8 /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVCPOP_M_B2_1:%[0-9]+]]:gprnox0 = PseudoVCPOP_M_B2 [[PseudoVSLIDEDOWN_VI_M1_]], [[ADDI]] /* vl */, 0 /* e8 */ + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoVCPOP_M_B2_]], 1 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY3]], [[SLLI]] + ; CHECK-NEXT: [[PseudoVLE16_V_M8_1:%[0-9]+]]:vrm8 = PseudoVLE16_V_M8 undef [[PseudoVLE16_V_M8_1]], [[ADD]], [[PseudoVCPOP_M_B2_1]] /* vl */, 4 /* e16 */, 2 /* tu, ma */ + ; CHECK-NEXT: early-clobber %13:vrm8 = PseudoVIOTA_M_M8 undef %13, [[PseudoVSLIDEDOWN_VI_M1_]], [[ADDI]] /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: $v0 = COPY [[PseudoVSLIDEDOWN_VI_M1_]] + ; CHECK-NEXT: early-clobber [[COPY]]:vrm8nov0 = PseudoVRGATHER_VV_M8_E16_MASK [[COPY]], [[PseudoVLE16_V_M8_1]], %13, $v0, [[ADDI]] /* vl */, 4 /* e16 */, 1 /* ta, mu */ + ; CHECK-NEXT: $v8m8 = COPY [[COPY1]] + ; CHECK-NEXT: $v16m8 = COPY [[COPY]] + ; CHECK-NEXT: PseudoRET implicit $v8m8, implicit $v16m8 + %23:vrm8nov0 = COPY $v16m8 + %12:vrm8nov0 = COPY $v8m8 + %6:vr = COPY $v0 + %0:gpr = COPY $x10 + %8:gprnox0 = ADDI $x0, 64 + early-clobber %9:vrm8 = PseudoVIOTA_M_M8 undef %9, %6, %8, 4 /* e16 */, 0 /* tu, mu */ + %10:gprnox0 = PseudoVCPOP_M_B2 %6, %8, 0 /* e8 */ + %11:vrm8 = PseudoVLE16_V_M8 undef %11, %0, %10, 4 /* e16 */, 2 /* tu, ma */ + $v0 = COPY %6 + early-clobber %12:vrm8nov0 = PseudoVRGATHER_VV_M8_E16_MASK %12, %11, %9, $v0, %8, 4 /* e16 */, 1 /* ta, mu */ + %16:vr = PseudoVSLIDEDOWN_VI_M1 undef %16, %6, 8, 8, 3 /* e8 */, 3 /* ta, ma */ + %18:gprnox0 = PseudoVCPOP_M_B2 %16, %8, 0 /* e8 */ + %19:gpr = SLLI %10, 1 + %20:gpr = ADD %0, %19 + %21:vrm8 = PseudoVLE16_V_M8 undef %21, %20, %18, 4 /* e16 */, 2 /* tu, ma */ + early-clobber %22:vrm8 = PseudoVIOTA_M_M8 undef %22, %16, %8, 4 /* e16 */, 0 /* tu, mu */ + $v0 = COPY %16 + early-clobber %23:vrm8nov0 = PseudoVRGATHER_VV_M8_E16_MASK %23, %21, %22, $v0, %8, 4 /* e16 */, 1 /* ta, mu */ + $v8m8 = COPY %12 + $v16m8 = COPY %23 + PseudoRET implicit $v8m8, implicit $v16m8 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/stack-inst-compress.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/stack-inst-compress.mir new file mode 100644 index 0000000..bd31662 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/stack-inst-compress.mir @@ -0,0 +1,346 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 +# RUN: llc -mtriple=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefixes=CHECK-RV32-NO-COM %s +# RUN: llc -mtriple=riscv32 -mattr=+c -x mir -run-pass=prologepilog \ +# RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-RV32-COM %s +# RUN: llc -mtriple=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \ +# RUN: | FileCheck -check-prefixes=CHECK-RV64-NO-COM %s +# RUN: llc -mtriple=riscv64 -mattr=+c -x mir -run-pass=prologepilog \ +# RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-RV64-COM %s +--- | + define dso_local void @_Z15stack_size_2048v() { + entry: + ret void + } + + declare dso_local void @_Z6calleePi(ptr noundef) + + define dso_local void @_Z15stack_size_4096v() { + entry: + ret void + } + + define dso_local void @_Z15stack_size_8192v() { + entry: + ret void + } + +... +--- +name: _Z15stack_size_2048v +alignment: 2 +tracksRegLiveness: true +frameInfo: + maxAlignment: 4 + adjustsStack: true + hasCalls: true + localFrameSize: 2048 +stack: + - { id: 0, size: 2048, alignment: 4, local-offset: -2048 } +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + ; CHECK-RV32-NO-COM-LABEL: name: _Z15stack_size_2048v + ; CHECK-RV32-NO-COM: liveins: $x1 + ; CHECK-RV32-NO-COM-NEXT: {{ $}} + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-setup ADDI $x2, -2032 + ; CHECK-RV32-NO-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-RV32-NO-COM-NEXT: frame-setup SW killed $x1, $x2, 2028 :: (store (s32) into %stack.1) + ; CHECK-RV32-NO-COM-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-setup ADDI $x2, -32 + ; CHECK-RV32-NO-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2064 + ; CHECK-RV32-NO-COM-NEXT: renamable $x10 = ADDI $x2, 12 + ; CHECK-RV32-NO-COM-NEXT: PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-destroy ADDI $x2, 32 + ; CHECK-RV32-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-RV32-NO-COM-NEXT: $x1 = frame-destroy LW $x2, 2028 :: (load (s32) from %stack.1) + ; CHECK-RV32-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-RV32-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-RV32-NO-COM-NEXT: PseudoRET + ; + ; CHECK-RV32-COM-LABEL: name: _Z15stack_size_2048v + ; CHECK-RV32-COM: liveins: $x1 + ; CHECK-RV32-COM-NEXT: {{ $}} + ; CHECK-RV32-COM-NEXT: $x2 = frame-setup ADDI $x2, -256 + ; CHECK-RV32-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 256 + ; CHECK-RV32-COM-NEXT: frame-setup SW killed $x1, $x2, 252 :: (store (s32) into %stack.1) + ; CHECK-RV32-COM-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-RV32-COM-NEXT: $x2 = frame-setup ADDI $x2, -1808 + ; CHECK-RV32-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2064 + ; CHECK-RV32-COM-NEXT: renamable $x10 = ADDI $x2, 12 + ; CHECK-RV32-COM-NEXT: PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ; CHECK-RV32-COM-NEXT: $x2 = frame-destroy ADDI $x2, 1808 + ; CHECK-RV32-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 256 + ; CHECK-RV32-COM-NEXT: $x1 = frame-destroy LW $x2, 252 :: (load (s32) from %stack.1) + ; CHECK-RV32-COM-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-RV32-COM-NEXT: $x2 = frame-destroy ADDI $x2, 256 + ; CHECK-RV32-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-RV32-COM-NEXT: PseudoRET + ; + ; CHECK-RV64-NO-COM-LABEL: name: _Z15stack_size_2048v + ; CHECK-RV64-NO-COM: liveins: $x1 + ; CHECK-RV64-NO-COM-NEXT: {{ $}} + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-setup ADDI $x2, -2032 + ; CHECK-RV64-NO-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-RV64-NO-COM-NEXT: frame-setup SD killed $x1, $x2, 2024 :: (store (s64) into %stack.1) + ; CHECK-RV64-NO-COM-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-setup ADDI $x2, -32 + ; CHECK-RV64-NO-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2064 + ; CHECK-RV64-NO-COM-NEXT: renamable $x10 = ADDI $x2, 8 + ; CHECK-RV64-NO-COM-NEXT: PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-destroy ADDI $x2, 32 + ; CHECK-RV64-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-RV64-NO-COM-NEXT: $x1 = frame-destroy LD $x2, 2024 :: (load (s64) from %stack.1) + ; CHECK-RV64-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-RV64-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-RV64-NO-COM-NEXT: PseudoRET + ; + ; CHECK-RV64-COM-LABEL: name: _Z15stack_size_2048v + ; CHECK-RV64-COM: liveins: $x1 + ; CHECK-RV64-COM-NEXT: {{ $}} + ; CHECK-RV64-COM-NEXT: $x2 = frame-setup ADDI $x2, -496 + ; CHECK-RV64-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 496 + ; CHECK-RV64-COM-NEXT: frame-setup SD killed $x1, $x2, 488 :: (store (s64) into %stack.1) + ; CHECK-RV64-COM-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-RV64-COM-NEXT: $x2 = frame-setup ADDI $x2, -1568 + ; CHECK-RV64-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2064 + ; CHECK-RV64-COM-NEXT: renamable $x10 = ADDI $x2, 8 + ; CHECK-RV64-COM-NEXT: PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ; CHECK-RV64-COM-NEXT: $x2 = frame-destroy ADDI $x2, 1568 + ; CHECK-RV64-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 496 + ; CHECK-RV64-COM-NEXT: $x1 = frame-destroy LD $x2, 488 :: (load (s64) from %stack.1) + ; CHECK-RV64-COM-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-RV64-COM-NEXT: $x2 = frame-destroy ADDI $x2, 496 + ; CHECK-RV64-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-RV64-COM-NEXT: PseudoRET + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + renamable $x10 = ADDI %stack.0, 0 + PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + PseudoRET + +... +--- +name: _Z15stack_size_4096v +alignment: 2 +tracksRegLiveness: true +frameInfo: + maxAlignment: 4 + adjustsStack: true + hasCalls: true + localFrameSize: 4096 +stack: + - { id: 0, size: 4096, alignment: 4, local-offset: -4096 } +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + ; CHECK-RV32-NO-COM-LABEL: name: _Z15stack_size_4096v + ; CHECK-RV32-NO-COM: liveins: $x1 + ; CHECK-RV32-NO-COM-NEXT: {{ $}} + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-setup ADDI $x2, -2032 + ; CHECK-RV32-NO-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-RV32-NO-COM-NEXT: frame-setup SW killed $x1, $x2, 2028 :: (store (s32) into %stack.1) + ; CHECK-RV32-NO-COM-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-setup ADDI $x2, -2048 + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-setup ADDI killed $x2, -32 + ; CHECK-RV32-NO-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 4112 + ; CHECK-RV32-NO-COM-NEXT: renamable $x10 = ADDI $x2, 12 + ; CHECK-RV32-NO-COM-NEXT: PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-destroy ADDI killed $x2, 48 + ; CHECK-RV32-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-RV32-NO-COM-NEXT: $x1 = frame-destroy LW $x2, 2028 :: (load (s32) from %stack.1) + ; CHECK-RV32-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-RV32-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-RV32-NO-COM-NEXT: PseudoRET + ; + ; CHECK-RV32-COM-LABEL: name: _Z15stack_size_4096v + ; CHECK-RV32-COM: liveins: $x1 + ; CHECK-RV32-COM-NEXT: {{ $}} + ; CHECK-RV32-COM-NEXT: $x2 = frame-setup ADDI $x2, -256 + ; CHECK-RV32-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 256 + ; CHECK-RV32-COM-NEXT: frame-setup SW killed $x1, $x2, 252 :: (store (s32) into %stack.1) + ; CHECK-RV32-COM-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-RV32-COM-NEXT: $x2 = frame-setup ADDI $x2, -2048 + ; CHECK-RV32-COM-NEXT: $x2 = frame-setup ADDI killed $x2, -1808 + ; CHECK-RV32-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 4112 + ; CHECK-RV32-COM-NEXT: renamable $x10 = ADDI $x2, 12 + ; CHECK-RV32-COM-NEXT: PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ; CHECK-RV32-COM-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-RV32-COM-NEXT: $x2 = frame-destroy ADDI killed $x2, 1824 + ; CHECK-RV32-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 256 + ; CHECK-RV32-COM-NEXT: $x1 = frame-destroy LW $x2, 252 :: (load (s32) from %stack.1) + ; CHECK-RV32-COM-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-RV32-COM-NEXT: $x2 = frame-destroy ADDI $x2, 256 + ; CHECK-RV32-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-RV32-COM-NEXT: PseudoRET + ; + ; CHECK-RV64-NO-COM-LABEL: name: _Z15stack_size_4096v + ; CHECK-RV64-NO-COM: liveins: $x1 + ; CHECK-RV64-NO-COM-NEXT: {{ $}} + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-setup ADDI $x2, -2032 + ; CHECK-RV64-NO-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-RV64-NO-COM-NEXT: frame-setup SD killed $x1, $x2, 2024 :: (store (s64) into %stack.1) + ; CHECK-RV64-NO-COM-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-setup ADDI $x2, -2048 + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-setup ADDI killed $x2, -32 + ; CHECK-RV64-NO-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 4112 + ; CHECK-RV64-NO-COM-NEXT: renamable $x10 = ADDI $x2, 8 + ; CHECK-RV64-NO-COM-NEXT: PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-destroy ADDI killed $x2, 48 + ; CHECK-RV64-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-RV64-NO-COM-NEXT: $x1 = frame-destroy LD $x2, 2024 :: (load (s64) from %stack.1) + ; CHECK-RV64-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-RV64-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-RV64-NO-COM-NEXT: PseudoRET + ; + ; CHECK-RV64-COM-LABEL: name: _Z15stack_size_4096v + ; CHECK-RV64-COM: liveins: $x1 + ; CHECK-RV64-COM-NEXT: {{ $}} + ; CHECK-RV64-COM-NEXT: $x2 = frame-setup ADDI $x2, -496 + ; CHECK-RV64-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 496 + ; CHECK-RV64-COM-NEXT: frame-setup SD killed $x1, $x2, 488 :: (store (s64) into %stack.1) + ; CHECK-RV64-COM-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-RV64-COM-NEXT: $x2 = frame-setup ADDI $x2, -2048 + ; CHECK-RV64-COM-NEXT: $x2 = frame-setup ADDI killed $x2, -1568 + ; CHECK-RV64-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 4112 + ; CHECK-RV64-COM-NEXT: renamable $x10 = ADDI $x2, 8 + ; CHECK-RV64-COM-NEXT: PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ; CHECK-RV64-COM-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-RV64-COM-NEXT: $x2 = frame-destroy ADDI killed $x2, 1584 + ; CHECK-RV64-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 496 + ; CHECK-RV64-COM-NEXT: $x1 = frame-destroy LD $x2, 488 :: (load (s64) from %stack.1) + ; CHECK-RV64-COM-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-RV64-COM-NEXT: $x2 = frame-destroy ADDI $x2, 496 + ; CHECK-RV64-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-RV64-COM-NEXT: PseudoRET + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + renamable $x10 = ADDI %stack.0, 0 + PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + PseudoRET + +... +--- +name: _Z15stack_size_8192v +alignment: 2 +tracksRegLiveness: true +frameInfo: + maxAlignment: 4 + adjustsStack: true + hasCalls: true + localFrameSize: 8192 +stack: + - { id: 0, size: 8192, alignment: 4, local-offset: -8192 } +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + ; CHECK-RV32-NO-COM-LABEL: name: _Z15stack_size_8192v + ; CHECK-RV32-NO-COM: liveins: $x1 + ; CHECK-RV32-NO-COM-NEXT: {{ $}} + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-setup ADDI $x2, -2032 + ; CHECK-RV32-NO-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-RV32-NO-COM-NEXT: frame-setup SW killed $x1, $x2, 2028 :: (store (s32) into %stack.1) + ; CHECK-RV32-NO-COM-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-RV32-NO-COM-NEXT: $x10 = frame-setup LUI 2 + ; CHECK-RV32-NO-COM-NEXT: $x10 = frame-setup ADDI killed $x10, -2016 + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-setup SUB $x2, killed $x10 + ; CHECK-RV32-NO-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8208 + ; CHECK-RV32-NO-COM-NEXT: renamable $x10 = ADDI $x2, 12 + ; CHECK-RV32-NO-COM-NEXT: PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ; CHECK-RV32-NO-COM-NEXT: $x10 = frame-destroy LUI 2 + ; CHECK-RV32-NO-COM-NEXT: $x10 = frame-destroy ADDI killed $x10, -2016 + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-destroy ADD $x2, killed $x10 + ; CHECK-RV32-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-RV32-NO-COM-NEXT: $x1 = frame-destroy LW $x2, 2028 :: (load (s32) from %stack.1) + ; CHECK-RV32-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-RV32-NO-COM-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-RV32-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-RV32-NO-COM-NEXT: PseudoRET + ; + ; CHECK-RV32-COM-LABEL: name: _Z15stack_size_8192v + ; CHECK-RV32-COM: liveins: $x1 + ; CHECK-RV32-COM-NEXT: {{ $}} + ; CHECK-RV32-COM-NEXT: $x2 = frame-setup ADDI $x2, -256 + ; CHECK-RV32-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 256 + ; CHECK-RV32-COM-NEXT: frame-setup SW killed $x1, $x2, 252 :: (store (s32) into %stack.1) + ; CHECK-RV32-COM-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-RV32-COM-NEXT: $x10 = frame-setup LUI 2 + ; CHECK-RV32-COM-NEXT: $x10 = frame-setup ADDI killed $x10, -240 + ; CHECK-RV32-COM-NEXT: $x2 = frame-setup SUB $x2, killed $x10 + ; CHECK-RV32-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8208 + ; CHECK-RV32-COM-NEXT: renamable $x10 = ADDI $x2, 12 + ; CHECK-RV32-COM-NEXT: PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ; CHECK-RV32-COM-NEXT: $x10 = frame-destroy LUI 2 + ; CHECK-RV32-COM-NEXT: $x10 = frame-destroy ADDI killed $x10, -240 + ; CHECK-RV32-COM-NEXT: $x2 = frame-destroy ADD $x2, killed $x10 + ; CHECK-RV32-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 256 + ; CHECK-RV32-COM-NEXT: $x1 = frame-destroy LW $x2, 252 :: (load (s32) from %stack.1) + ; CHECK-RV32-COM-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-RV32-COM-NEXT: $x2 = frame-destroy ADDI $x2, 256 + ; CHECK-RV32-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-RV32-COM-NEXT: PseudoRET + ; + ; CHECK-RV64-NO-COM-LABEL: name: _Z15stack_size_8192v + ; CHECK-RV64-NO-COM: liveins: $x1 + ; CHECK-RV64-NO-COM-NEXT: {{ $}} + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-setup ADDI $x2, -2032 + ; CHECK-RV64-NO-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-RV64-NO-COM-NEXT: frame-setup SD killed $x1, $x2, 2024 :: (store (s64) into %stack.1) + ; CHECK-RV64-NO-COM-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-RV64-NO-COM-NEXT: $x10 = frame-setup LUI 2 + ; CHECK-RV64-NO-COM-NEXT: $x10 = frame-setup ADDI killed $x10, -2016 + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-setup SUB $x2, killed $x10 + ; CHECK-RV64-NO-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8208 + ; CHECK-RV64-NO-COM-NEXT: renamable $x10 = ADDI $x2, 8 + ; CHECK-RV64-NO-COM-NEXT: PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ; CHECK-RV64-NO-COM-NEXT: $x10 = frame-destroy LUI 2 + ; CHECK-RV64-NO-COM-NEXT: $x10 = frame-destroy ADDI killed $x10, -2016 + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-destroy ADD $x2, killed $x10 + ; CHECK-RV64-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 2032 + ; CHECK-RV64-NO-COM-NEXT: $x1 = frame-destroy LD $x2, 2024 :: (load (s64) from %stack.1) + ; CHECK-RV64-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-RV64-NO-COM-NEXT: $x2 = frame-destroy ADDI $x2, 2032 + ; CHECK-RV64-NO-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-RV64-NO-COM-NEXT: PseudoRET + ; + ; CHECK-RV64-COM-LABEL: name: _Z15stack_size_8192v + ; CHECK-RV64-COM: liveins: $x1 + ; CHECK-RV64-COM-NEXT: {{ $}} + ; CHECK-RV64-COM-NEXT: $x2 = frame-setup ADDI $x2, -496 + ; CHECK-RV64-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 496 + ; CHECK-RV64-COM-NEXT: frame-setup SD killed $x1, $x2, 488 :: (store (s64) into %stack.1) + ; CHECK-RV64-COM-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-RV64-COM-NEXT: $x10 = frame-setup LUI 2 + ; CHECK-RV64-COM-NEXT: $x10 = frame-setup ADDI killed $x10, -480 + ; CHECK-RV64-COM-NEXT: $x2 = frame-setup SUB $x2, killed $x10 + ; CHECK-RV64-COM-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8208 + ; CHECK-RV64-COM-NEXT: renamable $x10 = ADDI $x2, 8 + ; CHECK-RV64-COM-NEXT: PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ; CHECK-RV64-COM-NEXT: $x10 = frame-destroy LUI 2 + ; CHECK-RV64-COM-NEXT: $x10 = frame-destroy ADDI killed $x10, -480 + ; CHECK-RV64-COM-NEXT: $x2 = frame-destroy ADD $x2, killed $x10 + ; CHECK-RV64-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 496 + ; CHECK-RV64-COM-NEXT: $x1 = frame-destroy LD $x2, 488 :: (load (s64) from %stack.1) + ; CHECK-RV64-COM-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-RV64-COM-NEXT: $x2 = frame-destroy ADDI $x2, 496 + ; CHECK-RV64-COM-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-RV64-COM-NEXT: PseudoRET + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + renamable $x10 = ADDI %stack.0, 0 + PseudoCALL target-flags(riscv-call) @_Z6calleePi, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit-def $x2 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir new file mode 100644 index 0000000..ad7273a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir @@ -0,0 +1,198 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \ +# RUN: | FileCheck %s -check-prefixes=RV64I +# RUN: llc -mtriple=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \ +# RUN: | FileCheck %s -check-prefixes=RV32I +--- | + ; Function Attrs: uwtable + define void @no_reserved_call_frame(i64 %n) #0 { + entry: + %v = alloca i32, i64 %n, align 4 + call void @callee_stack_args(ptr %v, [518 x i64] poison) + ret void + } + + declare void @callee_stack_args(ptr, [518 x i64]) #1 + + attributes #0 = { uwtable "frame-pointer"="none" "probe-stack"="inline-asm" "target-features"="+m" } + attributes #1 = { "target-features"="+m" } +... +--- +name: no_reserved_call_frame +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +noPhis: true +isSSA: false +noVRegs: true +hasFakeUses: false +callsEHReturn: false +callsUnwindInit: false +hasEHContTarget: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: true +registers: [] +liveins: + - { reg: '$x10', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: true + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + isCalleeSavedInfoValid: false + localFrameSize: 0 + savePoint: [] + restorePoint: [] +fixedStack: [] +stack: + - { id: 0, name: v, type: variable-sized, offset: 0, alignment: 1, stack-id: default, + callee-saved-register: '', callee-saved-restored: true, local-offset: 0, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; RV64I-LABEL: name: no_reserved_call_frame + ; RV64I: bb.0.entry: + ; RV64I-NEXT: successors: %bb.1(0x80000000) + ; RV64I-NEXT: liveins: $x10, $x1 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; RV64I-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; RV64I-NEXT: frame-setup SD killed $x1, $x2, 8 :: (store (s64) into %stack.1) + ; RV64I-NEXT: frame-setup SD killed $x8, $x2, 0 :: (store (s64) into %stack.2) + ; RV64I-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; RV64I-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; RV64I-NEXT: $x8 = frame-setup ADDI $x2, 16 + ; RV64I-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0 + ; RV64I-NEXT: renamable $x10 = SLLI killed renamable $x10, 2 + ; RV64I-NEXT: renamable $x10 = nuw ADDI killed renamable $x10, 15 + ; RV64I-NEXT: renamable $x10 = ANDI killed renamable $x10, -16 + ; RV64I-NEXT: renamable $x10 = SUB $x2, killed renamable $x10 + ; RV64I-NEXT: renamable $x11 = LUI 1 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.1.entry: + ; RV64I-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; RV64I-NEXT: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: $x2 = SUB $x2, renamable $x11 + ; RV64I-NEXT: SD $x0, $x2, 0 + ; RV64I-NEXT: BLT renamable $x10, $x2, %bb.1 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.2.entry: + ; RV64I-NEXT: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: $x2 = ADDI renamable $x10, 0 + ; RV64I-NEXT: $x11 = LUI 1 + ; RV64I-NEXT: $x2 = SUB $x2, killed $x11 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_stack_args, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit undef $x11, implicit undef $x12, implicit undef $x13, implicit undef $x14, implicit undef $x15, implicit undef $x16, implicit undef $x17, implicit-def $x2 + ; RV64I-NEXT: $x10 = LUI 1 + ; RV64I-NEXT: $x2 = ADD $x2, killed $x10 + ; RV64I-NEXT: $x2 = frame-destroy ADDI $x8, -16 + ; RV64I-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 16 + ; RV64I-NEXT: $x1 = frame-destroy LD $x2, 8 :: (load (s64) from %stack.1) + ; RV64I-NEXT: $x8 = frame-destroy LD $x2, 0 :: (load (s64) from %stack.2) + ; RV64I-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; RV64I-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; RV64I-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; RV64I-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; RV64I-NEXT: PseudoRET + ; + ; RV32I-LABEL: name: no_reserved_call_frame + ; RV32I: bb.0.entry: + ; RV32I-NEXT: successors: %bb.1(0x80000000) + ; RV32I-NEXT: liveins: $x10, $x1 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; RV32I-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; RV32I-NEXT: frame-setup SW killed $x1, $x2, 12 :: (store (s32) into %stack.1) + ; RV32I-NEXT: frame-setup SW killed $x8, $x2, 8 :: (store (s32) into %stack.2) + ; RV32I-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; RV32I-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; RV32I-NEXT: $x8 = frame-setup ADDI $x2, 16 + ; RV32I-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0 + ; RV32I-NEXT: renamable $x10 = SLLI killed renamable $x10, 2 + ; RV32I-NEXT: renamable $x10 = nuw ADDI killed renamable $x10, 15 + ; RV32I-NEXT: renamable $x10 = ANDI killed renamable $x10, -16 + ; RV32I-NEXT: renamable $x10 = SUB $x2, killed renamable $x10 + ; RV32I-NEXT: renamable $x11 = LUI 1 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.1.entry: + ; RV32I-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; RV32I-NEXT: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: $x2 = SUB $x2, renamable $x11 + ; RV32I-NEXT: SD $x0, $x2, 0 + ; RV32I-NEXT: BLT renamable $x10, $x2, %bb.1 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.2.entry: + ; RV32I-NEXT: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: $x2 = ADDI renamable $x10, 0 + ; RV32I-NEXT: $x11 = LUI 1 + ; RV32I-NEXT: $x2 = SUB $x2, killed $x11 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_stack_args, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit undef $x11, implicit undef $x12, implicit undef $x13, implicit undef $x14, implicit undef $x15, implicit undef $x16, implicit undef $x17, implicit-def $x2 + ; RV32I-NEXT: $x10 = LUI 1 + ; RV32I-NEXT: $x2 = ADD $x2, killed $x10 + ; RV32I-NEXT: $x2 = frame-destroy ADDI $x8, -16 + ; RV32I-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 16 + ; RV32I-NEXT: $x1 = frame-destroy LW $x2, 12 :: (load (s32) from %stack.1) + ; RV32I-NEXT: $x8 = frame-destroy LW $x2, 8 :: (load (s32) from %stack.2) + ; RV32I-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; RV32I-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; RV32I-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; RV32I-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; RV32I-NEXT: PseudoRET + bb.0.entry: + successors: %bb.1(0x80000000) + liveins: $x10 + + renamable $x10 = SLLI killed renamable $x10, 2 + renamable $x10 = nuw ADDI killed renamable $x10, 15 + renamable $x10 = ANDI killed renamable $x10, -16 + renamable $x10 = SUB $x2, killed renamable $x10 + renamable $x11 = LUI 1 + + bb.1.entry: + successors: %bb.2(0x40000000), %bb.1(0x40000000) + liveins: $x10, $x11 + + $x2 = SUB $x2, renamable $x11 + SD $x0, $x2, 0 + BLT renamable $x10, $x2, %bb.1 + + bb.2.entry: + liveins: $x10 + + $x2 = ADDI renamable $x10, 0 + ADJCALLSTACKDOWN 4088, 0, implicit-def dead $x2, implicit $x2 + PseudoCALL target-flags(riscv-call) @callee_stack_args, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit undef $x11, implicit undef $x12, implicit undef $x13, implicit undef $x14, implicit undef $x15, implicit undef $x16, implicit undef $x17, implicit-def $x2 + ADJCALLSTACKUP 4088, 0, implicit-def dead $x2, implicit $x2 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/stack-slot-coloring.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/stack-slot-coloring.mir new file mode 100644 index 0000000..869553f --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/stack-slot-coloring.mir @@ -0,0 +1,213 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=greedy,virtregrewriter,stack-slot-coloring %s -o - 2>&1 | FileCheck %s + +--- | + define dso_local i32 @main() local_unnamed_addr { + entry: + %a = alloca i32, align 4 + ret i32 0 + } + +... +--- +name: main +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHContTarget: false +hasEHScopes: false +hasEHFunclets: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gpr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } +liveins: [] +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: [] + restorePoint: [] +fixedStack: [] +stack: + - { id: 0, name: a, type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + ; CHECK-LABEL: name: main + ; CHECK: $x10 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x11 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x12 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x13 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x14 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x15 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x16 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x17 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x5 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x6 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x7 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x28 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x29 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x30 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x31 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x8 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x9 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x18 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x19 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x20 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x21 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x22 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x23 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x24 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x25 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x26 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: $x27 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: renamable $x1 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: SW killed renamable $x1, %stack.1, 0 :: (store (s32) into %stack.1) + ; CHECK-NEXT: renamable $x1 = LB %stack.0.a, 0 :: (volatile dereferenceable load (s8) from %ir.a) + ; CHECK-NEXT: SW killed renamable $x1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: renamable $x1 = LW %stack.1, 0 :: (load (s32) from %stack.1) + ; CHECK-NEXT: SW killed renamable $x1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: renamable $x1 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + ; CHECK-NEXT: SW killed renamable $x1, %stack.1, 0 :: (store (s32) into %stack.1) + ; CHECK-NEXT: renamable $x1 = LB %stack.0.a, 0 :: (volatile dereferenceable load (s8) from %ir.a) + ; CHECK-NEXT: SW killed renamable $x1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: renamable $x1 = LW %stack.1, 0 :: (load (s32) from %stack.1) + ; CHECK-NEXT: SW killed renamable $x1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x10, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x11, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x12, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x13, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x14, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x15, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x16, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x17, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x5, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x6, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x7, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x28, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x29, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x30, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x31, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x8, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x9, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x18, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x19, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x20, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x21, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x22, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x23, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x24, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x25, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x26, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: SW $x27, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + ; CHECK-NEXT: $x10 = COPY $x0 + ; CHECK-NEXT: PseudoRET implicit $x10 + $x10 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x11 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x12 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x13 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x14 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x15 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x16 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x17 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x5 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x6 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x7 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x28 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x29 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x30 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x31 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x8 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x9 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x18 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x19 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x20 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x21 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x22 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x23 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x24 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x25 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x26 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + $x27 = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + + ; First vreg load + %1:gpr = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + + ; First faulty sequence; %1 spilt + %12:gpr = LB %stack.0.a, 0 :: (volatile dereferenceable load (s8) from %ir.a) + SW %12, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + + ; Store %1 to avoid it being optimised out, will result in a load-from-spill + SW %1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + + ; That code sequence a second time, to generate a second spill slot that + ; will get coloured and merged. + %2:gpr = LW %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a) + + %22:gpr = LB %stack.0.a, 0 :: (volatile dereferenceable load (s8) from %ir.a) + SW %22, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + + SW %2, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + + SW $x10, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x11, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x12, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x13, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x14, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x15, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x16, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x17, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x5, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x6, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x7, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x28, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x29, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x30, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x31, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x8, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x9, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x18, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x19, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x20, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x21, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x22, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x23, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x24, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x25, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x26, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + SW $x27, %stack.0.a, 0 :: (volatile store (s32) into %ir.a) + $x10 = COPY $x0 + PseudoRET implicit killed $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/twoaddr-tied.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/twoaddr-tied.mir new file mode 100644 index 0000000..dbf10d5 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/twoaddr-tied.mir @@ -0,0 +1,53 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=riscv64 -start-before twoaddressinstruction \ +# RUN: -stop-before riscv-asm-printer -o - %s -mattr=+v | FileCheck %s + +--- +name: foo +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: foo + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead renamable $x10 = IMPLICIT_DEF + ; CHECK-NEXT: dead renamable $v8m4 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $v8m4 = IMPLICIT_DEF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) + ; CHECK-NEXT: liveins: $v8m4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v12m4 = PseudoVLE32_V_M4 undef renamable $v12m4, undef renamable $x10, 0 /* vl */, 5 /* e32 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 4) + ; CHECK-NEXT: renamable $v8m4 = PseudoVFMACC_VV_M4_E32 killed renamable $v8m4, undef renamable $v8m4, killed renamable $v12m4, 0 /* frm=rne */, 0 /* vl */, 5 /* e32 */, 1 /* ta, mu */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 146 /* e32, m4, tu, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl + ; CHECK-NEXT: renamable $v8m4 = PseudoVFMACC_VV_M4_E32 killed renamable $v8m4, undef renamable $v8m4, undef renamable $v8m4, 0 /* frm=rne */, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: BNE undef renamable $x10, $x0, %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: PseudoRET + bb.0: + successors: %bb.1(0x80000000) + liveins: $x10, $x11 + + %28:gpr = IMPLICIT_DEF + %29:vrm4 = IMPLICIT_DEF + %23:vrm4 = IMPLICIT_DEF + + bb.1: + successors: %bb.2(0x04000000), %bb.1(0x7c000000) + + %3:vrm4 = COPY killed %23 + %13:vrm4 = PseudoVLE32_V_M4 undef %29, undef %28, 0, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size, align 4) + %14:vrm4 = PseudoVFMACC_VV_M4_E32 killed %3, undef %29, killed %13, 0, 0, 5 /* e32 */, 1 /* ta, mu */, implicit $frm + %4:vrm4 = PseudoVFMACC_VV_M4_E32 killed %14, undef %29, undef %29, 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $frm + %23:vrm4 = COPY %4 + BNE killed undef %28, $x0, %bb.1 + PseudoBR %bb.2 + + bb.2: + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/verify-instr.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/verify-instr.mir new file mode 100644 index 0000000..b6deed3 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/verify-instr.mir @@ -0,0 +1,12 @@ +# RUN: not --crash llc -mtriple=riscv32 -run-pass machineverifier %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=riscv32 --passes='machine-function(verify)' %s -o - 2>&1 | FileCheck %s + +# CHECK: *** Bad machine code: Invalid immediate *** +# CHECK: - instruction: $x2 = ADDI $x1, 10000 + +--- +name: verify_instr +body: | + bb.0: + $x2 = ADDI $x1, 10000 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/xqccmp-cm-popretz.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/xqccmp-cm-popretz.mir new file mode 100644 index 0000000..4f79743 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/xqccmp-cm-popretz.mir @@ -0,0 +1,70 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -mattr=+xqccmp -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-XQCCMP32 %s +# RUN: llc -mtriple=riscv64 -mattr=+xqccmp -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-XQCCMP64 %s +--- +name: popret_rvlist5 +tracksRegLiveness: true +frameInfo: + maxCallFrameSize: 0 +body: | + bb.0: + ; CHECK-XQCCMP32-LABEL: name: popret_rvlist5 + ; CHECK-XQCCMP32: liveins: $x1, $x8 + ; CHECK-XQCCMP32-NEXT: {{ $}} + ; CHECK-XQCCMP32-NEXT: frame-setup QC_CM_PUSH 5, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-XQCCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: frame-destroy QC_CM_POPRET 5, 0, implicit-def $x2, implicit $x2, implicit-def $x1, implicit-def $x8 + ; + ; CHECK-XQCCMP64-LABEL: name: popret_rvlist5 + ; CHECK-XQCCMP64: liveins: $x1, $x8 + ; CHECK-XQCCMP64-NEXT: {{ $}} + ; CHECK-XQCCMP64-NEXT: frame-setup QC_CM_PUSH 5, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-XQCCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: frame-destroy QC_CM_POPRET 5, 0, implicit-def $x2, implicit $x2, implicit-def $x1, implicit-def $x8 + $x1 = IMPLICIT_DEF + $x8 = IMPLICIT_DEF + PseudoRET +... +--- +name: popretz_rvlist5 +tracksRegLiveness: true +frameInfo: + maxCallFrameSize: 0 +body: | + bb.0: + ; CHECK-XQCCMP32-LABEL: name: popretz_rvlist5 + ; CHECK-XQCCMP32: liveins: $x1, $x8 + ; CHECK-XQCCMP32-NEXT: {{ $}} + ; CHECK-XQCCMP32-NEXT: frame-setup QC_CM_PUSH 5, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-XQCCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: frame-destroy QC_CM_POPRETZ 5, 0, implicit-def $x2, implicit-def $x10, implicit $x2, implicit-def $x1, implicit-def $x8 + ; + ; CHECK-XQCCMP64-LABEL: name: popretz_rvlist5 + ; CHECK-XQCCMP64: liveins: $x1, $x8 + ; CHECK-XQCCMP64-NEXT: {{ $}} + ; CHECK-XQCCMP64-NEXT: frame-setup QC_CM_PUSH 5, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-XQCCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: frame-destroy QC_CM_POPRETZ 5, 0, implicit-def $x2, implicit-def $x10, implicit $x2, implicit-def $x1, implicit-def $x8 + $x1 = IMPLICIT_DEF + $x8 = IMPLICIT_DEF + $x10 = COPY $x0 + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/xqccmp-cm-push-pop.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/xqccmp-cm-push-pop.mir new file mode 100644 index 0000000..7ed481a --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/xqccmp-cm-push-pop.mir @@ -0,0 +1,94 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -mattr=+xqccmp -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-XQCCMP32 %s +# RUN: llc -mtriple=riscv64 -mattr=+xqccmp -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-XQCCMP64 %s +--- +name: push_rvlist15 +tracksRegLiveness: true +frameInfo: + maxCallFrameSize: 0 +body: | + bb.0: + ; CHECK-XQCCMP32-LABEL: name: push_rvlist15 + ; CHECK-XQCCMP32: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-XQCCMP32-NEXT: {{ $}} + ; CHECK-XQCCMP32-NEXT: frame-setup QC_CM_PUSH 15, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8, implicit $x9, implicit $x18, implicit $x19, implicit $x20, implicit $x21, implicit $x22, implicit $x23, implicit $x24, implicit $x25, implicit $x26, implicit $x27 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 64 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -12 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -16 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -20 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -24 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -28 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -32 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -36 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -40 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -44 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -48 + ; CHECK-XQCCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -52 + ; CHECK-XQCCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-XQCCMP32-NEXT: frame-destroy QC_CM_POP 15, 0, implicit-def $x2, implicit $x2, implicit-def $x1, implicit-def $x8, implicit-def $x9, implicit-def $x18, implicit-def $x19, implicit-def $x20, implicit-def $x21, implicit-def $x22, implicit-def $x23, implicit-def $x24, implicit-def $x25, implicit-def $x26, implicit-def $x27 + ; CHECK-XQCCMP32-NEXT: PseudoRET + ; + ; CHECK-XQCCMP64-LABEL: name: push_rvlist15 + ; CHECK-XQCCMP64: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-XQCCMP64-NEXT: {{ $}} + ; CHECK-XQCCMP64-NEXT: frame-setup QC_CM_PUSH 15, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8, implicit $x9, implicit $x18, implicit $x19, implicit $x20, implicit $x21, implicit $x22, implicit $x23, implicit $x24, implicit $x25, implicit $x26, implicit $x27 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 112 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -24 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -32 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -40 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -48 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -56 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -64 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -72 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -80 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -88 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -96 + ; CHECK-XQCCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -104 + ; CHECK-XQCCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-XQCCMP64-NEXT: frame-destroy QC_CM_POP 15, 0, implicit-def $x2, implicit $x2, implicit-def $x1, implicit-def $x8, implicit-def $x9, implicit-def $x18, implicit-def $x19, implicit-def $x20, implicit-def $x21, implicit-def $x22, implicit-def $x23, implicit-def $x24, implicit-def $x25, implicit-def $x26, implicit-def $x27 + ; CHECK-XQCCMP64-NEXT: PseudoRET + $x1 = IMPLICIT_DEF + $x8 = IMPLICIT_DEF + $x9 = IMPLICIT_DEF + $x18 = IMPLICIT_DEF + $x19 = IMPLICIT_DEF + $x20 = IMPLICIT_DEF + $x21 = IMPLICIT_DEF + $x22 = IMPLICIT_DEF + $x23 = IMPLICIT_DEF + $x24 = IMPLICIT_DEF + $x25 = IMPLICIT_DEF + $x26 = IMPLICIT_DEF + $x27 = IMPLICIT_DEF + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/xqccmp_mvas_mvsa.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/xqccmp_mvas_mvsa.mir new file mode 100644 index 0000000..6483893 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/xqccmp_mvas_mvsa.mir @@ -0,0 +1,28 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -mattr=+xqccmp -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck -check-prefixes=CHECK32XQCCMP %s +# RUN: llc -mtriple=riscv64 -mattr=+xqccmp -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck -check-prefixes=CHECK64XQCCMP %s +--- +name: mv +tracksRegLiveness: true +body: | + bb.0: + liveins: $x11, $x10 + ; CHECK32XQCCMP-LABEL: name: mv + ; CHECK32XQCCMP: liveins: $x11, $x10 + ; CHECK32XQCCMP-NEXT: {{ $}} + ; CHECK32XQCCMP-NEXT: $x9, $x8 = QC_CM_MVSA01 implicit $x10, implicit $x11 + ; CHECK32XQCCMP-NEXT: QC_CM_MVA01S killed $x9, $x8, implicit-def $x10, implicit-def $x11 + ; CHECK32XQCCMP-NEXT: PseudoRET + ; + ; CHECK64XQCCMP-LABEL: name: mv + ; CHECK64XQCCMP: liveins: $x11, $x10 + ; CHECK64XQCCMP-NEXT: {{ $}} + ; CHECK64XQCCMP-NEXT: $x9, $x8 = QC_CM_MVSA01 implicit $x10, implicit $x11 + ; CHECK64XQCCMP-NEXT: QC_CM_MVA01S killed $x9, $x8, implicit-def $x10, implicit-def $x11 + ; CHECK64XQCCMP-NEXT: PseudoRET + $x8 = ADDI $x11, 0 + $x9 = ADDI $x10, 0 + $x10 = ADDI killed $x9, 0 + $x11 = ADDI $x8, 0 + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi-multiple.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi-multiple.mir new file mode 100644 index 0000000..688719b --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi-multiple.mir @@ -0,0 +1,207 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=riscv32 -mattr=+xqcilsm -run-pass=riscv-load-store-opt %s -o - | FileCheck %s + +--- | + + define void @lwmi() { ret void } + define void @lwmi_x0() { ret void } + define void @lwmi_nonconsecutive() { ret void } + define void @lwmi_misaligned() { ret void } + define void @swmi() { ret void } + define void @swmi_x0() { ret void } + define void @swmi_nonconsecutive() { ret void } + define void @swmi_misaligned() { ret void} + + define void @setwmi(ptr %a, ptr %b, ptr %c, ptr %d) { + entry: + store i32 0, ptr %a, align 4 + store i32 0, ptr %b, align 4 + store i32 0, ptr %c, align 4 + store i32 0, ptr %d, align 4 + ret void + } + + define void @setwmi_no_pair_move_insn_back() { ret void } + +... +--- +name: lwmi +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: lwmi + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x28 = QC_LWMI $x10, 4, 0, implicit-def $x29, implicit-def $x30, implicit-def $x31 :: (load (s32)) + ; CHECK-NEXT: $x10 = ADD $x28, $x29 + ; CHECK-NEXT: $x10 = ADD $x10, $x30 + ; CHECK-NEXT: $x10 = ADD $x10, $x31 + ; CHECK-NEXT: PseudoRET + $x28 = LW $x10, 0 :: (load (s32), align 4) + $x29 = LW $x10, 4 :: (load (s32), align 4) + $x30 = LW $x10, 8 :: (load (s32), align 4) + $x31 = LW $x10, 12 :: (load (s32), align 4) + $x10 = ADD $x28, $x29 + $x10 = ADD $x10, $x30 + $x10 = ADD $x10, $x31 + PseudoRET +... +--- +name: lwmi_x0 +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: lwmi_x0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x0 = LW $x10, 0 :: (load (s32)) + ; CHECK-NEXT: $x1 = QC_LWMI killed $x10, 3, 4, implicit-def $x2, implicit-def $x3 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x0 = LW $x10, 0 :: (load (s32), align 4) + $x1 = LW $x10, 4 :: (load (s32), align 4) + $x2 = LW $x10, 8 :: (load (s32), align 4) + $x3 = LW killed $x10, 12 :: (load (s32), align 4) + PseudoRET +... +--- +name: lwmi_nonconsecutive +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: lwmi_nonconsecutive + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x28 = LW $x10, 0 :: (load (s32)) + ; CHECK-NEXT: $x29 = LW $x10, 8 :: (load (s32)) + ; CHECK-NEXT: $x30 = LW $x10, 4 :: (load (s32)) + ; CHECK-NEXT: $x31 = LW $x10, 12 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x28 = LW $x10, 0 :: (load (s32), align 4) + $x29 = LW $x10, 8 :: (load (s32), align 4) + $x30 = LW $x10, 4 :: (load (s32), align 4) + $x31 = LW $x10, 12 :: (load (s32), align 4) + PseudoRET +... +--- +name: lwmi_misaligned +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: lwmi_misaligned + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x28 = LW $x10, 2 :: (load (s32)) + ; CHECK-NEXT: $x29 = LW $x10, 6 :: (load (s32)) + ; CHECK-NEXT: $x30 = LW $x10, 10 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x28 = LW $x10, 2 :: (load (s32), align 4) + $x29 = LW $x10, 6 :: (load (s32), align 4) + $x30 = LW $x10, 10 :: (load (s32), align 4) + PseudoRET +... +--- +name: swmi +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: swmi + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: QC_SWMI killed $x28, $x10, 4, 0, implicit killed $x29, implicit $x30, implicit killed $x31 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW killed $x28, $x10, 0 :: (store (s32), align 4) + SW killed $x29, $x10, 4 :: (store (s32), align 4) + SW $x30, $x10, 8 :: (store (s32), align 4) + SW killed $x31, $x10, 12 :: (store (s32), align 4) + PseudoRET +... +--- +name: swmi_x0 +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: swmi_x0 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SW $x0, $x10, 0 :: (store (s32)) + ; CHECK-NEXT: QC_SWMI $x1, $x10, 3, 4, implicit $x2, implicit $x3 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW $x0, $x10, 0 :: (store (s32), align 4) + SW $x1, $x10, 4 :: (store (s32), align 4) + SW $x2, $x10, 8 :: (store (s32), align 4) + SW $x3, $x10, 12 :: (store (s32), align 4) + PseudoRET +... +--- +name: swmi_nonconsecutive +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: swmi_nonconsecutive + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: QC_SWMI $x28, $x10, 2, 0, implicit killed $x29 :: (store (s32)) + ; CHECK-NEXT: $x11 = ADDI $x28, 1 + ; CHECK-NEXT: QC_SWMI $x30, $x10, 2, 8, implicit killed $x31 :: (store (s32)) + ; CHECK-NEXT: $x12 = ADDI $x30, 1 + ; CHECK-NEXT: PseudoRET + SW $x28, $x10, 0 :: (store (s32), align 4) + $x11 = ADDI $x28, 1 + SW killed $x29, $x10, 4 :: (store (s32), align 4) + SW $x30, $x10, 8 :: (store (s32), align 4) + $x12 = ADDI $x30, 1 + SW killed $x31, $x10, 12 :: (store (s32), align 4) + PseudoRET +... +--- +name: swmi_misaligned +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: swmi_misaligned + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SW $x0, $x10, 0 :: (store (s32)) + ; CHECK-NEXT: SW $x1, $x10, 4 :: (store (s32)) + ; CHECK-NEXT: SW $x2, $x10, 8 :: (store (s32), align 2) + ; CHECK-NEXT: SW $x3, $x10, 12 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW $x0, $x10, 0 :: (store (s32), align 4) + SW $x1, $x10, 4 :: (store (s32), align 4) + SW $x2, $x10, 8 :: (store (s32), align 2) + SW $x3, $x10, 12 :: (store (s32), align 4) + PseudoRET +... +--- +name: setwmi +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: setwmi + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: QC_SETWMI $x0, $x10, 4, 0 :: (store (s32) into %ir.a), (store (s32) into %ir.b), (store (s32) into %ir.c), (store (s32) into %ir.d) + ; CHECK-NEXT: PseudoRET + SW $x0, $x10, 0 :: (store (s32) into %ir.a, align 4) + SW $x0, $x10, 4 :: (store (s32) into %ir.b, align 4) + SW $x0, $x10, 8 :: (store (s32) into %ir.c, align 4) + SW $x0, $x10, 12 :: (store (s32) into %ir.d, align 4) + PseudoRET +... +--- +name: setwmi_no_pair_move_insn_back +body: | + bb.0: + liveins: $x1, $x2 + ; CHECK-LABEL: name: setwmi_no_pair_move_insn_back + ; CHECK: liveins: $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SW killed $x1, $x2, 12 :: (store (s32)) + ; CHECK-NEXT: QC_SETWMI $x0, $x2, 3, 0 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW killed $x1, $x2, 12 :: (store (s32), align 4) + SW $x0, $x2, 0 :: (store (s32), align 4) + SW $x0, $x2, 4 :: (store (s32), align 4) + SW $x0, $x2, 8 :: (store (s32), align 4) + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi.mir new file mode 100644 index 0000000..971a62d --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi.mir @@ -0,0 +1,460 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=riscv32 -mattr=+xqcilsm -run-pass=riscv-load-store-opt %s -o - | FileCheck %s + +--- | + + define void @pair_two_lw_into_qc_lwmi() nounwind { ret void } + define void @pair_two_lw_into_qc_lwmi_reversed() nounwind { ret void } + define void @pair_two_sw_into_qc_swmi_reversed() nounwind { ret void } + define void @no_pair_if_different_base_regs() nounwind { ret void } + define void @no_pair_if_alignment_lt_4() nounwind { ret void } + define void @pair_two_sw_into_qc_swmi() nounwind { ret void } + define void @no_pair_if_misaligned() nounwind { ret void } + define void @pair_at_upper_boundary_lw() nounwind { ret void } + define void @pair_at_upper_boundary_sw() nounwind { ret void } + define void @no_pair_if_offset_out_of_range_lw() nounwind { ret void } + define void @no_pair_if_offset_out_of_range_sw() nounwind { ret void } + define void @no_pair_if_non_consecutive_regs() nounwind { ret void } + define void @no_pair_if_rd_is_x0_lwmi() nounwind { ret void } + define void @no_pair_if_rd_is_x0_swmi() nounwind { ret void } + define void @pair_if_rd_is_x0_setwmi() nounwind { ret void } + define void @no_pair_if_lw_rd_equals_base() nounwind { ret void } + define void @second_pair_if_no_first_pair_lwmi() nounwind { ret void } + define void @second_pair_if_no_first_pair_swmi() nounwind { ret void } + define void @second_pair_if_no_first_pair_setwmi() nounwind { ret void } + define void @pair_if_not_adjacent() nounwind { ret void } + define void @pair_if_not_adjacent_use() nounwind { ret void } + define void @no_pair_if_not_adjacent_use() nounwind { ret void } + define void @pair_two_sw_into_qc_setwmi() nounwind { ret void } + define void @pair_two_sw_into_qc_setwmi_reversed() nounwind { ret void } + define void @pair_if_not_adjacent_setwmi() nounwind { ret void } +--- +name: pair_two_lw_into_qc_lwmi +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: pair_two_lw_into_qc_lwmi + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x12 = QC_LWMI $x10, 2, 0, implicit-def $x13 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x12 = LW $x10, 0 :: (load (s32), align 4) + $x13 = LW $x10, 4 :: (load (s32), align 4) + PseudoRET + +... +--- +# FIXME: Kill flags are not propagated correctly for the base register +name: pair_two_lw_into_qc_lwmi_reversed +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: pair_two_lw_into_qc_lwmi_reversed + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x12 = QC_LWMI $x10, 2, 0, implicit-def $x13 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x13 = LW $x10, 4 :: (load (s32)) + $x12 = LW killed $x10, 0 :: (load (s32)) + PseudoRET + +... +--- +name: pair_two_sw_into_qc_swmi_reversed +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10, $x12, $x13 + ; CHECK-LABEL: name: pair_two_sw_into_qc_swmi_reversed + ; CHECK: liveins: $x10, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: QC_SWMI killed $x12, $x10, 2, 0, implicit killed $x13 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW killed $x13, $x10, 4 :: (store (s32)) + SW killed $x12, $x10, 0 :: (store (s32)) + PseudoRET + +... +--- +name: no_pair_if_different_base_regs +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10, $x11 + ; CHECK-LABEL: name: no_pair_if_different_base_regs + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x12 = LW $x10, 0 :: (load (s32)) + ; CHECK-NEXT: $x13 = LW $x11, 4 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x12 = LW $x10, 0 :: (load (s32)) + $x13 = LW $x11, 4 :: (load (s32)) + PseudoRET + +... +--- +name: no_pair_if_alignment_lt_4 +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: no_pair_if_alignment_lt_4 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x12 = LW $x10, 0 :: (load (s32)) + ; CHECK-NEXT: $x13 = LW $x10, 3 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x12 = LW $x10, 0 :: (load (s32)) + $x13 = LW $x10, 3 :: (load (s32)) + PseudoRET + +... +--- +name: pair_two_sw_into_qc_swmi +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10, $x12, $x13 + ; CHECK-LABEL: name: pair_two_sw_into_qc_swmi + ; CHECK: liveins: $x10, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: QC_SWMI killed $x12, $x10, 2, 0, implicit killed $x13 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW killed $x12, $x10, 0 :: (store (s32), align 4) + SW killed $x13, $x10, 4 :: (store (s32), align 4) + PseudoRET + +... +--- +name: no_pair_if_misaligned +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: no_pair_if_misaligned + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x12 = LW $x10, 2 :: (load (s32)) + ; CHECK-NEXT: $x13 = LW $x10, 6 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x12 = LW $x10, 2 :: (load (s32), align 4) + $x13 = LW $x10, 6 :: (load (s32), align 4) + PseudoRET + +... +--- +# FIXME: Kill flags are not propagated correctly for the base register +name: pair_at_upper_boundary_lw +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: pair_at_upper_boundary_lw + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x12 = QC_LWMI $x10, 2, 124, implicit-def $x13 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x12 = LW $x10, 124 :: (load (s32), align 4) + $x13 = LW killed $x10, 128 :: (load (s32), align 4) + PseudoRET + +... +--- +# FIXME: Kill flags are not propagated correctly for the base register +name: pair_at_upper_boundary_sw +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10, $x12, $x13 + ; CHECK-LABEL: name: pair_at_upper_boundary_sw + ; CHECK: liveins: $x10, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: QC_SWMI $x12, $x10, 2, 124, implicit $x13 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW $x12, $x10, 124 :: (store (s32), align 4) + SW $x13, killed $x10, 128 :: (store (s32), align 4) + PseudoRET + +... +--- +name: no_pair_if_offset_out_of_range_lw +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: no_pair_if_offset_out_of_range_lw + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x12 = LW $x10, 128 :: (load (s32)) + ; CHECK-NEXT: $x13 = LW $x10, 132 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x12 = LW $x10, 128 :: (load (s32), align 4) + $x13 = LW $x10, 132 :: (load (s32), align 4) + PseudoRET + +... +--- +name: no_pair_if_offset_out_of_range_sw +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10, $x12, $x13 + ; CHECK-LABEL: name: no_pair_if_offset_out_of_range_sw + ; CHECK: liveins: $x10, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SW $x12, $x10, 128 :: (store (s32)) + ; CHECK-NEXT: SW $x13, $x10, 132 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW $x12, $x10, 128 :: (store (s32), align 4) + SW $x13, $x10, 132 :: (store (s32), align 4) + PseudoRET + +... +--- +name: no_pair_if_non_consecutive_regs +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: no_pair_if_non_consecutive_regs + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = LW $x10, 0 :: (load (s32)) + ; CHECK-NEXT: $x13 = LW $x10, 4 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x11 = LW $x10, 0 :: (load (s32), align 4) + $x13 = LW $x10, 4 :: (load (s32), align 4) + PseudoRET + +... +--- +name: no_pair_if_rd_is_x0_lwmi +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: no_pair_if_rd_is_x0_lwmi + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x0 = LW $x10, 0 :: (load (s32)) + ; CHECK-NEXT: $x1 = LW $x10, 4 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x0 = LW $x10, 0 :: (load (s32), align 4) + $x1 = LW $x10, 4 :: (load (s32), align 4) + PseudoRET + +... +--- +name: no_pair_if_rd_is_x0_swmi +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: no_pair_if_rd_is_x0_swmi + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SW $x0, $x10, 0 :: (store (s32)) + ; CHECK-NEXT: SW $x1, $x10, 4 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW $x0, $x10, 0 :: (store (s32), align 4) + SW $x1, $x10, 4 :: (store (s32), align 4) + PseudoRET + +... +--- +name: pair_if_rd_is_x0_setwmi +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: pair_if_rd_is_x0_setwmi + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: QC_SETWMI $x0, $x10, 2, 0 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW $x0, $x10, 0 :: (store (s32), align 4) + SW $x0, $x10, 4 :: (store (s32), align 4) + PseudoRET + +... +--- +name: no_pair_if_lw_rd_equals_base +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: no_pair_if_lw_rd_equals_base + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x10 = LW $x10, 20 :: (load (s32)) + ; CHECK-NEXT: $x11 = LW $x10, 24 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x10 = LW $x10, 20 :: (load (s32), align 4) + $x11 = LW $x10, 24 :: (load (s32), align 4) + PseudoRET + +... +--- +name: second_pair_if_no_first_pair_lwmi +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: second_pair_if_no_first_pair_lwmi + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x0 = LW $x10, 0 :: (load (s32)) + ; CHECK-NEXT: $x1 = QC_LWMI $x10, 2, 4, implicit-def $x2 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x0 = LW $x10, 0 :: (load (s32), align 4) + $x1 = LW $x10, 4 :: (load (s32), align 4) + $x2 = LW $x10, 8 :: (load (s32), align 4) + PseudoRET + +... +--- +name: second_pair_if_no_first_pair_swmi +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: second_pair_if_no_first_pair_swmi + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SW $x0, $x10, 0 :: (store (s32)) + ; CHECK-NEXT: QC_SWMI $x1, $x10, 2, 4, implicit $x2 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW $x0, $x10, 0 :: (store (s32), align 4) + SW $x1, $x10, 4 :: (store (s32), align 4) + SW $x2, $x10, 8 :: (store (s32), align 4) + PseudoRET + +... +--- +name: second_pair_if_no_first_pair_setwmi +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: second_pair_if_no_first_pair_setwmi + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SW $x0, $x10, 0 :: (store (s32)) + ; CHECK-NEXT: QC_SETWMI $x2, $x10, 2, 4 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW $x0, $x10, 0 :: (store (s32), align 4) + SW $x2, $x10, 4 :: (store (s32), align 4) + SW $x2, $x10, 8 :: (store (s32), align 4) + PseudoRET + +... +--- +# FIXME: Kill flags are not propagated correctly for the base register +name: pair_if_not_adjacent +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: pair_if_not_adjacent + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x1 = QC_LWMI $x10, 2, 20, implicit-def $x2 :: (load (s32)) + ; CHECK-NEXT: $x3 = ADDI $x1, 10 + ; CHECK-NEXT: PseudoRET + $x1 = LW $x10, 20 :: (load (s32), align 4) + $x3 = ADDI $x1, 10 + $x2 = LW killed $x10, 24 :: (load (s32), align 4) + PseudoRET + +... +--- +name: pair_if_not_adjacent_use +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10, $x1, $x2 + ; CHECK-LABEL: name: pair_if_not_adjacent_use + ; CHECK: liveins: $x10, $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x2 = ADDI $x2, 10 + ; CHECK-NEXT: QC_SWMI $x1, $x10, 2, 20, implicit $x2 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW $x1, $x10, 20 :: (store (s32), align 4) + $x2 = ADDI $x2, 10 + SW $x2, $x10, 24 :: (store (s32), align 4) + PseudoRET + +... +--- +name: no_pair_if_not_adjacent_use +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10, $x2 + ; CHECK-LABEL: name: no_pair_if_not_adjacent_use + ; CHECK: liveins: $x10, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x1 = LW $x10, 20 :: (load (s32)) + ; CHECK-NEXT: $x1 = ADDI $x1, 10 + ; CHECK-NEXT: SW $x2, $x10, 40 :: (store (s32)) + ; CHECK-NEXT: $x2 = LW $x10, 24 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + $x1 = LW $x10, 20 :: (load (s32), align 4) + $x1 = ADDI $x1, 10 + SW $x2, $x10, 40 :: (store (s32), align 4) + $x2 = LW $x10, 24 :: (load (s32), align 4) + PseudoRET + +... +--- +name: pair_two_sw_into_qc_setwmi +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10, $x1 + ; CHECK-LABEL: name: pair_two_sw_into_qc_setwmi + ; CHECK: liveins: $x10, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: QC_SETWMI $x1, $x10, 2, 20 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW $x1, $x10, 20 :: (store (s32), align 4) + SW $x1, $x10, 24 :: (store (s32), align 4) + PseudoRET + +... +--- +name: pair_two_sw_into_qc_setwmi_reversed +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10, $x2 + ; CHECK-LABEL: name: pair_two_sw_into_qc_setwmi_reversed + ; CHECK: liveins: $x10, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: QC_SETWMI $x2, $x10, 2, 20 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + SW $x2, $x10, 24 :: (store (s32), align 4) + SW $x2, $x10, 20 :: (store (s32), align 4) + PseudoRET + +... +--- +name: pair_if_not_adjacent_setwmi +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10, $x1 + ; CHECK-LABEL: name: pair_if_not_adjacent_setwmi + ; CHECK: liveins: $x10, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: QC_SETWMI killed $x1, $x10, 2, 20 :: (store (s32)) + ; CHECK-NEXT: $x2 = ADDI $x2, 10 + ; CHECK-NEXT: PseudoRET + SW $x1, $x10, 20 :: (store (s32), align 4) + $x2 = ADDI $x2, 10 + SW killed $x1, $x10, 24 :: (store (s32), align 4) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir new file mode 100644 index 0000000..1cdb352 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir @@ -0,0 +1,202 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -mattr=+zcmp -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-ZCMP32 %s +# RUN: llc -mtriple=riscv32 -mattr=+save-restore -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-LIBCALL32 %s +# RUN: llc -mtriple=riscv64 -mattr=+zcmp -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-ZCMP64 %s +# RUN: llc -mtriple=riscv64 -mattr=+save-restore -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-LIBCALL64 %s +# RUN: llc -mtriple=riscv32 -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-ZCMP32 %s +# RUN: llc -mtriple=riscv64 -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-ZCMP64 %s +--- +name: popret_rvlist5 +tracksRegLiveness: true +frameInfo: + maxCallFrameSize: 0 +body: | + bb.0: + ; CHECK-ZCMP32-LABEL: name: popret_rvlist5 + ; CHECK-ZCMP32: liveins: $x1, $x8 + ; CHECK-ZCMP32-NEXT: {{ $}} + ; CHECK-ZCMP32-NEXT: frame-setup CM_PUSH 5, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -4 + ; CHECK-ZCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: frame-destroy CM_POPRET 5, 0, implicit-def $x2, implicit $x2, implicit-def $x1, implicit-def $x8 + ; + ; CHECK-LIBCALL32-LABEL: name: popret_rvlist5 + ; CHECK-LIBCALL32: liveins: $x1, $x8 + ; CHECK-LIBCALL32-NEXT: {{ $}} + ; CHECK-LIBCALL32-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1, implicit $x2, implicit-def $x2, implicit $x1, implicit $x8 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-LIBCALL32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2, implicit-def $x2, implicit-def $x1, implicit-def $x8 + ; + ; CHECK-ZCMP64-LABEL: name: popret_rvlist5 + ; CHECK-ZCMP64: liveins: $x1, $x8 + ; CHECK-ZCMP64-NEXT: {{ $}} + ; CHECK-ZCMP64-NEXT: frame-setup CM_PUSH 5, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -16 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-ZCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: frame-destroy CM_POPRET 5, 0, implicit-def $x2, implicit $x2, implicit-def $x1, implicit-def $x8 + ; + ; CHECK-LIBCALL64-LABEL: name: popret_rvlist5 + ; CHECK-LIBCALL64: liveins: $x1, $x8 + ; CHECK-LIBCALL64-NEXT: {{ $}} + ; CHECK-LIBCALL64-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1, implicit $x2, implicit-def $x2, implicit $x1, implicit $x8 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-LIBCALL64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2, implicit-def $x2, implicit-def $x1, implicit-def $x8 + ; + ; CHECK-NO-ZCMP32-LABEL: name: popret_rvlist5 + ; CHECK-NO-ZCMP32: liveins: $x1, $x8 + ; CHECK-NO-ZCMP32-NEXT: {{ $}} + ; CHECK-NO-ZCMP32-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x1, $x2, 12 :: (store (s32) into %stack.0) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x8, $x2, 8 :: (store (s32) into %stack.1) + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-NO-ZCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x1 = frame-destroy LW $x2, 12 :: (load (s32) from %stack.0) + ; CHECK-NO-ZCMP32-NEXT: $x8 = frame-destroy LW $x2, 8 :: (load (s32) from %stack.1) + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; CHECK-NO-ZCMP32-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NO-ZCMP32-NEXT: PseudoRET + ; + ; CHECK-NO-ZCMP64-LABEL: name: popret_rvlist5 + ; CHECK-NO-ZCMP64: liveins: $x1, $x8 + ; CHECK-NO-ZCMP64-NEXT: {{ $}} + ; CHECK-NO-ZCMP64-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x1, $x2, 8 :: (store (s64) into %stack.0) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x8, $x2, 0 :: (store (s64) into %stack.1) + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-NO-ZCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x1 = frame-destroy LD $x2, 8 :: (load (s64) from %stack.0) + ; CHECK-NO-ZCMP64-NEXT: $x8 = frame-destroy LD $x2, 0 :: (load (s64) from %stack.1) + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; CHECK-NO-ZCMP64-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NO-ZCMP64-NEXT: PseudoRET + $x1 = IMPLICIT_DEF + $x8 = IMPLICIT_DEF + PseudoRET +... +--- +name: popretz_rvlist5 +tracksRegLiveness: true +frameInfo: + maxCallFrameSize: 0 +body: | + bb.0: + ; CHECK-ZCMP32-LABEL: name: popretz_rvlist5 + ; CHECK-ZCMP32: liveins: $x1, $x8 + ; CHECK-ZCMP32-NEXT: {{ $}} + ; CHECK-ZCMP32-NEXT: frame-setup CM_PUSH 5, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -4 + ; CHECK-ZCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: frame-destroy CM_POPRETZ 5, 0, implicit-def $x2, implicit-def $x10, implicit $x2, implicit-def $x1, implicit-def $x8 + ; + ; CHECK-LIBCALL32-LABEL: name: popretz_rvlist5 + ; CHECK-LIBCALL32: liveins: $x1, $x8 + ; CHECK-LIBCALL32-NEXT: {{ $}} + ; CHECK-LIBCALL32-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1, implicit $x2, implicit-def $x2, implicit $x1, implicit $x8 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-LIBCALL32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x10 = ADDI $x0, 0 + ; CHECK-LIBCALL32-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2, implicit-def $x2, implicit-def $x1, implicit-def $x8, implicit $x10 + ; + ; CHECK-ZCMP64-LABEL: name: popretz_rvlist5 + ; CHECK-ZCMP64: liveins: $x1, $x8 + ; CHECK-ZCMP64-NEXT: {{ $}} + ; CHECK-ZCMP64-NEXT: frame-setup CM_PUSH 5, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -16 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-ZCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: frame-destroy CM_POPRETZ 5, 0, implicit-def $x2, implicit-def $x10, implicit $x2, implicit-def $x1, implicit-def $x8 + ; + ; CHECK-LIBCALL64-LABEL: name: popretz_rvlist5 + ; CHECK-LIBCALL64: liveins: $x1, $x8 + ; CHECK-LIBCALL64-NEXT: {{ $}} + ; CHECK-LIBCALL64-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1, implicit $x2, implicit-def $x2, implicit $x1, implicit $x8 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-LIBCALL64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x10 = ADDI $x0, 0 + ; CHECK-LIBCALL64-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2, implicit-def $x2, implicit-def $x1, implicit-def $x8, implicit $x10 + ; + ; CHECK-NO-ZCMP32-LABEL: name: popretz_rvlist5 + ; CHECK-NO-ZCMP32: liveins: $x1, $x8 + ; CHECK-NO-ZCMP32-NEXT: {{ $}} + ; CHECK-NO-ZCMP32-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x1, $x2, 12 :: (store (s32) into %stack.0) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x8, $x2, 8 :: (store (s32) into %stack.1) + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-NO-ZCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x10 = ADDI $x0, 0 + ; CHECK-NO-ZCMP32-NEXT: $x1 = frame-destroy LW $x2, 12 :: (load (s32) from %stack.0) + ; CHECK-NO-ZCMP32-NEXT: $x8 = frame-destroy LW $x2, 8 :: (load (s32) from %stack.1) + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; CHECK-NO-ZCMP32-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NO-ZCMP32-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-NO-ZCMP64-LABEL: name: popretz_rvlist5 + ; CHECK-NO-ZCMP64: liveins: $x1, $x8 + ; CHECK-NO-ZCMP64-NEXT: {{ $}} + ; CHECK-NO-ZCMP64-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x1, $x2, 8 :: (store (s64) into %stack.0) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x8, $x2, 0 :: (store (s64) into %stack.1) + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-NO-ZCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x10 = ADDI $x0, 0 + ; CHECK-NO-ZCMP64-NEXT: $x1 = frame-destroy LD $x2, 8 :: (load (s64) from %stack.0) + ; CHECK-NO-ZCMP64-NEXT: $x8 = frame-destroy LD $x2, 0 :: (load (s64) from %stack.1) + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; CHECK-NO-ZCMP64-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NO-ZCMP64-NEXT: PseudoRET implicit $x10 + $x1 = IMPLICIT_DEF + $x8 = IMPLICIT_DEF + $x10 = COPY $x0 + PseudoRET implicit $x10 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir new file mode 100644 index 0000000..9cc8421 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir @@ -0,0 +1,316 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -mattr=+zcmp -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-ZCMP32 %s +# RUN: llc -mtriple=riscv32 -mattr=+save-restore -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-LIBCALL32 %s +# RUN: llc -mtriple=riscv64 -mattr=+zcmp -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-ZCMP64 %s +# RUN: llc -mtriple=riscv64 -mattr=+save-restore -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-LIBCALL64 %s +# RUN: llc -mtriple=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-ZCMP32 %s +# RUN: llc -mtriple=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-ZCMP64 %s +--- +name: push_rvlist15 +tracksRegLiveness: true +frameInfo: + maxCallFrameSize: 0 +body: | + bb.0: + ; CHECK-ZCMP32-LABEL: name: push_rvlist15 + ; CHECK-ZCMP32: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-ZCMP32-NEXT: {{ $}} + ; CHECK-ZCMP32-NEXT: frame-setup CM_PUSH 15, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8, implicit $x9, implicit $x18, implicit $x19, implicit $x20, implicit $x21, implicit $x22, implicit $x23, implicit $x24, implicit $x25, implicit $x26, implicit $x27 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 64 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -52 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -48 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -44 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -40 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -36 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -32 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -28 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -24 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -20 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -16 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -12 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -8 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -4 + ; CHECK-ZCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: frame-destroy CM_POP 15, 0, implicit-def $x2, implicit $x2, implicit-def $x1, implicit-def $x8, implicit-def $x9, implicit-def $x18, implicit-def $x19, implicit-def $x20, implicit-def $x21, implicit-def $x22, implicit-def $x23, implicit-def $x24, implicit-def $x25, implicit-def $x26, implicit-def $x27 + ; CHECK-ZCMP32-NEXT: PseudoRET + ; + ; CHECK-LIBCALL32-LABEL: name: push_rvlist15 + ; CHECK-LIBCALL32: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-LIBCALL32-NEXT: {{ $}} + ; CHECK-LIBCALL32-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_12 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 64 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -12 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -16 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -20 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -24 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -28 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -32 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -36 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -40 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -44 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -48 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -52 + ; CHECK-LIBCALL32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_12, implicit $x2 + ; + ; CHECK-ZCMP64-LABEL: name: push_rvlist15 + ; CHECK-ZCMP64: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-ZCMP64-NEXT: {{ $}} + ; CHECK-ZCMP64-NEXT: frame-setup CM_PUSH 15, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8, implicit $x9, implicit $x18, implicit $x19, implicit $x20, implicit $x21, implicit $x22, implicit $x23, implicit $x24, implicit $x25, implicit $x26, implicit $x27 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 112 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -104 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -96 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -88 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -80 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -72 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -64 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -56 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -48 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -40 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -32 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -24 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -16 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -8 + ; CHECK-ZCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: frame-destroy CM_POP 15, 0, implicit-def $x2, implicit $x2, implicit-def $x1, implicit-def $x8, implicit-def $x9, implicit-def $x18, implicit-def $x19, implicit-def $x20, implicit-def $x21, implicit-def $x22, implicit-def $x23, implicit-def $x24, implicit-def $x25, implicit-def $x26, implicit-def $x27 + ; CHECK-ZCMP64-NEXT: PseudoRET + ; + ; CHECK-LIBCALL64-LABEL: name: push_rvlist15 + ; CHECK-LIBCALL64: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-LIBCALL64-NEXT: {{ $}} + ; CHECK-LIBCALL64-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_12 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 112 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -24 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -32 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -40 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -48 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -56 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -64 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -72 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -80 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -88 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -96 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -104 + ; CHECK-LIBCALL64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_12, implicit $x2 + ; + ; CHECK-NO-ZCMP32-LABEL: name: push_rvlist15 + ; CHECK-NO-ZCMP32: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-NO-ZCMP32-NEXT: {{ $}} + ; CHECK-NO-ZCMP32-NEXT: $x2 = frame-setup ADDI $x2, -64 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 64 + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x1, $x2, 60 :: (store (s32) into %stack.0) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x8, $x2, 56 :: (store (s32) into %stack.1) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x9, $x2, 52 :: (store (s32) into %stack.2) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x18, $x2, 48 :: (store (s32) into %stack.3) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x19, $x2, 44 :: (store (s32) into %stack.4) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x20, $x2, 40 :: (store (s32) into %stack.5) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x21, $x2, 36 :: (store (s32) into %stack.6) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x22, $x2, 32 :: (store (s32) into %stack.7) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x23, $x2, 28 :: (store (s32) into %stack.8) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x24, $x2, 24 :: (store (s32) into %stack.9) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x25, $x2, 20 :: (store (s32) into %stack.10) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x26, $x2, 16 :: (store (s32) into %stack.11) + ; CHECK-NO-ZCMP32-NEXT: frame-setup SW killed $x27, $x2, 12 :: (store (s32) into %stack.12) + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -12 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -16 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -20 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -24 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -28 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -32 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -36 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -40 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -44 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -48 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -52 + ; CHECK-NO-ZCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x1 = frame-destroy LW $x2, 60 :: (load (s32) from %stack.0) + ; CHECK-NO-ZCMP32-NEXT: $x8 = frame-destroy LW $x2, 56 :: (load (s32) from %stack.1) + ; CHECK-NO-ZCMP32-NEXT: $x9 = frame-destroy LW $x2, 52 :: (load (s32) from %stack.2) + ; CHECK-NO-ZCMP32-NEXT: $x18 = frame-destroy LW $x2, 48 :: (load (s32) from %stack.3) + ; CHECK-NO-ZCMP32-NEXT: $x19 = frame-destroy LW $x2, 44 :: (load (s32) from %stack.4) + ; CHECK-NO-ZCMP32-NEXT: $x20 = frame-destroy LW $x2, 40 :: (load (s32) from %stack.5) + ; CHECK-NO-ZCMP32-NEXT: $x21 = frame-destroy LW $x2, 36 :: (load (s32) from %stack.6) + ; CHECK-NO-ZCMP32-NEXT: $x22 = frame-destroy LW $x2, 32 :: (load (s32) from %stack.7) + ; CHECK-NO-ZCMP32-NEXT: $x23 = frame-destroy LW $x2, 28 :: (load (s32) from %stack.8) + ; CHECK-NO-ZCMP32-NEXT: $x24 = frame-destroy LW $x2, 24 :: (load (s32) from %stack.9) + ; CHECK-NO-ZCMP32-NEXT: $x25 = frame-destroy LW $x2, 20 :: (load (s32) from %stack.10) + ; CHECK-NO-ZCMP32-NEXT: $x26 = frame-destroy LW $x2, 16 :: (load (s32) from %stack.11) + ; CHECK-NO-ZCMP32-NEXT: $x27 = frame-destroy LW $x2, 12 :: (load (s32) from %stack.12) + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x9 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x18 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x19 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x20 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x21 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x22 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x23 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x24 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x25 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x26 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION restore $x27 + ; CHECK-NO-ZCMP32-NEXT: $x2 = frame-destroy ADDI $x2, 64 + ; CHECK-NO-ZCMP32-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NO-ZCMP32-NEXT: PseudoRET + ; + ; CHECK-NO-ZCMP64-LABEL: name: push_rvlist15 + ; CHECK-NO-ZCMP64: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-NO-ZCMP64-NEXT: {{ $}} + ; CHECK-NO-ZCMP64-NEXT: $x2 = frame-setup ADDI $x2, -112 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 112 + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x1, $x2, 104 :: (store (s64) into %stack.0) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x8, $x2, 96 :: (store (s64) into %stack.1) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x9, $x2, 88 :: (store (s64) into %stack.2) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x18, $x2, 80 :: (store (s64) into %stack.3) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x19, $x2, 72 :: (store (s64) into %stack.4) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x20, $x2, 64 :: (store (s64) into %stack.5) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x21, $x2, 56 :: (store (s64) into %stack.6) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x22, $x2, 48 :: (store (s64) into %stack.7) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x23, $x2, 40 :: (store (s64) into %stack.8) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x24, $x2, 32 :: (store (s64) into %stack.9) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x25, $x2, 24 :: (store (s64) into %stack.10) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x26, $x2, 16 :: (store (s64) into %stack.11) + ; CHECK-NO-ZCMP64-NEXT: frame-setup SD killed $x27, $x2, 8 :: (store (s64) into %stack.12) + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -24 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -32 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -40 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -48 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -56 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -64 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -72 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -80 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -88 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -96 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -104 + ; CHECK-NO-ZCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x1 = frame-destroy LD $x2, 104 :: (load (s64) from %stack.0) + ; CHECK-NO-ZCMP64-NEXT: $x8 = frame-destroy LD $x2, 96 :: (load (s64) from %stack.1) + ; CHECK-NO-ZCMP64-NEXT: $x9 = frame-destroy LD $x2, 88 :: (load (s64) from %stack.2) + ; CHECK-NO-ZCMP64-NEXT: $x18 = frame-destroy LD $x2, 80 :: (load (s64) from %stack.3) + ; CHECK-NO-ZCMP64-NEXT: $x19 = frame-destroy LD $x2, 72 :: (load (s64) from %stack.4) + ; CHECK-NO-ZCMP64-NEXT: $x20 = frame-destroy LD $x2, 64 :: (load (s64) from %stack.5) + ; CHECK-NO-ZCMP64-NEXT: $x21 = frame-destroy LD $x2, 56 :: (load (s64) from %stack.6) + ; CHECK-NO-ZCMP64-NEXT: $x22 = frame-destroy LD $x2, 48 :: (load (s64) from %stack.7) + ; CHECK-NO-ZCMP64-NEXT: $x23 = frame-destroy LD $x2, 40 :: (load (s64) from %stack.8) + ; CHECK-NO-ZCMP64-NEXT: $x24 = frame-destroy LD $x2, 32 :: (load (s64) from %stack.9) + ; CHECK-NO-ZCMP64-NEXT: $x25 = frame-destroy LD $x2, 24 :: (load (s64) from %stack.10) + ; CHECK-NO-ZCMP64-NEXT: $x26 = frame-destroy LD $x2, 16 :: (load (s64) from %stack.11) + ; CHECK-NO-ZCMP64-NEXT: $x27 = frame-destroy LD $x2, 8 :: (load (s64) from %stack.12) + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x9 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x18 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x19 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x20 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x21 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x22 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x23 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x24 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x25 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x26 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION restore $x27 + ; CHECK-NO-ZCMP64-NEXT: $x2 = frame-destroy ADDI $x2, 112 + ; CHECK-NO-ZCMP64-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NO-ZCMP64-NEXT: PseudoRET + $x1 = IMPLICIT_DEF + $x8 = IMPLICIT_DEF + $x9 = IMPLICIT_DEF + $x18 = IMPLICIT_DEF + $x19 = IMPLICIT_DEF + $x20 = IMPLICIT_DEF + $x21 = IMPLICIT_DEF + $x22 = IMPLICIT_DEF + $x23 = IMPLICIT_DEF + $x24 = IMPLICIT_DEF + $x25 = IMPLICIT_DEF + $x26 = IMPLICIT_DEF + $x27 = IMPLICIT_DEF + PseudoRET +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir new file mode 100644 index 0000000..979b8a4 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir @@ -0,0 +1,161 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 +# REQUIRES: asserts +# RUN: llc %s -o - -mtriple=riscv32 -mattr=+zcmp -target-abi ilp32 -run-pass=prologepilog \ +# RUN: -simplify-mir -verify-machineinstrs | FileCheck %s + +--- | + define hidden void @f(fp128 %a) local_unnamed_addr #0 { + entry: + %0 = bitcast fp128 %a to i128 + %and.i = lshr i128 %0, 112 + %1 = trunc i128 %and.i to i32 + %2 = and i32 %1, 32767 + %or.i = or i128 poison, 5192296858534827628530496329220096 + br label %if.end.i + + if.end.i: ; preds = %entry + br i1 poison, label %exit, label %if.then12.i + + if.then12.i: ; preds = %if.end.i + %sub13.i = sub nuw nsw i32 16495, %2 + %sh_prom.i = zext i32 %sub13.i to i128 + %shr14.i = lshr i128 %or.i, %sh_prom.i + %conv15.i = trunc i128 %shr14.i to i32 + br label %exit + + exit: ; preds = %if.then12.i, %if.end.i + %retval.0.i = phi i32 [ %conv15.i, %if.then12.i ], [ -1, %if.end.i ] + ret void + } +... +--- +name: f +alignment: 2 +tracksRegLiveness: true +tracksDebugUserValues: true +liveins: + - { reg: '$x10' } +frameInfo: + maxAlignment: 1 + localFrameSize: 32 + savePoint: + - point: '%bb.2' + restorePoint: + - point: '%bb.2' +stack: + - { id: 0, size: 32, alignment: 1, local-offset: -32 } +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; CHECK-LABEL: name: f + ; CHECK: bb.0.entry: + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $x10 = ADDI $x0, -1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.if.end.i: + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BNE $x0, $x0, %bb.3 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.if.then12.i: + ; CHECK-NEXT: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 32 + ; CHECK-NEXT: SB $x0, $x2, 31 :: (store (s8) into %stack.0 + 31) + ; CHECK-NEXT: SB $x0, $x2, 30 :: (store (s8) into %stack.0 + 30) + ; CHECK-NEXT: SB $x0, $x2, 29 :: (store (s8) into %stack.0 + 29) + ; CHECK-NEXT: SB $x0, $x2, 28 :: (store (s8) into %stack.0 + 28) + ; CHECK-NEXT: SB $x0, $x2, 27 :: (store (s8) into %stack.0 + 27) + ; CHECK-NEXT: SB $x0, $x2, 26 :: (store (s8) into %stack.0 + 26) + ; CHECK-NEXT: SB $x0, $x2, 25 :: (store (s8) into %stack.0 + 25) + ; CHECK-NEXT: SB $x0, $x2, 24 :: (store (s8) into %stack.0 + 24) + ; CHECK-NEXT: SB $x0, $x2, 23 :: (store (s8) into %stack.0 + 23) + ; CHECK-NEXT: SB $x0, $x2, 22 :: (store (s8) into %stack.0 + 22) + ; CHECK-NEXT: SB $x0, $x2, 21 :: (store (s8) into %stack.0 + 21) + ; CHECK-NEXT: SB $x0, $x2, 20 :: (store (s8) into %stack.0 + 20) + ; CHECK-NEXT: SB $x0, $x2, 19 :: (store (s8) into %stack.0 + 19) + ; CHECK-NEXT: SB $x0, $x2, 18 :: (store (s8) into %stack.0 + 18) + ; CHECK-NEXT: SB $x0, $x2, 17 :: (store (s8) into %stack.0 + 17) + ; CHECK-NEXT: SB $x0, $x2, 16 :: (store (s8) into %stack.0 + 16) + ; CHECK-NEXT: SB renamable $x10, $x2, 0 :: (store (s8) into %stack.0) + ; CHECK-NEXT: SB renamable $x10, $x2, 4 :: (store (s8) into %stack.0 + 4) + ; CHECK-NEXT: renamable $x11 = SRLI renamable $x10, 24 + ; CHECK-NEXT: SB renamable $x11, $x2, 3 :: (store (s8) into %stack.0 + 3) + ; CHECK-NEXT: renamable $x12 = SRLI renamable $x10, 16 + ; CHECK-NEXT: SB renamable $x12, $x2, 2 :: (store (s8) into %stack.0 + 2) + ; CHECK-NEXT: renamable $x13 = SRLI renamable $x10, 8 + ; CHECK-NEXT: SB renamable $x13, $x2, 1 :: (store (s8) into %stack.0 + 1) + ; CHECK-NEXT: SB renamable $x10, $x2, 8 :: (store (s8) into %stack.0 + 8) + ; CHECK-NEXT: SB renamable $x11, $x2, 7 :: (store (s8) into %stack.0 + 7) + ; CHECK-NEXT: SB renamable $x12, $x2, 6 :: (store (s8) into %stack.0 + 6) + ; CHECK-NEXT: SB renamable $x13, $x2, 5 :: (store (s8) into %stack.0 + 5) + ; CHECK-NEXT: SB killed renamable $x10, $x2, 12 :: (store (s8) into %stack.0 + 12) + ; CHECK-NEXT: SB renamable $x11, $x2, 11 :: (store (s8) into %stack.0 + 11) + ; CHECK-NEXT: SB renamable $x12, $x2, 10 :: (store (s8) into %stack.0 + 10) + ; CHECK-NEXT: SB renamable $x13, $x2, 9 :: (store (s8) into %stack.0 + 9) + ; CHECK-NEXT: SB killed renamable $x11, $x2, 15 :: (store (s8) into %stack.0 + 15) + ; CHECK-NEXT: SB killed renamable $x12, $x2, 14 :: (store (s8) into %stack.0 + 14) + ; CHECK-NEXT: SB killed renamable $x13, $x2, 13 :: (store (s8) into %stack.0 + 13) + ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 32 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: PseudoRET + bb.0.entry: + liveins: $x10 + + renamable $x10 = ADDI $x0, -1 + + bb.1.if.end.i: + liveins: $x10 + + BNE $x0, $x0, %bb.3 + PseudoBR %bb.2 + + bb.2.if.then12.i: + liveins: $x10 + + SB $x0, %stack.0, 31 :: (store (s8) into %stack.0 + 31) + SB $x0, %stack.0, 30 :: (store (s8) into %stack.0 + 30) + SB $x0, %stack.0, 29 :: (store (s8) into %stack.0 + 29) + SB $x0, %stack.0, 28 :: (store (s8) into %stack.0 + 28) + SB $x0, %stack.0, 27 :: (store (s8) into %stack.0 + 27) + SB $x0, %stack.0, 26 :: (store (s8) into %stack.0 + 26) + SB $x0, %stack.0, 25 :: (store (s8) into %stack.0 + 25) + SB $x0, %stack.0, 24 :: (store (s8) into %stack.0 + 24) + SB $x0, %stack.0, 23 :: (store (s8) into %stack.0 + 23) + SB $x0, %stack.0, 22 :: (store (s8) into %stack.0 + 22) + SB $x0, %stack.0, 21 :: (store (s8) into %stack.0 + 21) + SB $x0, %stack.0, 20 :: (store (s8) into %stack.0 + 20) + SB $x0, %stack.0, 19 :: (store (s8) into %stack.0 + 19) + SB $x0, %stack.0, 18 :: (store (s8) into %stack.0 + 18) + SB $x0, %stack.0, 17 :: (store (s8) into %stack.0 + 17) + SB $x0, %stack.0, 16 :: (store (s8) into %stack.0 + 16) + SB renamable $x10, %stack.0, 0 :: (store (s8) into %stack.0) + SB renamable $x10, %stack.0, 4 :: (store (s8) into %stack.0 + 4) + renamable $x11 = SRLI renamable $x10, 24 + SB renamable $x11, %stack.0, 3 :: (store (s8) into %stack.0 + 3) + renamable $x12 = SRLI renamable $x10, 16 + SB renamable $x12, %stack.0, 2 :: (store (s8) into %stack.0 + 2) + renamable $x13 = SRLI renamable $x10, 8 + SB renamable $x13, %stack.0, 1 :: (store (s8) into %stack.0 + 1) + SB renamable $x10, %stack.0, 8 :: (store (s8) into %stack.0 + 8) + SB renamable $x11, %stack.0, 7 :: (store (s8) into %stack.0 + 7) + SB renamable $x12, %stack.0, 6 :: (store (s8) into %stack.0 + 6) + SB renamable $x13, %stack.0, 5 :: (store (s8) into %stack.0 + 5) + SB killed renamable $x10, %stack.0, 12 :: (store (s8) into %stack.0 + 12) + SB renamable $x11, %stack.0, 11 :: (store (s8) into %stack.0 + 11) + SB renamable $x12, %stack.0, 10 :: (store (s8) into %stack.0 + 10) + SB renamable $x13, %stack.0, 9 :: (store (s8) into %stack.0 + 9) + SB killed renamable $x11, %stack.0, 15 :: (store (s8) into %stack.0 + 15) + SB killed renamable $x12, %stack.0, 14 :: (store (s8) into %stack.0 + 14) + SB killed renamable $x13, %stack.0, 13 :: (store (s8) into %stack.0 + 13) + + bb.3.exit: + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/zdinx-large-spill.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/zdinx-large-spill.mir new file mode 100644 index 0000000..f8b2b54 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/zdinx-large-spill.mir @@ -0,0 +1,82 @@ +# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +# RUN: llc %s -mtriple=riscv32 -mattr=+zdinx -start-before=prologepilog -o - | FileCheck %s + +# We want to make sure eliminateFrameIndex doesn't fold sp+2044 as an offset in +# a GPR pair spill/reload instruction. When we split the pair spill, we would be +# unable to add 4 to the immediate without overflowing simm12. + +--- | + define void @foo() { + ; CHECK-LABEL: foo: + ; CHECK: # %bb.0: + ; CHECK-NEXT: addi sp, sp, -2048 + ; CHECK-NEXT: addi sp, sp, -32 + ; CHECK-NEXT: .cfi_def_cfa_offset 2080 + ; CHECK-NEXT: lui t0, 1 + ; CHECK-NEXT: add t0, sp, t0 + ; CHECK-NEXT: sw a0, -2024(t0) # 4-byte Folded Spill + ; CHECK-NEXT: sw a1, -2020(t0) # 4-byte Folded Spill + ; CHECK-NEXT: lui a0, 1 + ; CHECK-NEXT: add a0, sp, a0 + ; CHECK-NEXT: sw a2, -2032(a0) # 4-byte Folded Spill + ; CHECK-NEXT: sw a3, -2028(a0) # 4-byte Folded Spill + ; CHECK-NEXT: lui a0, 1 + ; CHECK-NEXT: add a0, sp, a0 + ; CHECK-NEXT: sw a4, -2040(a0) # 4-byte Folded Spill + ; CHECK-NEXT: sw a5, -2036(a0) # 4-byte Folded Spill + ; CHECK-NEXT: addi a0, sp, 2044 + ; CHECK-NEXT: sw a6, 0(a0) # 4-byte Folded Spill + ; CHECK-NEXT: sw a7, 4(a0) # 4-byte Folded Spill + ; CHECK-NEXT: lui a0, 1 + ; CHECK-NEXT: add a0, sp, a0 + ; CHECK-NEXT: lw a1, -2020(a0) # 4-byte Folded Reload + ; CHECK-NEXT: lw a0, -2024(a0) # 4-byte Folded Reload + ; CHECK-NEXT: lui a0, 1 + ; CHECK-NEXT: add a0, sp, a0 + ; CHECK-NEXT: lw a2, -2032(a0) # 4-byte Folded Reload + ; CHECK-NEXT: lw a3, -2028(a0) # 4-byte Folded Reload + ; CHECK-NEXT: lui a0, 1 + ; CHECK-NEXT: add a0, sp, a0 + ; CHECK-NEXT: lw a4, -2040(a0) # 4-byte Folded Reload + ; CHECK-NEXT: lw a5, -2036(a0) # 4-byte Folded Reload + ; CHECK-NEXT: addi a0, sp, 2044 + ; CHECK-NEXT: lw a6, 0(a0) # 4-byte Folded Reload + ; CHECK-NEXT: lw a7, 4(a0) # 4-byte Folded Reload + ; CHECK-NEXT: addi sp, sp, 2032 + ; CHECK-NEXT: addi sp, sp, 48 + ; CHECK-NEXT: .cfi_def_cfa_offset 0 + ; CHECK-NEXT: ret + ret void + } +... +--- +name: foo +tracksRegLiveness: true +tracksDebugUserValues: true +frameInfo: + maxAlignment: 4 +stack: + - { id: 0, type: spill-slot, size: 8, alignment: 4 } + - { id: 1, type: spill-slot, size: 8, alignment: 4 } + - { id: 2, type: spill-slot, size: 8, alignment: 4 } + - { id: 3, type: spill-slot, size: 4, alignment: 4 } + - { id: 4, type: spill-slot, size: 8, alignment: 4 } + - { id: 5, type: spill-slot, size: 2028, alignment: 4 } +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0: + liveins: $x10_x11, $x12_x13, $x14_x15, $x16_x17 + + PseudoRV32ZdinxSD killed renamable $x10_x11, %stack.0, 0 :: (store (s64) into %stack.0, align 4) + PseudoRV32ZdinxSD killed renamable $x12_x13, %stack.1, 0 :: (store (s64) into %stack.1, align 4) + PseudoRV32ZdinxSD killed renamable $x14_x15, %stack.2, 0 :: (store (s64) into %stack.2, align 4) + PseudoRV32ZdinxSD killed renamable $x16_x17, %stack.4, 0 :: (store (s64) into %stack.4, align 4) + renamable $x10_x11 = PseudoRV32ZdinxLD %stack.0, 0 :: (load (s64) from %stack.0, align 4) + renamable $x12_x13 = PseudoRV32ZdinxLD %stack.1, 0 :: (load (s64) from %stack.1, align 4) + renamable $x14_x15 = PseudoRV32ZdinxLD %stack.2, 0 :: (load (s64) from %stack.2, align 4) + renamable $x16_x17 = PseudoRV32ZdinxLD %stack.4, 0 :: (load (s64) from %stack.4, align 4) + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/zilsd-csr-duplicate.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/zilsd-csr-duplicate.mir new file mode 100644 index 0000000..5fda434 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/zilsd-csr-duplicate.mir @@ -0,0 +1,135 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple riscv32 -mattr=+zcmp,+zilsd --run-pass=prologepilog %s -verify-machineinstrs -o - \ +# RUN: | FileCheck %s + +--- | + declare i32 @foo() + declare void @bar() + + ; Function Attrs: nounwind optsize + define void @zilsd_dup_csr(ptr %p, i32 %a) #1 { + entry: + %call1 = call i32 @foo() + %0 = alloca i8, i32 %a, align 8 + store ptr %0, ptr %p, align 8 + tail call void @bar() + ret void + } + +... +--- +name: zilsd_dup_csr +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +noPhis: true +isSSA: false +noVRegs: true +hasFakeUses: false +callsEHReturn: false +callsUnwindInit: false +hasEHContTarget: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: true +registers: [] +liveins: + - { reg: '$x10', virtual-reg: '' } + - { reg: '$x11', virtual-reg: '' } +calleeSavedRegisters: [ '$x1', '$x8', '$x9', '$x18', '$x19', '$x20', '$x21', + '$x22', '$x23', '$x24', '$x25', '$x26', '$x27', + '$x8_x9', '$x18_x19', '$x20_x21', '$x22_x23', '$x24_x25', + '$x26_x27' ] +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: true + hasCalls: true + framePointerPolicy: none + stackProtector: '' + functionContext: '' + maxCallFrameSize: 0 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: true + isCalleeSavedInfoValid: false + localFrameSize: 0 +fixedStack: [] +stack: + - { id: 0, name: '', type: variable-sized, offset: 0, alignment: 1, stack-id: default, + callee-saved-register: '', callee-saved-restored: true, local-offset: 0, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: zilsd_dup_csr + ; CHECK: liveins: $x10, $x11, $x1, $x18_x19 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CM_PUSH 4, 16, implicit-def $x2, implicit $x2, implicit $x1 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-NEXT: frame-setup SD_RV32 killed $x8_x9, $x2, 8 :: (store (s64) into %stack.1) + ; CHECK-NEXT: frame-setup SD_RV32 killed $x18_x19, $x2, 0 :: (store (s64) into %stack.2) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -28 + ; CHECK-NEXT: $x8 = frame-setup ADDI $x2, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0 + ; CHECK-NEXT: renamable $x9 = COPY $x11 + ; CHECK-NEXT: renamable $x18 = COPY $x10 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def dead $x1, implicit-def $x2, implicit-def dead $x10 + ; CHECK-NEXT: renamable $x9 = nuw ADDI killed renamable $x9, 15 + ; CHECK-NEXT: renamable $x9 = ANDI killed renamable $x9, -16 + ; CHECK-NEXT: renamable $x10 = SUB $x2, killed renamable $x9 + ; CHECK-NEXT: $x2 = COPY renamable $x10 + ; CHECK-NEXT: SW killed renamable $x10, killed renamable $x18, 0 :: (store (s32) into %ir.p, align 8) + ; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -32 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 32 + ; CHECK-NEXT: $x8_x9 = frame-destroy LD_RV32 $x2, 8 :: (load (s64) from %stack.1) + ; CHECK-NEXT: $x18_x19 = frame-destroy LD_RV32 $x2, 0 :: (load (s64) from %stack.2) + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x9 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x18 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x19 + ; CHECK-NEXT: frame-destroy CM_POP 4, 16, implicit-def $x2, implicit $x2, implicit-def $x1 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; CHECK-NEXT: PseudoTAIL target-flags(riscv-call) @bar, csr_ilp32_lp64, implicit $x2 + renamable $x9 = COPY $x11 + renamable $x18 = COPY $x10 + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def dead $x1, implicit-def $x2, implicit-def dead $x10 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + renamable $x9 = nuw ADDI killed renamable $x9, 15 + renamable $x9 = ANDI killed renamable $x9, -16 + renamable $x10 = SUB $x2, killed renamable $x9 + $x2 = COPY renamable $x10 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + SW killed renamable $x10, killed renamable $x18, 0 :: (store (s32) into %ir.p, align 8) + PseudoTAIL target-flags(riscv-call) @bar, csr_ilp32_lp64, implicit $x2 +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-postra.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-postra.mir new file mode 100644 index 0000000..c27cb25 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-postra.mir @@ -0,0 +1,216 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# NOTE: Test expansion of PseudoLD_RV32_OPT/PseudoSD_RV32_OPT after register allocation +# RUN: llc -mtriple=riscv32 -mattr=+zilsd -run-pass riscv-load-store-opt %s -o - | FileCheck %s +--- | + define i32 @expand_pseudold_valid(ptr %0) { + %2 = load i32, ptr %0, align 4 + %3 = getelementptr inbounds i32, ptr %0, i32 1 + %4 = load i32, ptr %3, align 4 + %5 = add i32 %2, %4 + ret i32 %5 + } + + define void @expand_pseudosd_valid(ptr %0, i32 %1, i32 %2) { + store i32 %1, ptr %0, align 4 + %4 = getelementptr inbounds i32, ptr %0, i32 1 + store i32 %2, ptr %4, align 4 + ret void + } + + define i32 @expand_pseudold_invalid_pair(ptr %0) { + %2 = load i32, ptr %0, align 4 + %3 = getelementptr inbounds i32, ptr %0, i32 1 + %4 = load i32, ptr %3, align 4 + %5 = add i32 %2, %4 + ret i32 %5 + } + + define void @expand_pseudosd_invalid_pair(ptr %0, i32 %1, i32 %2) { + store i32 %1, ptr %0, align 4 + %4 = getelementptr inbounds i32, ptr %0, i32 1 + store i32 %2, ptr %4, align 4 + ret void + } + + define void @store_zero_combine_valid(ptr %0) { + store i32 0, ptr %0, align 8 + %2 = getelementptr inbounds i32, ptr %0, i32 1 + store i32 0, ptr %2, align 8 + ret void + } + + define void @store_zero_combine_invalid(ptr %0, i32 %1) { + store i32 %1, ptr %0, align 8 + %3 = getelementptr inbounds i32, ptr %0, i32 1 + store i32 0, ptr %3, align 8 + ret void + } + + @global_array = external global [100 x i32] + + define i32 @expand_pseudold_invalid_symbolic() { + ret i32 0 + } + + define i32 @overlapped_first_reg_base_reg() { + ret i32 0 + } +... +--- +# Valid consecutive even/odd register pair - should expand to LD_RV32 +name: expand_pseudold_valid +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + + ; PseudoLD_RV32_OPT with consecutive even/odd registers (x12, x13) + ; CHECK-LABEL: name: expand_pseudold_valid + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x12_x13 = LD_RV32 killed $x10, 0 + ; CHECK-NEXT: $x10 = ADD killed $x12, killed $x13 + ; CHECK-NEXT: PseudoRET implicit $x10 + $x12, $x13 = PseudoLD_RV32_OPT killed $x10, 0 + $x10 = ADD killed $x12, killed $x13 + PseudoRET implicit $x10 + +... +--- +# Valid consecutive even/odd register pair - should expand to SD_RV32 +name: expand_pseudosd_valid +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10, $x12, $x13 + + ; PseudoSD_RV32_OPT with consecutive even/odd registers (x12, x13) + ; CHECK-LABEL: name: expand_pseudosd_valid + ; CHECK: liveins: $x10, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SD_RV32 killed $x12_x13, killed $x10, 0 + ; CHECK-NEXT: PseudoRET + PseudoSD_RV32_OPT killed $x12, killed $x13, killed $x10, 0 + PseudoRET + +... +--- +# Invalid register pair (not consecutive) - should decompose back to LW +name: expand_pseudold_invalid_pair +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + + ; PseudoLD_RV32_OPT with non-consecutive registers (x11, x13) + ; Should decompose back to two LW instructions + ; CHECK-LABEL: name: expand_pseudold_invalid_pair + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = LW $x10, 0 + ; CHECK-NEXT: $x13 = LW killed $x10, 4 + ; CHECK-NEXT: $x10 = ADD killed $x11, killed $x13 + ; CHECK-NEXT: PseudoRET implicit $x10 + $x11, $x13 = PseudoLD_RV32_OPT killed $x10, 0 + $x10 = ADD killed $x11, killed $x13 + PseudoRET implicit $x10 + +... +--- +# Invalid register pair (not even/odd) - should decompose back to SW +name: expand_pseudosd_invalid_pair +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10, $x11, $x14 + + ; PseudoSD_RV32_OPT with non-consecutive registers (x11, x14) + ; Should decompose back to two SW instructions + ; CHECK-LABEL: name: expand_pseudosd_invalid_pair + ; CHECK: liveins: $x10, $x11, $x14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SW killed $x11, $x10, 0 + ; CHECK-NEXT: SW killed $x14, killed $x10, 4 + ; CHECK-NEXT: PseudoRET + PseudoSD_RV32_OPT killed $x11, killed $x14, killed $x10, 0 + PseudoRET + +... +--- +# Test store zero combinations - zeros don't need consecutive pairs +name: store_zero_combine_valid +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: store_zero_combine_valid + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SD_RV32 $x0_pair, killed $x10, 0 + ; CHECK-NEXT: PseudoRET + PseudoSD_RV32_OPT $x0, $x0, killed $x10, 0 + PseudoRET + +... +--- +# Test store zero base combinations - zero can't be first register unless both +# are zeros +name: store_zero_combine_invalid +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + ; CHECK-LABEL: name: store_zero_combine_invalid + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SW killed $x0, $x10, 0 + ; CHECK-NEXT: SW killed $x1, killed $x10, 4 + ; CHECK-NEXT: PseudoRET + PseudoSD_RV32_OPT killed $x0, killed $x1, killed $x10, 0 + PseudoRET + +... +--- +# Test invalid register pair with symbolic operands - should split back to LW +name: expand_pseudold_invalid_symbolic +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + + ; PseudoLD_RV32_OPT with symbolic operand and non-consecutive registers (x11, x14) + ; Should decompose back to two LW instructions preserving symbolic references + ; CHECK-LABEL: name: expand_pseudold_invalid_symbolic + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x11 = LW $x10, target-flags(riscv-lo) @global_array + ; CHECK-NEXT: $x14 = LW killed $x10, target-flags(riscv-lo) @global_array + 4 + ; CHECK-NEXT: $x10 = ADD killed $x11, killed $x14 + ; CHECK-NEXT: PseudoRET implicit $x10 + $x11, $x14 = PseudoLD_RV32_OPT killed $x10, target-flags(riscv-lo) @global_array + $x10 = ADD killed $x11, killed $x14 + PseudoRET implicit $x10 + +... +--- +# Test overlapped first reg and base reg - should split back to LW +name: overlapped_first_reg_base_reg +tracksRegLiveness: false +body: | + bb.0: + liveins: $x10 + + ; PseudoLD_RV32_OPT with first destination register overlapping base register ($x11) + ; Should decompose back to two LW instructions when first reg overlaps base reg + ; CHECK-LABEL: name: overlapped_first_reg_base_reg + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x14 = LW $x11, 4 + ; CHECK-NEXT: $x11 = LW killed $x11, 0 + ; CHECK-NEXT: $x10 = ADD killed $x11, killed $x14 + ; CHECK-NEXT: PseudoRET implicit $x10 + $x11, $x14 = PseudoLD_RV32_OPT killed $x11, 0 + $x10 = ADD killed $x11, killed $x14 + PseudoRET implicit $x10 + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir new file mode 100644 index 0000000..20dc3a9 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir @@ -0,0 +1,1378 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv32 -mattr=+zilsd -run-pass riscv-prera-zilsd-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv32 -mattr=+zilsd,+zilsd-word-align -run-pass riscv-prera-zilsd-opt %s -o - | FileCheck %s --check-prefix=CHECK-4BYTE +--- | + declare void @external_func() + + define i32 @basic_load_combine(ptr %0) { + %2 = load i32, ptr %0, align 4 + %3 = getelementptr inbounds i32, ptr %0, i32 1 + %4 = load i32, ptr %3, align 4 + %5 = add i32 %2, %4 + ret i32 %5 + } + + define void @basic_store_combine(ptr %0, i32 %1, i32 %2) { + store i32 %1, ptr %0, align 4 + %4 = getelementptr inbounds i32, ptr %0, i32 1 + store i32 %2, ptr %4, align 4 + ret void + } + + define void @basic_store_zero_combine(ptr %0, i32 %1, i32 %2) { + store i32 0, ptr %0, align 4 + %4 = getelementptr inbounds i32, ptr %0, i32 1 + store i32 0, ptr %4, align 4 + ret void + } + + define i32 @basic_load_combine_8_byte_aligned(ptr %0) { + %2 = load i32, ptr %0, align 8 + %3 = getelementptr inbounds i32, ptr %0, i32 1 + %4 = load i32, ptr %3, align 4 + %5 = add i32 %2, %4 + ret i32 %5 + } + + define void @basic_store_combine_8_byte_aligned(ptr %0, i32 %1, i32 %2) { + store i32 %1, ptr %0, align 8 + %4 = getelementptr inbounds i32, ptr %0, i32 1 + store i32 %2, ptr %4, align 4 + ret void + } + + + define i32 @non_consecutive_offsets(ptr %0) { + %2 = load i32, ptr %0, align 4 + %3 = getelementptr inbounds i32, ptr %0, i32 2 + %4 = load i32, ptr %3, align 4 + %5 = add i32 %2, %4 + ret i32 %5 + } + + define i32 @different_base_regs(ptr %0, ptr %1) { + %3 = load i32, ptr %0, align 4 + %4 = getelementptr inbounds i32, ptr %1, i32 1 + %5 = load i32, ptr %4, align 4 + %6 = add i32 %3, %5 + ret i32 %6 + } + + define i32 @call_blocks_optimization(ptr %0) { + %2 = load i32, ptr %0, align 4 + call void @external_func() + %3 = getelementptr inbounds i32, ptr %0, i32 1 + %4 = load i32, ptr %3, align 4 + %5 = add i32 %2, %4 + ret i32 %5 + } + + define i32 @terminator_blocks_optimization(ptr %0, i32 %1) { + %3 = load i32, ptr %0, align 4 + %4 = icmp eq i32 %1, %3 + br i1 %4, label %5, label %5 + 5: + %6 = getelementptr inbounds i32, ptr %0, i32 1 + %7 = load i32, ptr %6, align 4 + %8 = add i32 %3, %7 + ret i32 %8 + } + + define i32 @memory_aliasing(ptr %0, i32 %1) { + %3 = load i32, ptr %0, align 4 + %4 = getelementptr inbounds i32, ptr %0, i32 2 + store i32 %1, ptr %4, align 4 + %5 = getelementptr inbounds i32, ptr %0, i32 1 + %6 = load i32, ptr %5, align 4 + %7 = add i32 %3, %6 + ret i32 %7 + } + + define i32 @multiple_pairs(ptr %0, ptr %1) { + %3 = load i32, ptr %0, align 4 + %4 = getelementptr inbounds i32, ptr %0, i32 1 + %5 = load i32, ptr %4, align 4 + %6 = add i32 %3, %5 + %7 = getelementptr inbounds i32, ptr %1, i32 2 + %8 = load i32, ptr %7, align 4 + %9 = getelementptr inbounds i32, ptr %1, i32 3 + %10 = load i32, ptr %9, align 4 + %11 = add i32 %8, %10 + %12 = add i32 %6, %11 + ret i32 %12 + } + + define i32 @many_loads(ptr %0) { + %2 = getelementptr inbounds i32, ptr %0, i32 4 + %3 = load i32, ptr %2, align 4 + %4 = getelementptr inbounds i32, ptr %0, i32 5 + %5 = load i32, ptr %4, align 4 + %6 = getelementptr inbounds i32, ptr %0, i32 6 + %7 = load i32, ptr %6, align 4 + %8 = getelementptr inbounds i32, ptr %0, i32 7 + %9 = load i32, ptr %8, align 4 + %10 = getelementptr inbounds i32, ptr %0, i32 8 + %11 = load i32, ptr %10, align 4 + %12 = getelementptr inbounds i32, ptr %0, i32 9 + %13 = load i32, ptr %12, align 4 + %14 = getelementptr inbounds i32, ptr %0, i32 10 + %15 = load i32, ptr %14, align 4 + %16 = getelementptr inbounds i32, ptr %0, i32 11 + %17 = load i32, ptr %16, align 4 + %18 = getelementptr inbounds i32, ptr %0, i32 12 + %19 = load i32, ptr %18, align 4 + %20 = getelementptr inbounds i32, ptr %0, i32 13 + %21 = load i32, ptr %20, align 4 + %22 = getelementptr inbounds i32, ptr %0, i32 14 + %23 = load i32, ptr %22, align 4 + %24 = getelementptr inbounds i32, ptr %0, i32 15 + %25 = load i32, ptr %24, align 4 + %26 = load i32, ptr %0, align 4 + %27 = getelementptr inbounds i32, ptr %0, i32 1 + %28 = load i32, ptr %27, align 4 + %29 = add i32 %3, %5 + %30 = add i32 %7, %9 + %31 = add i32 %11, %13 + %32 = add i32 %15, %17 + %33 = add i32 %19, %21 + %34 = add i32 %23, %25 + %35 = add i32 %26, %28 + %36 = add i32 %29, %30 + %37 = add i32 %31, %32 + %38 = add i32 %33, %34 + %39 = add i32 %35, %36 + %40 = add i32 %37, %38 + %41 = add i32 %39, %40 + ret i32 %41 + } + + define i32 @reverse_order_loads(ptr %0) { + %2 = getelementptr inbounds i32, ptr %0, i32 1 + %3 = load i32, ptr %2, align 4 + %4 = load i32, ptr %0, align 4 + %5 = add i32 %3, %4 + ret i32 %5 + } + + define i32 @offset_calculation(ptr %0) { + %2 = getelementptr inbounds i8, ptr %0, i32 100 + %3 = load i32, ptr %2, align 4 + %4 = getelementptr inbounds i8, ptr %0, i32 104 + %5 = load i32, ptr %4, align 4 + %6 = add i32 %3, %5 + ret i32 %6 + } + + define i32 @large_offsets(ptr %0) { + %2 = getelementptr inbounds i8, ptr %0, i32 2040 + %3 = load i32, ptr %2, align 4 + %4 = getelementptr inbounds i8, ptr %0, i32 2044 + %5 = load i32, ptr %4, align 4 + %6 = add i32 %3, %5 + ret i32 %6 + } + + define i32 @negative_offsets(ptr %0) { + %2 = getelementptr inbounds i8, ptr %0, i32 -8 + %3 = load i32, ptr %2, align 4 + %4 = getelementptr inbounds i8, ptr %0, i32 -4 + %5 = load i32, ptr %4, align 4 + %6 = add i32 %3, %5 + ret i32 %6 + } + + define i32 @volatile_loads(ptr %0) { + %2 = load volatile i32, ptr %0, align 4 + %3 = getelementptr inbounds i32, ptr %0, i32 1 + %4 = load volatile i32, ptr %3, align 4 + %5 = add i32 %2, %4 + ret i32 %5 + } + + define i32 @store_dependency(ptr %0, i32 %1) { + %3 = load i32, ptr %0, align 4 + %4 = getelementptr inbounds i32, ptr %0, i32 1 + store i32 %1, ptr %4, align 4 + %5 = load i32, ptr %4, align 4 + %6 = add i32 %3, %5 + ret i32 %6 + } + + define i32 @three_loads(ptr %0) { + %2 = load i32, ptr %0, align 4 + %3 = getelementptr inbounds i32, ptr %0, i32 1 + %4 = load i32, ptr %3, align 4 + %5 = getelementptr inbounds i32, ptr %0, i32 2 + %6 = load i32, ptr %5, align 4 + %7 = add i32 %2, %4 + %8 = add i32 %7, %6 + ret i32 %8 + } + + define i32 @distance_exceeds_max(ptr %0, i32 %1) { + %3 = load i32, ptr %0, align 4 + %4 = add i32 %3, %1 + %5 = add i32 %4, %1 + %6 = add i32 %5, %1 + %7 = add i32 %6, %1 + %8 = add i32 %7, %1 + %9 = add i32 %8, %1 + %10 = add i32 %9, %1 + %11 = add i32 %10, %1 + %12 = add i32 %11, %1 + %13 = add i32 %12, %1 + %14 = add i32 %13, %1 + %15 = getelementptr inbounds i32, ptr %0, i32 1 + %16 = load i32, ptr %15, align 4 + %17 = add i32 %14, %16 + ret i32 %17 + } + + @global_var = external global [100 x i32] + + define i32 @symbolic_operands_global() { + ret i32 0 + } + + define i32 @symbolic_operands_different_globals() { + ret i32 0 + } + + define i32 @symbolic_operands_constantpool() { + ret i32 0 + } + + define i32 @symbolic_operands_interleave() { + ret i32 0 + } + + declare void @external(ptr) + define i32 @frame_index() { + %arr = alloca [2 x i32], align 4 + %arrayidx1 = getelementptr inbounds nuw i8, ptr %arr, i32 4 + ret i32 0 + } + + define i32 @frame_index_operands_interleave() { + %arr = alloca [2 x i32], align 4 + %arrayidx1 = getelementptr inbounds nuw i8, ptr %arr, i32 4 + ret i32 0 + } +--- +# Basic case: two consecutive 32-bit loads that can be combined into LD +name: basic_load_combine +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: basic_load_combine + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: basic_load_combine + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = LW %0, 0 :: (load (s32)) + %2:gpr = LW %0, 4 :: (load (s32)) + %3:gpr = ADD %1, %2 + PseudoRET + +... +--- +# Basic case: two consecutive 32-bit stores that can be combined into SD +name: basic_store_combine +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } + - { reg: '$x12', virtual-reg: '%2' } +body: | + bb.0: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: basic_store_combine + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: SW [[COPY1]], [[COPY]], 0 :: (store (s32)) + ; CHECK-NEXT: SW [[COPY2]], [[COPY]], 4 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: basic_store_combine + ; CHECK-4BYTE: liveins: $x10, $x11, $x12 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-4BYTE-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-4BYTE-NEXT: PseudoSD_RV32_OPT [[COPY1]], [[COPY2]], [[COPY]], 0 :: (store (s32)) + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + SW %1, %0, 0 :: (store (s32)) + SW %2, %0, 4 :: (store (s32)) + PseudoRET + +... +--- +# Basic case: two consecutive 32-bit store 0 that can be combined into SD +name: basic_store_zero_combine +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: basic_store_zero_combine + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: SW [[COPY1]], [[COPY]], 0 :: (store (s32)) + ; CHECK-NEXT: SW [[COPY1]], [[COPY]], 4 :: (store (s32)) + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: basic_store_zero_combine + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-4BYTE-NEXT: PseudoSD_RV32_OPT [[COPY1]], [[COPY1]], [[COPY]], 0 :: (store (s32)) + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x0 + SW %1, %0, 0 :: (store (s32)) + SW %1, %0, 4 :: (store (s32)) + PseudoRET + +... +--- +name: basic_load_combine_8_byte_aligned +alignment: 8 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: basic_load_combine_8_byte_aligned + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32), align 8), (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: basic_load_combine_8_byte_aligned + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32), align 8), (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = LW %0, 0 :: (load (s32), align 8) + %2:gpr = LW %0, 4 :: (load (s32)) + %3:gpr = ADD %1, %2 + PseudoRET + +... +--- +# Basic case: two consecutive 32-bit stores that can be combined into SD +name: basic_store_combine_8_byte_aligned +alignment: 8 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } + - { reg: '$x12', virtual-reg: '%2' } +body: | + bb.0: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: basic_store_combine_8_byte_aligned + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: PseudoSD_RV32_OPT [[COPY1]], [[COPY2]], [[COPY]], 0 :: (store (s32), align 8), (store (s32)) + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: basic_store_combine_8_byte_aligned + ; CHECK-4BYTE: liveins: $x10, $x11, $x12 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-4BYTE-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-4BYTE-NEXT: PseudoSD_RV32_OPT [[COPY1]], [[COPY2]], [[COPY]], 0 :: (store (s32), align 8), (store (s32)) + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + SW %1, %0, 0 :: (store (s32), align 8) + SW %2, %0, 4 :: (store (s32)) + PseudoRET + +... +--- +# Non-consecutive offsets - should not combine +name: non_consecutive_offsets +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: non_consecutive_offsets + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 8 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: non_consecutive_offsets + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 8 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; Should not combine - offset gap is 8, not 4 + %1:gpr = LW %0, 0 :: (load (s32)) + %2:gpr = LW %0, 8 :: (load (s32)) + %3:gpr = ADD %1, %2 + PseudoRET + +... +--- +# Different base registers - should not combine +name: different_base_regs +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: different_base_regs + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY1]], 4 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: different_base_regs + ; CHECK-4BYTE: liveins: $x10, $x11 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY1]], 4 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + ; Should not combine - different base registers + %2:gpr = LW %0, 0 :: (load (s32)) + %3:gpr = LW %1, 4 :: (load (s32)) + %4:gpr = ADD %2, %3 + PseudoRET + +... +--- +# Call instruction blocks optimization +name: call_blocks_optimization +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: call_blocks_optimization + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @external_func, csr_ilp32_lp64, implicit-def $x1 + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: call_blocks_optimization + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: PseudoCALL target-flags(riscv-call) @external_func, csr_ilp32_lp64, implicit-def $x1 + ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = LW %0, 0 :: (load (s32)) + ; Call instruction should block combining across it + PseudoCALL target-flags(riscv-call) @external_func, csr_ilp32_lp64, implicit-def $x1 + %2:gpr = LW %0, 4 :: (load (s32)) + %3:gpr = ADD %1, %2 + PseudoRET + +... +--- +# Terminator instruction blocks optimization +name: terminator_blocks_optimization +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } +body: | + ; CHECK-LABEL: name: terminator_blocks_optimization + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: BEQ [[COPY1]], [[LW]], %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: terminator_blocks_optimization + ; CHECK-4BYTE: bb.0: + ; CHECK-4BYTE-NEXT: successors: %bb.1(0x80000000) + ; CHECK-4BYTE-NEXT: liveins: $x10, $x11 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: BEQ [[COPY1]], [[LW]], %bb.1 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: bb.1: + ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-4BYTE-NEXT: PseudoRET + bb.0: + liveins: $x10, $x11 + + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = LW %0, 0 :: (load (s32)) + BEQ %1, %2, %bb.1 + + bb.1: + ; Should not combine across basic block boundary + %3:gpr = LW %0, 4 :: (load (s32)) + %4:gpr = ADD %2, %3 + PseudoRET + +... +--- +# Memory aliasing - store between loads with unknown base should prevent combining +name: memory_aliasing +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } + - { reg: '$x12', virtual-reg: '%2' } +body: | + bb.0: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: memory_aliasing + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: SW [[COPY1]], [[COPY2]], 8 :: (store (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: memory_aliasing + ; CHECK-4BYTE: liveins: $x10, $x11, $x12 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-4BYTE-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: SW [[COPY1]], [[COPY2]], 8 :: (store (s32)) + ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %3:gpr = LW %0, 0 :: (load (s32)) + SW %1, %2, 8 :: (store (s32)) + %4:gpr = LW %0, 4 :: (load (s32)) + %5:gpr = ADD %3, %4 + PseudoRET + +... +--- +# Multiple pairs in same function +name: multiple_pairs +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: multiple_pairs + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY1]], 8 :: (load (s32)) + ; CHECK-NEXT: [[LW3:%[0-9]+]]:gpr = LW [[COPY1]], 12 :: (load (s32)) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[LW2]], [[LW3]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD]], [[ADD1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: multiple_pairs + ; CHECK-4BYTE: liveins: $x10, $x11 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]] + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT2:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT3:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY1]], 8 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT2]], [[PseudoLD_RV32_OPT3]] + ; CHECK-4BYTE-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD]], [[ADD1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + ; First pair should combine + %2:gpr = LW %0, 0 :: (load (s32)) + %3:gpr = LW %0, 4 :: (load (s32)) + %4:gpr = ADD %2, %3 + + ; Second pair should also combine + %5:gpr = LW %1, 8 :: (load (s32)) + %6:gpr = LW %1, 12 :: (load (s32)) + %7:gpr = ADD %5, %6 + %8:gpr = ADD %4, %7 + PseudoRET + +... +--- +# Many loads test +name: many_loads +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: many_loads + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 16 :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 20 :: (load (s32)) + ; CHECK-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY]], 24 :: (load (s32)) + ; CHECK-NEXT: [[LW3:%[0-9]+]]:gpr = LW [[COPY]], 28 :: (load (s32)) + ; CHECK-NEXT: [[LW4:%[0-9]+]]:gpr = LW [[COPY]], 32 :: (load (s32)) + ; CHECK-NEXT: [[LW5:%[0-9]+]]:gpr = LW [[COPY]], 36 :: (load (s32)) + ; CHECK-NEXT: [[LW6:%[0-9]+]]:gpr = LW [[COPY]], 40 :: (load (s32)) + ; CHECK-NEXT: [[LW7:%[0-9]+]]:gpr = LW [[COPY]], 44 :: (load (s32)) + ; CHECK-NEXT: [[LW8:%[0-9]+]]:gpr = LW [[COPY]], 48 :: (load (s32)) + ; CHECK-NEXT: [[LW9:%[0-9]+]]:gpr = LW [[COPY]], 52 :: (load (s32)) + ; CHECK-NEXT: [[LW10:%[0-9]+]]:gpr = LW [[COPY]], 56 :: (load (s32)) + ; CHECK-NEXT: [[LW11:%[0-9]+]]:gpr = LW [[COPY]], 60 :: (load (s32)) + ; CHECK-NEXT: [[LW12:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: [[LW13:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[LW2]], [[LW3]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[LW4]], [[LW5]] + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD [[LW6]], [[LW7]] + ; CHECK-NEXT: [[ADD4:%[0-9]+]]:gpr = ADD [[LW8]], [[LW9]] + ; CHECK-NEXT: [[ADD5:%[0-9]+]]:gpr = ADD [[LW10]], [[LW11]] + ; CHECK-NEXT: [[ADD6:%[0-9]+]]:gpr = ADD [[LW12]], [[LW13]] + ; CHECK-NEXT: [[ADD7:%[0-9]+]]:gpr = ADD [[ADD]], [[ADD1]] + ; CHECK-NEXT: [[ADD8:%[0-9]+]]:gpr = ADD [[ADD2]], [[ADD3]] + ; CHECK-NEXT: [[ADD9:%[0-9]+]]:gpr = ADD [[ADD4]], [[ADD5]] + ; CHECK-NEXT: [[ADD10:%[0-9]+]]:gpr = ADD [[ADD6]], [[ADD7]] + ; CHECK-NEXT: [[ADD11:%[0-9]+]]:gpr = ADD [[ADD8]], [[ADD9]] + ; CHECK-NEXT: [[ADD12:%[0-9]+]]:gpr = ADD [[ADD10]], [[ADD11]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: many_loads + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 16 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT2:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT3:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 24 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT4:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT5:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 32 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT6:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT7:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 40 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT8:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT9:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 48 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT10:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT11:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 56 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT12:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT13:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]] + ; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT2]], [[PseudoLD_RV32_OPT3]] + ; CHECK-4BYTE-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT4]], [[PseudoLD_RV32_OPT5]] + ; CHECK-4BYTE-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT6]], [[PseudoLD_RV32_OPT7]] + ; CHECK-4BYTE-NEXT: [[ADD4:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT8]], [[PseudoLD_RV32_OPT9]] + ; CHECK-4BYTE-NEXT: [[ADD5:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT10]], [[PseudoLD_RV32_OPT11]] + ; CHECK-4BYTE-NEXT: [[ADD6:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT12]], [[PseudoLD_RV32_OPT13]] + ; CHECK-4BYTE-NEXT: [[ADD7:%[0-9]+]]:gpr = ADD [[ADD]], [[ADD1]] + ; CHECK-4BYTE-NEXT: [[ADD8:%[0-9]+]]:gpr = ADD [[ADD2]], [[ADD3]] + ; CHECK-4BYTE-NEXT: [[ADD9:%[0-9]+]]:gpr = ADD [[ADD4]], [[ADD5]] + ; CHECK-4BYTE-NEXT: [[ADD10:%[0-9]+]]:gpr = ADD [[ADD6]], [[ADD7]] + ; CHECK-4BYTE-NEXT: [[ADD11:%[0-9]+]]:gpr = ADD [[ADD8]], [[ADD9]] + ; CHECK-4BYTE-NEXT: [[ADD12:%[0-9]+]]:gpr = ADD [[ADD10]], [[ADD11]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; Create high register pressure with many live values + %1:gpr = LW %0, 16 :: (load (s32)) + %2:gpr = LW %0, 20 :: (load (s32)) + %3:gpr = LW %0, 24 :: (load (s32)) + %4:gpr = LW %0, 28 :: (load (s32)) + %5:gpr = LW %0, 32 :: (load (s32)) + %6:gpr = LW %0, 36 :: (load (s32)) + %7:gpr = LW %0, 40 :: (load (s32)) + %8:gpr = LW %0, 44 :: (load (s32)) + %9:gpr = LW %0, 48 :: (load (s32)) + %10:gpr = LW %0, 52 :: (load (s32)) + %11:gpr = LW %0, 56 :: (load (s32)) + %12:gpr = LW %0, 60 :: (load (s32)) + + ; With high register pressure, these loads might not be combined + ; depending on the profitability analysis + %13:gpr = LW %0, 0 :: (load (s32)) + %14:gpr = LW %0, 4 :: (load (s32)) + + ; Use all the loaded values to keep them live + %15:gpr = ADD %1, %2 + %16:gpr = ADD %3, %4 + %17:gpr = ADD %5, %6 + %18:gpr = ADD %7, %8 + %19:gpr = ADD %9, %10 + %20:gpr = ADD %11, %12 + %21:gpr = ADD %13, %14 + %22:gpr = ADD %15, %16 + %23:gpr = ADD %17, %18 + %24:gpr = ADD %19, %20 + %25:gpr = ADD %21, %22 + %26:gpr = ADD %23, %24 + %27:gpr = ADD %25, %26 + PseudoRET + +... +--- +# Test reverse order - second load has lower offset than first +name: reverse_order_loads +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: reverse_order_loads + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: reverse_order_loads + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT1]], [[PseudoLD_RV32_OPT]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; Load at higher offset first, then lower offset + ; Should still be combined as LD with lower offset + %1:gpr = LW %0, 4 :: (load (s32)) + %2:gpr = LW %0, 0 :: (load (s32)) + %3:gpr = ADD %1, %2 + PseudoRET + +... +--- +# Test with immediate offset calculation +name: offset_calculation +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: offset_calculation + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 100 :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 104 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: offset_calculation + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 100 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; Test with different immediate values that are consecutive + %1:gpr = LW %0, 100 :: (load (s32)) + %2:gpr = LW %0, 104 :: (load (s32)) + %3:gpr = ADD %1, %2 + PseudoRET + +... +--- +# Test large offset values +name: large_offsets +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: large_offsets + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 2040 :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 2044 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: large_offsets + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 2040 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; Test with large offset values + %1:gpr = LW %0, 2040 :: (load (s32)) + %2:gpr = LW %0, 2044 :: (load (s32)) + %3:gpr = ADD %1, %2 + PseudoRET + +... +--- +# Test with negative offsets +name: negative_offsets +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: negative_offsets + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], -8 :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], -4 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: negative_offsets + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], -8 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; Test with negative consecutive offsets + %1:gpr = LW %0, -8 :: (load (s32)) + %2:gpr = LW %0, -4 :: (load (s32)) + %3:gpr = ADD %1, %2 + PseudoRET + +... +--- +# Test with volatile loads - should not combine +name: volatile_loads +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: volatile_loads + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (volatile load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (volatile load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: volatile_loads + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (volatile load (s32)) + ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (volatile load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; Volatile loads should not be combined + %1:gpr = LW %0, 0 :: (volatile load (s32)) + %2:gpr = LW %0, 4 :: (volatile load (s32)) + %3:gpr = ADD %1, %2 + PseudoRET + +... +--- +# Test store dependency - store modifies same location as load +name: store_dependency +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: store_dependency + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: SW [[COPY1]], [[COPY]], 4 :: (store (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: store_dependency + ; CHECK-4BYTE: liveins: $x10, $x11 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: SW [[COPY1]], [[COPY]], 4 :: (store (s32)) + ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = LW %0, 0 :: (load (s32)) + ; Store to same location as second load - should prevent combination + SW %1, %0, 4 :: (store (s32)) + %3:gpr = LW %0, 4 :: (load (s32)) + %4:gpr = ADD %2, %3 + PseudoRET + +... +--- +# Test three loads: +# align 8: last two should combine +# align 4: first two should combine +name: three_loads +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: three_loads + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY]], 8 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[LW2]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: three_loads + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 8 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]] + ; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[LW]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; First two loads should combine, third should remain separate + %1:gpr = LW %0, 0 :: (load (s32)) + %2:gpr = LW %0, 4 :: (load (s32)) + %3:gpr = LW %0, 8 :: (load (s32)) + %4:gpr = ADD %1, %2 + %5:gpr = ADD %4, %3 + PseudoRET +... +--- +# Test where distance between loads exceeds MaxRescheduleDistance +name: distance_exceeds_max +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: distance_exceeds_max + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[COPY1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[COPY1]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD1]], [[COPY1]] + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD [[ADD2]], [[COPY1]] + ; CHECK-NEXT: [[ADD4:%[0-9]+]]:gpr = ADD [[ADD3]], [[COPY1]] + ; CHECK-NEXT: [[ADD5:%[0-9]+]]:gpr = ADD [[ADD4]], [[COPY1]] + ; CHECK-NEXT: [[ADD6:%[0-9]+]]:gpr = ADD [[ADD5]], [[COPY1]] + ; CHECK-NEXT: [[ADD7:%[0-9]+]]:gpr = ADD [[ADD6]], [[COPY1]] + ; CHECK-NEXT: [[ADD8:%[0-9]+]]:gpr = ADD [[ADD7]], [[COPY1]] + ; CHECK-NEXT: [[ADD9:%[0-9]+]]:gpr = ADD [[ADD8]], [[COPY1]] + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: distance_exceeds_max + ; CHECK-4BYTE: liveins: $x10, $x11 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[COPY1]] + ; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[COPY1]] + ; CHECK-4BYTE-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD1]], [[COPY1]] + ; CHECK-4BYTE-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD [[ADD2]], [[COPY1]] + ; CHECK-4BYTE-NEXT: [[ADD4:%[0-9]+]]:gpr = ADD [[ADD3]], [[COPY1]] + ; CHECK-4BYTE-NEXT: [[ADD5:%[0-9]+]]:gpr = ADD [[ADD4]], [[COPY1]] + ; CHECK-4BYTE-NEXT: [[ADD6:%[0-9]+]]:gpr = ADD [[ADD5]], [[COPY1]] + ; CHECK-4BYTE-NEXT: [[ADD7:%[0-9]+]]:gpr = ADD [[ADD6]], [[COPY1]] + ; CHECK-4BYTE-NEXT: [[ADD8:%[0-9]+]]:gpr = ADD [[ADD7]], [[COPY1]] + ; CHECK-4BYTE-NEXT: [[ADD9:%[0-9]+]]:gpr = ADD [[ADD8]], [[COPY1]] + ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = LW %0, 0 :: (load (s32)) + ; Insert 11 instructions between the two loads + ; This makes the distance greater than the configured MaxRescheduleDistance + %3:gpr = ADD %2, %1 + %4:gpr = ADD %3, %1 + %5:gpr = ADD %4, %1 + %6:gpr = ADD %5, %1 + %7:gpr = ADD %6, %1 + %8:gpr = ADD %7, %1 + %9:gpr = ADD %8, %1 + %10:gpr = ADD %9, %1 + %11:gpr = ADD %10, %1 + %12:gpr = ADD %11, %1 + ; Second load at offset 4 - too far from first load + %14:gpr = LW %0, 4 :: (load (s32)) + PseudoRET +... +--- +# Test combining loads with symbolic operands (global address) +name: symbolic_operands_global +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: symbolic_operands_global + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) @global_var + 4 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: symbolic_operands_global + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; Two consecutive loads with symbolic global address operands + %1:gpr = LW %0, target-flags(riscv-lo) @global_var :: (load (s32)) + %2:gpr = LW %0, target-flags(riscv-lo) @global_var + 4 :: (load (s32)) + %3:gpr = ADD %1, %2 + PseudoRET + +... +--- +# Test that loads with different global symbols are not combined +name: symbolic_operands_different_globals +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +stack: + - { id: 0, offset: -4, size: 4 } +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: symbolic_operands_different_globals + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], %stack.0 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: symbolic_operands_different_globals + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], %stack.0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; Should not combine - different symbol types + %1:gpr = LW %0, target-flags(riscv-lo) @global_var :: (load (s32)) + %2:gpr = LW %0, %stack.0 :: (load (s32)) + %3:gpr = ADD %1, %2 + PseudoRET + +... +--- +# Test combining loads with constant pool operands +name: symbolic_operands_constantpool +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } +constants: + - id: 0 + value: 'double 3.140000e+00' + alignment: 8 +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: symbolic_operands_constantpool + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) %const.0 :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) %const.0 + 4 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW1]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: symbolic_operands_constantpool + ; CHECK-4BYTE: liveins: $x10 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], target-flags(riscv-lo) %const.0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + ; Two consecutive loads with constant pool operands + %1:gpr = LW %0, target-flags(riscv-lo) %const.0 :: (load (s32)) + %2:gpr = LW %0, target-flags(riscv-lo) %const.0 + 4 :: (load (s32)) + %3:gpr = ADD %1, %2 + PseudoRET + +... +--- +name: symbolic_operands_interleave +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: symbolic_operands_interleave + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32)) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: [[LW3:%[0-9]+]]:gpr = LW [[COPY]], target-flags(riscv-lo) @global_var + 4 :: (load (s32)) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW2]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[LW1]], [[LW3]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: symbolic_operands_interleave + ; CHECK-4BYTE: liveins: $x10, $x11 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], target-flags(riscv-lo) @global_var :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT2:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT3:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT2]] + ; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT3]], [[PseudoLD_RV32_OPT1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = LW %0, target-flags(riscv-lo) @global_var :: (load (s32)) + %3:gpr = LW %0, 4 :: (load (s32)) + %4:gpr = LW %0, 0 :: (load (s32)) + %5:gpr = LW %0, target-flags(riscv-lo) @global_var + 4 :: (load (s32)) + %6:gpr = ADD %2, %4 + %7:gpr = ADD %3, %5 + PseudoRET + +... +--- +name: frame_index +alignment: 4 +tracksRegLiveness: true +stack: + - { id: 0, offset: 0, size: 8, alignment: 4 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: frame_index + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SW [[COPY]], %stack.0, 0 :: (store (s32) into %ir.arr) + ; CHECK-NEXT: SW [[COPY1]], %stack.0, 4 :: (store (s32) into %ir.arrayidx1) + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: frame_index + ; CHECK-4BYTE: liveins: $x10, $x11 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-4BYTE-NEXT: PseudoSD_RV32_OPT [[COPY]], [[COPY1]], %stack.0, 0 :: (store (s32) into %ir.arr), (store (s32) into %ir.arrayidx1) + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + SW %0:gpr, %stack.0, 0 :: (store (s32) into %ir.arr) + SW %1:gpr, %stack.0, 4 :: (store (s32) into %ir.arrayidx1) + PseudoRET +... +--- +name: frame_index_operands_interleave +alignment: 4 +tracksRegLiveness: true +stack: + - { id: 0, offset: 0, size: 8, alignment: 4 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: frame_index_operands_interleave + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW %stack.0, 0 :: (load (s32) from %ir.arr) + ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32)) + ; CHECK-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: [[LW3:%[0-9]+]]:gpr = LW %stack.0, 4 :: (load (s32) from %ir.arrayidx1) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[LW]], [[LW2]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[LW1]], [[LW3]] + ; CHECK-NEXT: PseudoRET + ; + ; CHECK-4BYTE-LABEL: name: frame_index_operands_interleave + ; CHECK-4BYTE: liveins: $x10, $x11 + ; CHECK-4BYTE-NEXT: {{ $}} + ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT1:%[0-9]+]]:gpr = PseudoLD_RV32_OPT %stack.0, 0 :: (load (s32) from %ir.arr), (load (s32) from %ir.arrayidx1) + ; CHECK-4BYTE-NEXT: [[PseudoLD_RV32_OPT2:%[0-9]+]]:gpr, [[PseudoLD_RV32_OPT3:%[0-9]+]]:gpr = PseudoLD_RV32_OPT [[COPY]], 0 :: (load (s32)) + ; CHECK-4BYTE-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT]], [[PseudoLD_RV32_OPT2]] + ; CHECK-4BYTE-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[PseudoLD_RV32_OPT3]], [[PseudoLD_RV32_OPT1]] + ; CHECK-4BYTE-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = LW %stack.0, 0 :: (load (s32) from %ir.arr) + %3:gpr = LW %0, 4 :: (load (s32)) + %4:gpr = LW %0, 0 :: (load (s32)) + %5:gpr = LW %stack.0, 4 :: (load (s32) from %ir.arrayidx1) + %6:gpr = ADD %2, %4 + %7:gpr = ADD %3, %5 + PseudoRET + +... diff --git a/third_party/llvm/llvm/test/CodeGen/RISCV/zilsd-regalloc-hints.mir b/third_party/llvm/llvm/test/CodeGen/RISCV/zilsd-regalloc-hints.mir new file mode 100644 index 0000000..7b2ce62 --- /dev/null +++ b/third_party/llvm/llvm/test/CodeGen/RISCV/zilsd-regalloc-hints.mir @@ -0,0 +1,83 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv32 -mattr=+zilsd -run-pass=greedy,virtregrewriter %s -o - | FileCheck --check-prefix=WITHOUT-HINT %s +# RUN: llc -mtriple=riscv32 -mattr=+zilsd,+zilsd-word-align -run-pass=riscv-prera-zilsd-opt,greedy,virtregrewriter %s -o - | FileCheck --check-prefix=WITH-HINT %s + +--- | + define i32 @test_load_pair_hints(ptr %p) { + %v1 = load i32, ptr %p, align 4 + %p2 = getelementptr inbounds i8, ptr %p, i32 4 + %v2 = load i32, ptr %p2, align 4 + %sum = add i32 %v1, %v2 + ret i32 %sum + } + + define void @test_store_pair_hints(ptr %p, i32 %a, i32 %b) { + store i32 %a, ptr %p, align 4 + %p2 = getelementptr inbounds i8, ptr %p, i32 4 + store i32 %b, ptr %p2, align 4 + ret void + } +... +--- +# Test that load pairs get register hints and allocate consecutive registers +# After register allocation, should either keep LD_RV32 or split back to LW +name: test_load_pair_hints +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; WITHOUT-HINT-LABEL: name: test_load_pair_hints + ; WITHOUT-HINT: liveins: $x10 + ; WITHOUT-HINT-NEXT: {{ $}} + ; WITHOUT-HINT-NEXT: renamable $x11 = LW renamable $x10, 0 :: (load (s32) from %ir.p) + ; WITHOUT-HINT-NEXT: renamable $x10 = LW killed renamable $x10, 4 :: (load (s32) from %ir.p2) + ; WITHOUT-HINT-NEXT: renamable $x10 = ADD killed renamable $x11, killed renamable $x10 + ; WITHOUT-HINT-NEXT: PseudoRET implicit $x10 + ; + ; WITH-HINT-LABEL: name: test_load_pair_hints + ; WITH-HINT: liveins: $x10 + ; WITH-HINT-NEXT: {{ $}} + ; WITH-HINT-NEXT: renamable $x10, renamable $x11 = PseudoLD_RV32_OPT killed renamable $x10, 0 :: (load (s32) from %ir.p), (load (s32) from %ir.p2) + ; WITH-HINT-NEXT: renamable $x10 = ADD killed renamable $x10, killed renamable $x11 + ; WITH-HINT-NEXT: PseudoRET implicit $x10 + %10:gpr = COPY $x10 + ; These two LW instructions at offset 0 and 4 should be combined + %0:gpr = LW %10, 0 :: (load (s32) from %ir.p) + %1:gpr = LW %10, 4 :: (load (s32) from %ir.p2) + %2:gpr = ADD %0, %1 + $x10 = COPY %2 + PseudoRET implicit $x10 + +... +--- +# Test that store pairs get register hints and allocate consecutive registers +# After register allocation, should either keep SD_RV32 or split back to SW +name: test_store_pair_hints +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12 + + ; WITHOUT-HINT-LABEL: name: test_store_pair_hints + ; WITHOUT-HINT: liveins: $x10, $x11, $x12 + ; WITHOUT-HINT-NEXT: {{ $}} + ; WITHOUT-HINT-NEXT: SW killed renamable $x11, renamable $x10, 0 :: (store (s32) into %ir.p) + ; WITHOUT-HINT-NEXT: SW killed renamable $x12, killed renamable $x10, 4 :: (store (s32) into %ir.p2) + ; WITHOUT-HINT-NEXT: PseudoRET + ; + ; WITH-HINT-LABEL: name: test_store_pair_hints + ; WITH-HINT: liveins: $x10, $x11, $x12 + ; WITH-HINT-NEXT: {{ $}} + ; WITH-HINT-NEXT: renamable $x14 = COPY $x11 + ; WITH-HINT-NEXT: renamable $x15 = COPY $x12 + ; WITH-HINT-NEXT: PseudoSD_RV32_OPT killed renamable $x14, killed renamable $x15, killed renamable $x10, 0 :: (store (s32) into %ir.p), (store (s32) into %ir.p2) + ; WITH-HINT-NEXT: PseudoRET + %10:gpr = COPY $x10 + %11:gpr = COPY $x11 + %12:gpr = COPY $x12 + ; These two SW instructions at offset 0 and 4 should be combined + SW %11, %10, 0 :: (store (s32) into %ir.p) + SW %12, %10, 4 :: (store (s32) into %ir.p2) + PseudoRET +... -- cgit v1.2.3