From e16de95dce32f077361577377d5c52fc4ad78339 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Fri, 7 Aug 2026 02:15:09 +0800
Subject: [RISCV] Add generated RV64GC register description

Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
---
 backend/CMakeLists.txt | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'backend/CMakeLists.txt')

diff --git a/backend/CMakeLists.txt b/backend/CMakeLists.txt
index 0f983d0..aa4afe6 100644
--- a/backend/CMakeLists.txt
+++ b/backend/CMakeLists.txt
@@ -54,6 +54,8 @@ endif()
 rcc_backend_initialize_toolchain()
 
 add_subdirectory(lib)
+add_subdirectory(tools)
+add_subdirectory(lib/Target)
 
 if(RCC_BACKEND_BUILD_TESTS)
   enable_testing()
-- 
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