From 97e5fbaa55b4672db36123c2425d05a4738452ab Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Fri, 14 Aug 2026 20:35:54 +0800
Subject: [GlobalISel] Match LLVM legalization value tracking

---
 backend/include/rcc/CodeGen/GlobalISel/Utils.h | 54 ++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 backend/include/rcc/CodeGen/GlobalISel/Utils.h

(limited to 'backend/include/rcc/CodeGen/GlobalISel/Utils.h')

diff --git a/backend/include/rcc/CodeGen/GlobalISel/Utils.h b/backend/include/rcc/CodeGen/GlobalISel/Utils.h
new file mode 100644
index 0000000..5af2fb4
--- /dev/null
+++ b/backend/include/rcc/CodeGen/GlobalISel/Utils.h
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#ifndef RCC_CODEGEN_GLOBALISEL_UTILS_H
+#define RCC_CODEGEN_GLOBALISEL_UTILS_H
+
+#include "rcc/CodeGen/LowLevelType.h"
+#include "rcc/CodeGen/Register.h"
+#include "rcc/Support/Error.h"
+
+#include <cstddef>
+#include <span>
+#include <vector>
+
+namespace rcc {
+
+class MachineIRBuilder;
+class MachineInstr;
+class MachineRegisterInfo;
+class TargetDescription;
+
+/// Check whether an instruction only defines dead virtual registers and has no
+/// observable side effects.
+[[nodiscard]] bool isTriviallyDead(const MachineInstr &Instruction,
+                                   const MachineRegisterInfo &MRI,
+                                   const TargetDescription &Target) noexcept;
+
+[[nodiscard]] Expected<void> eraseInstrs(std::span<MachineInstr *const> Instructions,
+                                         MachineRegisterInfo &MRI,
+                                         const TargetDescription &Target);
+
+[[nodiscard]] Expected<void> eraseInstr(MachineInstr &Instruction,
+                                        MachineRegisterInfo &MRI,
+                                        const TargetDescription &Target);
+
+[[nodiscard]] Expected<void> extractParts(Register Reg, LowLevelType Type,
+                                          int PartCount,
+                                          std::vector<Register> &Parts,
+                                          MachineIRBuilder &MIRBuilder,
+                                          MachineRegisterInfo &MRI);
+
+[[nodiscard]] Expected<bool>
+extractParts(Register Reg, LowLevelType RegisterType, LowLevelType MainType,
+             LowLevelType &LeftoverType, std::vector<Register> &Parts,
+             std::vector<Register> &LeftoverParts,
+             MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI);
+
+[[nodiscard]] Expected<LowLevelType> getLCMType(LowLevelType OriginalType,
+                                                LowLevelType TargetType);
+[[nodiscard]] Expected<LowLevelType> getGCDType(LowLevelType OriginalType,
+                                                LowLevelType TargetType);
+
+} // namespace rcc
+
+#endif // RCC_CODEGEN_GLOBALISEL_UTILS_H
-- 
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