From b85a348ab7bdd878fd975121fc2501625eceec95 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Fri, 14 Aug 2026 22:37:46 +0800 Subject: [GlobalISel] Legalize G_ABS --- backend/include/rcc/CodeGen/GlobalISel/Utils.h | 46 ++++++++++++++------------ 1 file changed, 25 insertions(+), 21 deletions(-) (limited to 'backend/include/rcc/CodeGen/GlobalISel/Utils.h') diff --git a/backend/include/rcc/CodeGen/GlobalISel/Utils.h b/backend/include/rcc/CodeGen/GlobalISel/Utils.h index 5af2fb4..f252454 100644 --- a/backend/include/rcc/CodeGen/GlobalISel/Utils.h +++ b/backend/include/rcc/CodeGen/GlobalISel/Utils.h @@ -3,11 +3,13 @@ #ifndef RCC_CODEGEN_GLOBALISEL_UTILS_H #define RCC_CODEGEN_GLOBALISEL_UTILS_H +#include "rcc/ADT/APInt.h" #include "rcc/CodeGen/LowLevelType.h" #include "rcc/CodeGen/Register.h" #include "rcc/Support/Error.h" #include +#include #include #include @@ -18,36 +20,38 @@ class MachineInstr; class MachineRegisterInfo; class TargetDescription; +struct ValueAndVReg final { + APInt Value; + Register VReg; +}; + +[[nodiscard]] std::optional +getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, + bool LookThroughInstrs = true); + /// Check whether an instruction only defines dead virtual registers and has no /// observable side effects. -[[nodiscard]] bool isTriviallyDead(const MachineInstr &Instruction, - const MachineRegisterInfo &MRI, +[[nodiscard]] bool isTriviallyDead(const MachineInstr &Instruction, const MachineRegisterInfo &MRI, const TargetDescription &Target) noexcept; [[nodiscard]] Expected eraseInstrs(std::span Instructions, - MachineRegisterInfo &MRI, - const TargetDescription &Target); + MachineRegisterInfo &MRI, const TargetDescription &Target); -[[nodiscard]] Expected eraseInstr(MachineInstr &Instruction, - MachineRegisterInfo &MRI, +[[nodiscard]] Expected eraseInstr(MachineInstr &Instruction, MachineRegisterInfo &MRI, const TargetDescription &Target); -[[nodiscard]] Expected extractParts(Register Reg, LowLevelType Type, - int PartCount, +[[nodiscard]] Expected extractParts(Register Reg, LowLevelType Type, int PartCount, std::vector &Parts, - MachineIRBuilder &MIRBuilder, - MachineRegisterInfo &MRI); - -[[nodiscard]] Expected -extractParts(Register Reg, LowLevelType RegisterType, LowLevelType MainType, - LowLevelType &LeftoverType, std::vector &Parts, - std::vector &LeftoverParts, - MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI); - -[[nodiscard]] Expected getLCMType(LowLevelType OriginalType, - LowLevelType TargetType); -[[nodiscard]] Expected getGCDType(LowLevelType OriginalType, - LowLevelType TargetType); + MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI); + +[[nodiscard]] Expected extractParts(Register Reg, LowLevelType RegisterType, + LowLevelType MainType, LowLevelType &LeftoverType, + std::vector &Parts, + std::vector &LeftoverParts, + MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI); + +[[nodiscard]] Expected getLCMType(LowLevelType OriginalType, LowLevelType TargetType); +[[nodiscard]] Expected getGCDType(LowLevelType OriginalType, LowLevelType TargetType); } // namespace rcc -- cgit v1.2.3