From c759cebef15bdac2ef160065efd116fe6ed540a7 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Sat, 1 Aug 2026 05:27:13 +0800 Subject: [CodeGen] Build the core MachineIR object model Add arena-owned, address-stable MachineFunction, MachineBasicBlock, and MachineInstr nodes with intrusive layout and instruction lists. Model every required MachineOperand category, reciprocal ties, source state, and immutable per-instruction memory references. Implement physical and virtual register def-use chains whose back-links survive operand vector moves, plus vreg properties, tombstones, live-ins, reserved registers, and atomic CFG updates. Exercise ownership, reallocation, unlink/relink, cross-function rejection, and sanitizer paths. --- backend/include/rcc/CodeGen/MachineMemOperand.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'backend/include/rcc/CodeGen/MachineMemOperand.h') diff --git a/backend/include/rcc/CodeGen/MachineMemOperand.h b/backend/include/rcc/CodeGen/MachineMemOperand.h index 52514f9..e513385 100644 --- a/backend/include/rcc/CodeGen/MachineMemOperand.h +++ b/backend/include/rcc/CodeGen/MachineMemOperand.h @@ -207,6 +207,12 @@ struct MachineMemOperandDesc final { class MachineMemOperand final { public: + MachineMemOperand(const MachineMemOperand &) = default; + MachineMemOperand &operator=(const MachineMemOperand &) = default; + MachineMemOperand(MachineMemOperand &&) noexcept = default; + MachineMemOperand &operator=(MachineMemOperand &&) noexcept = default; + ~MachineMemOperand() = default; + [[nodiscard]] static Expected create(MachineMemOperandDesc Description); [[nodiscard]] const MachineMemOperandDesc &description() const noexcept { -- cgit v1.2.3