From f8daf08aba1f09c3024a70d3426891112d1662a2 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Wed, 12 Aug 2026 21:35:21 +0800
Subject: [RISCV] Consolidate instruction behavior in RISCVInstrInfo

---
 backend/include/rcc/CodeGen/MachineOptimizationPipeline.h | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'backend/include/rcc/CodeGen/MachineOptimizationPipeline.h')

diff --git a/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h b/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h
index 2cf1bcd..10bcbc6 100644
--- a/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h
+++ b/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h
@@ -13,16 +13,14 @@ class TargetMachineCombinerInfo;
 class TargetMemoryFoldingInfo;
 class TargetPseudoExpansionInfo;
 class TargetSchedulingModel;
-class TargetSSAInfo;
 
 struct MachineOptimizationPipelineTargetInfo final {
-  const TargetSSAInfo &SSA;
+  const TargetInstrInfo &InstrInfo;
   const TargetMachineCombinerInfo &Combiner;
   const TargetMemoryFoldingInfo &MemoryFolding;
   const TargetFrameLowering &FrameLowering;
   const TargetPseudoExpansionInfo &PseudoExpansion;
   const TargetSchedulingModel &SchedulingModel;
-  const TargetInstrInfo &BranchInfo;
 };
 
 [[nodiscard]] Expected<void> registerMachineOptimizationAnalyses(MachineAnalysisManager &Analyses);
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