From 19d8e4f562a8583b002dbaa837ec0083e7768a4f Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Sat, 1 Aug 2026 13:24:09 +0800
Subject: [CodeGen] Add strict MachineIR verification

Verify arena catalogs, intrusive layouts, reciprocal CFG edges, operand ownership, exact def-use coverage, instruction descriptors, pseudo deadlines, and MachineFunctionProperties. Preserve monotonic-arena history while rejecting detached objects that retain live state.
---
 backend/include/rcc/CodeGen/MachineRegisterInfo.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'backend/include/rcc/CodeGen/MachineRegisterInfo.h')

diff --git a/backend/include/rcc/CodeGen/MachineRegisterInfo.h b/backend/include/rcc/CodeGen/MachineRegisterInfo.h
index 495853a..da0f530 100644
--- a/backend/include/rcc/CodeGen/MachineRegisterInfo.h
+++ b/backend/include/rcc/CodeGen/MachineRegisterInfo.h
@@ -108,6 +108,9 @@ public:
   [[nodiscard]] Expected<void> eraseVirtualRegister(Register Reg);
 
   [[nodiscard]] bool isKnownVirtualRegister(Register Reg) const noexcept;
+  [[nodiscard]] std::span<const VirtualRegisterInfo> virtualRegisters() const noexcept {
+    return VirtualRegisters;
+  }
   [[nodiscard]] Expected<std::reference_wrapper<VirtualRegisterInfo>>
   virtualRegisterInfo(Register Reg);
   [[nodiscard]] Expected<std::reference_wrapper<const VirtualRegisterInfo>>
@@ -146,6 +149,7 @@ public:
   [[nodiscard]] Expected<std::size_t> replaceRegWith(Register OldReg, Register NewReg);
 
   [[nodiscard]] Expected<void> verifyDefUseChains() const;
+  [[nodiscard]] bool isLinkedOperand(const MachineOperand &Operand) const noexcept;
 
 private:
   struct RegOperandListHead final {
-- 
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