From 1ef9d699d3160a9f79e89f423352fbb8d43e70d7 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Thu, 13 Aug 2026 19:04:49 +0800 Subject: [RISCV] Match LLVM register bank mappings --- backend/include/rcc/CodeGen/MachineRegisterInfo.h | 1 + 1 file changed, 1 insertion(+) (limited to 'backend/include/rcc/CodeGen/MachineRegisterInfo.h') diff --git a/backend/include/rcc/CodeGen/MachineRegisterInfo.h b/backend/include/rcc/CodeGen/MachineRegisterInfo.h index cc9026e..524ee77 100644 --- a/backend/include/rcc/CodeGen/MachineRegisterInfo.h +++ b/backend/include/rcc/CodeGen/MachineRegisterInfo.h @@ -145,6 +145,7 @@ public: } [[nodiscard]] RegOperandRange regOperands(Register Reg) noexcept; + [[nodiscard]] RegOperandRange regOperands(Register Reg) const noexcept; [[nodiscard]] RegOperandRange regNoDebugOperands(Register Reg) noexcept; [[nodiscard]] RegOperandRange useOperands(Register Reg, bool IncludeDebug = true) noexcept; [[nodiscard]] RegOperandRange defOperands(Register Reg) noexcept; -- cgit v1.2.3