From da8bc76b4bf7d1a7b025d6c8ef5809551467dcc7 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Sun, 9 Aug 2026 13:23:48 +0800
Subject: [CodeGen] Implement RV64GC frame lowering

---
 backend/include/rcc/CodeGen/RegisterScavenger.h | 42 +++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 backend/include/rcc/CodeGen/RegisterScavenger.h

(limited to 'backend/include/rcc/CodeGen/RegisterScavenger.h')

diff --git a/backend/include/rcc/CodeGen/RegisterScavenger.h b/backend/include/rcc/CodeGen/RegisterScavenger.h
new file mode 100644
index 0000000..6351b98
--- /dev/null
+++ b/backend/include/rcc/CodeGen/RegisterScavenger.h
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#ifndef RCC_CODEGEN_REGISTERSCAVENGER_H
+#define RCC_CODEGEN_REGISTERSCAVENGER_H
+
+#include "rcc/CodeGen/Register.h"
+#include "rcc/Support/Error.h"
+
+#include <span>
+
+namespace rcc {
+
+class MachineFunction;
+class MachineInstr;
+class TargetDescription;
+
+struct ScavengedRegister final {
+  PhysicalRegister Reg;
+  bool RequiresSpill = false;
+};
+
+class RegisterScavenger final {
+public:
+  RegisterScavenger(const MachineFunction &Function, const TargetDescription &Target) noexcept
+      : Function(&Function), Target(&Target) {}
+
+  [[nodiscard]] Expected<ScavengedRegister>
+  scavenge(const MachineInstr &Instruction, std::span<const PhysicalRegister> Candidates) const;
+
+private:
+  [[nodiscard]] Expected<bool> isLiveBefore(const MachineInstr &Instruction,
+                                            PhysicalRegister Reg) const;
+  [[nodiscard]] bool instructionUses(const MachineInstr &Instruction,
+                                     PhysicalRegister Reg) const noexcept;
+
+  const MachineFunction *Function;
+  const TargetDescription *Target;
+};
+
+} // namespace rcc
+
+#endif // RCC_CODEGEN_REGISTERSCAVENGER_H
-- 
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