From 495c675771f43cfa12ab7a426a538be72fec1805 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Sun, 9 Aug 2026 17:03:19 +0800
Subject: [CodeGen] Implement machine optimization and scheduling

---
 backend/include/rcc/CodeGen/TargetBranchInfo.h | 66 ++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 backend/include/rcc/CodeGen/TargetBranchInfo.h

(limited to 'backend/include/rcc/CodeGen/TargetBranchInfo.h')

diff --git a/backend/include/rcc/CodeGen/TargetBranchInfo.h b/backend/include/rcc/CodeGen/TargetBranchInfo.h
new file mode 100644
index 0000000..39c5122
--- /dev/null
+++ b/backend/include/rcc/CodeGen/TargetBranchInfo.h
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#ifndef RCC_CODEGEN_TARGETBRANCHINFO_H
+#define RCC_CODEGEN_TARGETBRANCHINFO_H
+
+#include "rcc/Support/Error.h"
+
+#include <cstdint>
+#include <optional>
+
+namespace rcc {
+
+class MachineBasicBlock;
+class MachineFunction;
+class MachineInstr;
+class TargetDescription;
+
+struct MachineBranchAnalysis final {
+  MachineInstr *Conditional = nullptr;
+  MachineInstr *Unconditional = nullptr;
+  MachineBasicBlock *TrueTarget = nullptr;
+  MachineBasicBlock *FalseTarget = nullptr;
+  bool HasUnanalyzableTerminator = false;
+};
+
+class TargetBranchInfo {
+public:
+  virtual ~TargetBranchInfo() = default;
+
+  [[nodiscard]] virtual Expected<MachineBranchAnalysis>
+  analyzeBranch(MachineBasicBlock &Block, MachineFunction &Function,
+                const TargetDescription &Target) const = 0;
+  [[nodiscard]] virtual Expected<void>
+  reverseBranchCondition(MachineInstr &Branch, MachineBasicBlock &NewTarget,
+                         MachineFunction &Function, const TargetDescription &Target) const = 0;
+  [[nodiscard]] virtual Expected<void> removeBranch(MachineInstr &Branch, MachineFunction &Function,
+                                                    const TargetDescription &Target) const = 0;
+  [[nodiscard]] virtual Expected<bool>
+  rewriteBranchTarget(MachineBasicBlock &Block, MachineBasicBlock &OldTarget,
+                      MachineBasicBlock &NewTarget, MachineFunction &Function,
+                      const TargetDescription &Target) const = 0;
+  [[nodiscard]] virtual Expected<MachineInstr *>
+  insertUnconditionalBranch(MachineBasicBlock &Block, MachineBasicBlock &TargetBlock,
+                            MachineFunction &Function, const TargetDescription &Target) const = 0;
+
+  [[nodiscard]] virtual Expected<std::uint32_t>
+  instructionSize(const MachineInstr &Instruction, const MachineFunction &Function,
+                  const TargetDescription &Target) const = 0;
+  [[nodiscard]] virtual Expected<MachineBasicBlock *>
+  branchTarget(MachineInstr &Instruction, MachineFunction &Function,
+               const TargetDescription &Target) const = 0;
+  [[nodiscard]] virtual Expected<std::optional<bool>>
+  evaluateBranchCondition(const MachineInstr &, const MachineFunction &,
+                          const TargetDescription &) const {
+    return std::optional<bool>{};
+  }
+  [[nodiscard]] virtual bool isBranchOffsetInRange(const MachineInstr &Instruction,
+                                                   std::int64_t Offset) const noexcept = 0;
+  [[nodiscard]] virtual Expected<bool> relaxBranch(MachineInstr &Instruction, std::int64_t Offset,
+                                                   MachineFunction &Function,
+                                                   const TargetDescription &Target) const = 0;
+};
+
+} // namespace rcc
+
+#endif // RCC_CODEGEN_TARGETBRANCHINFO_H
-- 
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