From 77884c967d1cbc48afcbaef7e5a35adcb3c5da1b Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Sat, 8 Aug 2026 04:14:34 +0800 Subject: [CodeGen] Implement machine SSA exit --- backend/include/rcc/CodeGen/TargetDescription.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'backend/include/rcc/CodeGen/TargetDescription.h') diff --git a/backend/include/rcc/CodeGen/TargetDescription.h b/backend/include/rcc/CodeGen/TargetDescription.h index c2a4133..7e41a58 100644 --- a/backend/include/rcc/CodeGen/TargetDescription.h +++ b/backend/include/rcc/CodeGen/TargetDescription.h @@ -72,6 +72,9 @@ public: std::span MemOperands) const; [[nodiscard]] Expected validateInstruction(const MachineInstr &Instruction, const MachineRegisterInfo &RegInfo) const; + [[nodiscard]] Expected validateTieCompatibility(const MachineOperand &Def, + const MachineOperand &Use, + const MachineRegisterInfo &RegInfo) const; [[nodiscard]] Expected validateCFIInfo(const MachineCFIInfo &Info) const; [[nodiscard]] Expected validateFrameInfo(const MachineFrameInfo &Info) const; [[nodiscard]] Expected validateRegisterInfo(const MachineRegisterInfo &RegInfo) const; @@ -95,10 +98,6 @@ private: const VirtualRegisterInfo &Info) const; [[nodiscard]] std::optional effectiveRegisterClass(const MachineOperand &Operand, const MachineRegisterInfo &RegInfo) const; - [[nodiscard]] Expected validateTieCompatibility(const MachineOperand &Def, - const MachineOperand &Use, - const MachineRegisterInfo &RegInfo) const; - InstructionSet Instructions; TargetRegisterInfo Registers; TargetMIRTextInfo MIRText; -- cgit v1.2.3